Multi-channel rapid switching circulation excitation device for inducing seismic waves in rock friction experiment

Abstract

The invention discloses a multi-channel rapid switching circulation excitation device for inducing seismic waves in a rock friction experiment, which comprises a low-voltage logic control circuit and a high-voltage square wave power transmitting circuit, and is characterized in that the low-voltage logic control circuit comprises a CPLD (Complex Programmable Logic Device) main controller circuit, a USB2.0 logic circuit and an isolation control circuit; the USB2.0 logic circuit and the isolation control circuit are both connected with the CLPD main control circuit, the low-voltage logic control circuit is connected with the high-voltage square wave power transmitting circuit, and the USB2.0 logic circuit is connected with the CLPD main control circuit through a 16-bit-width Slavefifo bus. According to the invention, a parallel 16-path high-voltage square wave power emission structure instead of a structure of a single high-voltage square wave emission matching switching device is adopted, so that zero-error equal-interval multi-channel switching cyclic emission output of at least 1ms can be realized, which cannot be realized by the structure of the single high-voltage square wave emission matching switching device; and zero-error transmitting-receiving time extraction of data analysis in the later period of an experiment is ensured.

Description

Technical Field

[0001] The invention relates to the field of indoor earthquake simulation, and in particular to a multi-channel fast switching cycle excitation device for inducing seismic waves in rock friction experiments. Background Art

[0002] The indoor simulation of earthquakes currently mainly uses rock friction experiments. The change in rock wave velocity during the experiment is an important means to determine when the simulated earthquake occurs. At present, acoustic emission signals do not always appear in each stage of the rock friction deformation process. In some stages, the acoustic emission signals are strong, while in other stages, the acoustic emission signals are very weak or non-existent. This requires an artificial external trigger signal to pass through the rock fault, thereby generating ultrasonic waves inside the rock and propagating to the other side of the fault. The elastic wave collector can pick up the elastic waves on the other side of the fault and judge and analyze the trend of the elastic wave velocity change.

[0003] Since the rock samples used in rock friction experiments are mostly 30X30cm in size, the friction oblique fault is usually 45° and about 42cm long, and the contact sliding position of the friction oblique fault is not the same at different deformation stages, the experiment usually requires the deployment of excitation sensors and receiving sensors at different positions on both sides of the oblique fault. For this purpose, a multi-channel external excitation device is required.

[0004] Rocks are anisotropic, inhomogeneous materials, and the type and size of rocks have different attenuation levels for ultrasonic waves. Generally, the more pores a rock has and the larger its size, the greater its attenuation of ultrasonic waves. This requires the external excitation device to have sufficiently strong excitation energy.

[0005] The pre-slip stage of the rock friction deformation experiment simulating the indoor earthquake process is usually 10 to tens of seconds, and the rock friction deformation experiment is usually in a high-level electromagnetic radiation loading environment, which requires sliding average receiving data at the acquisition receiving end, and the short pre-slip stage also means that the subsequent data analysis process at this stage requires high-precision ultrasonic information first arrival time extraction (milliseconds), so the external excitation device needs to have extremely accurate equal-interval excitation function and repeated excitation ability, so as to facilitate time extraction and data sliding average in subsequent data analysis. The existing high-voltage transmitting device is usually a single channel or a single channel with a high-voltage switching device to achieve switching output between multiple channels. A single channel cannot achieve switching output between multiple channels, and a single channel with a high-voltage switching device is difficult to achieve extremely accurate equal-interval switching excitation output due to the characteristics of the high-voltage switching device. This is because the current high-voltage switching device is also composed of high-voltage relays, and the execution action of the high-voltage relay usually takes about a few ms, and there will be jitter after the execution action. The jitter time is inconsistent after each execution (a few ms to tens of ms), and it is impossible to achieve accurate equal-interval triggering, nor can it achieve fast channel switching output (1ms interval). According to the experimental requirements, this requires the device to have the ability to accurately and quickly switch multi-channel outputs at equal intervals of at least 1ms.

[0006] In view of the above problems, the present invention provides a multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments, which can artificially induce simulated seismic waves. Summary of the invention

[0007] The invention provides a multi-channel fast switching cycle excitation device which can artificially induce simulated seismic waves and is used for inducing seismic waves in rock friction experiments.

[0008] The purpose of the present invention is to provide a multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments, comprising a low-voltage logic control circuit and a high-voltage square wave power transmitting circuit, the low-voltage logic control circuit comprising a CPLD main controller circuit, a USB2.0 logic circuit and an isolation control circuit, the USB2.0 logic circuit and the isolation control circuit are both connected to a CLPD main control circuit, the low-voltage logic control circuit is connected to the high-voltage square wave power transmitting circuit, and the USB2.0 logic circuit and the CLPD main control circuit are connected using a 16-bit wide Slavefifo bus.

[0009] Furthermore, the low-voltage logic control circuit includes a CPLD chip, a power-on reset circuit and an RC filter circuit. The power-on reset circuit includes a resistor R4 and a diode D1 connected in parallel and connected to a 3.3V power supply, and then connected in parallel to a capacitor C1 to a DGND digital ground and connected to pin 143 of a CLPD chip. The RC filter circuit includes pin 2 of a crystal oscillator CY1 connected to DGND, pin 4 connected to a 3.3V power supply through a magnetic bead R5, capacitors C2, C3 and C4 connected in parallel and in series with a magnetic bead R5, pin 30 of a CLPD chip connected to pin 3 of a crystal oscillator CY1, pins 1, 8, 37, 42, 55, 73, 84, 109, 127 and 141 of the CLPD chip connected to a 3.3V power supply, and pins 18, 27, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123 and 144 of the CLPD chip connected to a DGND digital ground.

[0010] Furthermore, the USB2.0 logic circuit includes a USB microcontroller CYU1, USB2.0, a clock oscillation circuit, an RC filter circuit and a power-on reset circuit. Pin 5 of USB2.0 is connected to a resistor R9 and a capacitor C36. The clock oscillation circuit includes capacitors C26, C27 and a passive crystal oscillator Y1 to provide a working clock for the USB microcontroller CYU1. Pin 2 of the USB microcontroller CYU1 is connected in series with a resistor R13 to DGND. Pin 22 of the USB microcontroller CYU1 is connected in series with a resistor R14 to a 3.3V power supply and connected to pin 5 of the LC1 storage chip. Pin 51 of the USB microcontroller CYU1 is connected in series with a resistor R14 to a 3.3V power supply. Pin 49 of the USB microcontroller CYU1 is connected to a diode D2, a resistor R8 and a capacitor C25 to form a power-on reset circuit. Pin 1 of the LC1 chip is connected in series with a resistor R16. And connected to the 8-pin VCC, the RC filter circuit includes a magnetic bead RC, a capacitor C45, a capacitor C46 and a capacitor C37 to filter out the high-frequency noise of the 3.3V power supply and is connected to the 8-pin of the LC1 chip, the 6, 14, 18, 24, 34, 39, 50 pins of the USB microcontroller CYU1 are connected to the 3.3V power supply, the 4, 7, 13, 17, 19, 33, 35, 48 pins of the USB microcontroller CYU1 are connected to the DGND digital ground, the 25, 26, 27, 28, 29, 30, 31, 32, 52, 53, 54, 55, 56, 1, 2, 3 pins of the USB microcontroller CYU1 are connected to the USBFD1~USBFD16 of the slavefifo bus in sequence, the 44 and 45 pins of the USB microcontroller CYU1 are connected to the FIFOADDR0~ FIFOADDR1, pins 37 and 38 of the USB microcontroller CYU1 are connected to FLAGB and FLAGC of the slavefifo bus in sequence, pins 42, 8, and 9 of the USB microcontroller CYU1 are connected to SLOE, SLRD, and SLWR of the slavefifo bus in sequence, and pin 20 of the data USB microcontroller CYU1 is connected to IFCLK of the slavefifo bus.

[0011] Furthermore, the isolation control circuit includes a digital isolation chip AD16 and an RC filtering circuit. Pins 2 and 3 of the digital isolation chip AD16 are connected to pins 70 and 71 of the CLPD chip respectively. Pins 2 and 3 of the digital isolation chip AD16 of the other 15 isolation control circuits are sequentially connected to pins 74 and 75 of the CPLD for the second channel, pins 76 and 77 for the third channel, pins 78 and 79 for the fourth channel, pins 80 and 81 for the fifth channel, pins 82 and 83 for the sixth channel, pins 85 and 86 for the seventh channel, pins 87 and 88 for the eighth channel, pins 91 and 92 for the ninth channel, pins 93 and 94 for the tenth channel, and pins 95 and 96 for the eleventh channel. Pins 97 and 98 are the 12th channel, pins 100 and 101 are the 13th channel, pins 102 and 103 are the 14th channel, pins 105 and 106 are the 15th channel, and pins 107 and 110 are the 16th channel. Pins 6 and 7 of the digital isolation chip AD16 are connected to the on-off control pin of the high-voltage square wave power transmitting circuit. The RC filtering circuit is composed of a magnetic bead R183, a capacitor C510, a capacitor C511 and a capacitor C512 to filter out the high-frequency noise of the 3.3V digital power supply and is connected to pin 1 of the digital isolation chip AD16. Pin 5 of the digital isolation chip AD16 is connected to the low-voltage isolation ground GND of the high-voltage square wave power transmitting circuit.

[0012] Furthermore, the high-voltage square wave power transmitting circuit includes a half-bridge control chip NSD1, an RC filtering circuit, a first diode limiting circuit, a second diode limiting circuit, an LC filtering circuit, a first RC circuit and a second RC circuit. Pin 7 of the half-bridge control chip NSD1 is connected to a magnetic bead R6, a capacitor C3, a capacitor C4 and a capacitor C5 to form an RC filtering circuit and is connected to a 12V working power supply, and filters out high-frequency digital noise of the 12V working power supply. The ground of the RC filtering circuit is connected to the high-voltage transmitting ground TGND, pin 3 of the half-bridge control chip NSD1 is a digital control ground connected to a low-voltage isolation ground GND, and pin 5 of the half-bridge control chip NSD1 is a high-voltage ground connected to a high-voltage transmitting ground. The raw ground TGND, the 1st pin of the half-bridge control chip NSD1 is the start-up control pin of the high-side MOSFET tube of the half-bridge chip, and is connected in series with the resistor R4 and the positive electrode of the diode D6 to the 5V isolated power supply, the resistor R4 is connected in series with the negative electrode of the diode D5 to the low-voltage isolated ground GND, the first diode limiting circuit includes D5 and D6 in parallel, the 2nd pin of the half-bridge control core NSD1 is the start-up control pin of the low-side MOSFET tube of the half-bridge chip, and is connected in series with the resistor R9 and the positive electrode of the diode D4 to the 5V isolated power supply, R9 is connected in series with the negative electrode of the diode D3 to the low-voltage isolated ground GND, the second diode limiting circuit includes diodes D3 and D4, Pin 1 and pin 2 of the half-bridge control chip NSD1 are also pulled down and connected to resistors R3 and R7 to the low-voltage isolation ground respectively. Pin 7 of the half-bridge control chip NSD1 is connected to the positive electrode of the high-voltage diode D1, and the negative electrode of the D1 high-voltage diode is connected to pin 13 of the half-bridge control chip NSD1. Pin 13 of the half-bridge control core NSD1 is connected to capacitor C6, and the other pin of capacitor C6 is connected to pin 11 of the half-bridge control core NSD1. Pin 11 of the half-bridge control core NSD1 is simultaneously connected to the drain pin 2 of the Q2MOS tube and the source pin 3 of the Q1MOS tube and connected to pin 1 of the high-voltage output port P1 as a high-voltage pulse output. Pin 12 of the half-bridge control core NSD1 is a high-side MOS tube. The high-side MOS tube is turned on and the output pin is connected in series with the resistor R1, and then connected to the gate pin 1 of the Q1MOS tube. The pin 1 of the Q1MOS tube is connected to the resistor R5 and connected to the 11th pin of the half-bridge control chip NSD1 as a discharge resistor of the gate-source capacitor between the 1st pin and the 3rd pin of the Q1MOS. The 6th pin of the low-side MOS tube of the half-bridge control chip NSD1 is turned on and the output pin is connected to the gate pin 1 of the Q2 tube after being connected in series with the resistor R5. The resistor R5 is reversely connected in parallel with the diode D7. The pin 1 of the Q2MOS tube is connected with the resistor R8 and connected to the high-voltage emission ground TGND as a discharge resistor of the gate-source capacitor between the 1st pin and the 3rd pin of the Q2MOS tube. The LC filtering circuit includes a 1000V 1A high-voltage power supply composed of a solid-state inductor L1, a capacitor C16 and a high-voltage capacitor C2 and connected to the 2nd pin of the Q1MOS tube. The first RC circuit includes a capacitor C18 and a resistor R15 connected in series. The capacitor C18 and the resistor R15 are connected in series with the 2nd pin of the Q2MOS tube.Pin 3 of Q2MOS is connected to the high-voltage transmitter ground TGND. The second RC circuit includes a high-voltage capacitor C17 and a resistor R13 connected in series and connected between pins 2 and 3 of Q1MOS. The low-voltage isolation ground GND and the high-voltage transmitter ground TGND are connected with a magnetic bead R12.

[0013] The present invention has the following advantages: the present invention adopts a parallel 16-channel high-voltage square wave power transmission structure rather than a single high-voltage square wave transmission with a switching device structure, which can achieve zero-error equal-interval multi-channel switching cyclic transmission output of at least 1ms, which is impossible to achieve with a single high-voltage square wave transmission with a switching device structure, ensuring zero-error transmission-reception time extraction for data analysis in the later stage of the experiment.

[0014] The present invention can be applied to active source triggered simulated seismic waves in indoor simulated earthquake processes using rock friction experiments, providing a convenient and controllable technical means for conducting research on fault wave velocity changes on a millisecond time scale during deformation of different types of rock faults. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a work flow chart of the present invention; Figure 2 is a circuit diagram of the CLPD main controller of the present invention; Figure 3 The USB2.0 logic circuit diagram of the present invention; Figure 4 This is one of the isolation control circuit diagrams of the present invention; Figure 5 It is a high-voltage square wave power transmitting circuit diagram of the present invention; Figure 6 It is a schematic diagram of the bus interface between the CLPD of the present invention and the USB2.0 chip. DETAILED DESCRIPTION

[0016] The invention provides a multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments, comprising a low-voltage logic control circuit and a high-voltage square wave power transmitting circuit, wherein the low-voltage logic control circuit comprises a CPLD main controller circuit, a USB2.0 logic circuit and an isolation control circuit, wherein both the USB2.0 logic circuit and the isolation control circuit are connected to a CLPD main control circuit, the low-voltage logic control circuit is connected to the high-voltage square wave power transmitting circuit, and the USB2.0 logic circuit and the CLPD main control circuit are connected using a 16-bit wide Slavefifo bus.

[0017] In this embodiment, the low-voltage logic control circuit includes a CPLD chip, a power-on reset circuit and an RC filter circuit. The power-on reset circuit includes a resistor R4 and a diode D1 connected in parallel and connected to a 3.3V power supply, and then connected in parallel to a capacitor C1 to a DGND digital ground and connected to pin 143 of a CLPD chip. The RC filter circuit includes pin 2 of a crystal oscillator CY1 connected to DGND, and pin 4 connected to a 3.3V power supply through a magnetic bead R5. Capacitors C2, C3 and C4 are connected in parallel and in series with the magnetic bead R5. Pin 30 of the CLPD chip is connected to pin 3 of the crystal oscillator CY1. Pins 1, 8, 37, 42, 55, 73, 84, 109, 127 and 141 of the CLPD chip are connected to a 3.3V power supply, and pins 18, 27, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123 and 144 of the CLPD chip are connected to the DGND digital ground.

[0018] In this embodiment, the USB2.0 logic circuit includes a USB microcontroller CYU1, USB2.0, a clock oscillation circuit, an RC filter circuit and a power-on reset circuit. The 5th pin of USB2.0 is connected with a resistor R9 and a capacitor C36. The clock oscillation circuit includes capacitors C26, C27 and a passive crystal oscillator Y1 to provide a working clock for the USB microcontroller CYU1. The 2nd pin of the USB microcontroller CYU1 is connected in series with a resistor R13 to DGND. The 22nd pin of the USB microcontroller CYU1 is connected in series with a resistor R14 to a 3.3V power supply and connected to the 5th pin of the LC1 storage chip. The 51st pin of the USB microcontroller CYU1 is connected in series with a resistor R14 to a 3.3V power supply. The 49th pin of the USB microcontroller CYU1 is connected with a diode D2, a resistor R8 and a capacitor C25 to form a power-on reset circuit. The 1st pin of the LC1 chip is connected in series with a resistor R16. And connected to the 8-pin VCC, the RC filter circuit includes a magnetic bead RC, a capacitor C45, a capacitor C46 and a capacitor C37 to filter out the high-frequency noise of the 3.3V power supply and is connected to the 8-pin of the LC1 chip, the 6, 14, 18, 24, 34, 39, 50 pins of the USB microcontroller CYU1 are connected to the 3.3V power supply, the 4, 7, 13, 17, 19, 33, 35, 48 pins of the USB microcontroller CYU1 are connected to the DGND digital ground, the 25, 26, 27, 28, 29, 30, 31, 32, 52, 53, 54, 55, 56, 1, 2, 3 pins of the USB microcontroller CYU1 are connected to the USBFD1~USBFD16 of the slavefifo bus in sequence, the 44 and 45 pins of the USB microcontroller CYU1 are connected to the FIFOADDR0~ FIFOADDR1, pins 37 and 38 of the USB microcontroller CYU1 are connected to FLAGB and FLAGC of the slavefifo bus in sequence, pins 42, 8, and 9 of the USB microcontroller CYU1 are connected to SLOE, SLRD, and SLWR of the slavefifo bus in sequence, and pin 20 of the data USB microcontroller CYU1 is connected to IFCLK of the slavefifo bus.

[0019] In this embodiment, the isolation control circuit includes a digital isolation chip AD16 and an RC filtering circuit. Pins 2 and 3 of the digital isolation chip AD16 are connected to pins 70 and 71 of the CLPD chip respectively. Pins 2 and 3 of the digital isolation chip AD16 of the other 15 isolation control circuits are sequentially connected to pins 74 and 75 of the CPLD as the second path, pins 76 and 77 as the third path, pins 78 and 79 as the fourth path, pins 80 and 81 as the fifth path, pins 82 and 83 as the sixth path, pins 85 and 86 as the seventh path, pins 87 and 88 as the eighth path, pins 91 and 92 as the ninth path, pins 93 and 94 as the tenth path, and pins 95 and 96 as the first path. Pins 1, 97, and 98 are the 12th channel, pins 100 and 101 are the 13th channel, pins 102 and 103 are the 14th channel, pins 105 and 106 are the 15th channel, and pins 107 and 110 are the 16th channel. Pins 6 and 7 of the digital isolation chip AD16 are connected to the on-off control pin of the high-voltage square wave power transmitting circuit. The RC filtering circuit is composed of magnetic bead R183, capacitor C510, capacitor C511 and capacitor C512 to filter out the high-frequency noise of the 3.3V digital power supply and is connected to pin 1 of the digital isolation chip AD16. Pin 5 of the digital isolation chip AD16 is connected to the low-voltage isolation ground GND of the high-voltage square wave power transmitting circuit.

[0020] In this embodiment, the high-voltage square wave power transmitting circuit includes a half-bridge control chip NSD1, an RC filter circuit, a first diode limiter circuit, a second diode limiter circuit, an LC filter circuit, a first RC circuit and a second RC circuit. Pin 7 of the half-bridge control chip NSD1 is connected to a magnetic bead R6, a capacitor C3, a capacitor C4 and a capacitor C5 to form an RC filter circuit and is connected to a 12V working power supply, and filters out high-frequency digital noise of the 12V working power supply. The ground of the RC filter circuit is connected to the high-voltage transmitting ground TGND, the 3rd pin of the half-bridge control chip NSD1 is a digital control ground connected to the low-voltage isolation ground GND, and the 5th pin of the half-bridge control chip NSD1 is a high-voltage ground connected to the high-voltage The generating ground TGND, the 1st pin of the half-bridge control chip NSD1 is the start control pin of the high-side MOSFET tube of the half-bridge chip, and is connected in series with the resistor R4 and the positive pole of the diode D6 to the 5V isolated power supply, the resistor R4 is connected in series with the negative pole of the diode D5 to the low-voltage isolated ground GND, the first diode limiting circuit includes D5 and D6 in parallel, the 2nd pin of the half-bridge control core NSD1 is the start control pin of the low-side MOSFET tube of the half-bridge chip, and is connected in series with the resistor R9 and the positive pole of the diode D4 to the 5V isolated power supply, R9 is connected in series with the negative pole of the diode D3 to the low-voltage isolated ground GND, the second diode limiting circuit includes diodes D3 and D4 , Pin 1 and Pin 2 of the half-bridge control chip NSD1 are also pulled down and connected to the low-voltage isolation ground with resistors R3 and R7 respectively, Pin 7 of the half-bridge control chip NSD1 is connected to the positive electrode of the high-voltage diode D1, and the negative electrode of the D1 high-voltage diode is connected to Pin 13 of the half-bridge control chip NSD1, Pin 13 of the half-bridge control chip NSD1 is connected to capacitor C6, and the other pin of capacitor C6 is connected to Pin 11 of the half-bridge control chip NSD1, Pin 11 of the half-bridge control chip NSD1 is simultaneously connected to Pin 2 of the drain of the Q2MOS tube and Pin 3 of the source of the Q1MOS tube and connected to Pin 1 of the high-voltage output port P1 as a high-voltage pulse output, and Pin 12 of the half-bridge control chip NSD1 is a high-side MOS tube The high-side MOS tube is turned on by connecting the output pin with resistor R1 in series, and then connected to the gate pin 1 of the Q1MOS tube. The pin 1 of the Q1MOS tube is connected to resistor R5 and connected to pin 11 of the half-bridge control chip NSD1 as a discharge resistor of the gate-source capacitor between pins 1 and 3 of the Q1MOS. The 6-pin low-side MOS tube of the half-bridge control chip NSD1 is turned on by connecting the output pin with resistor R5 in series, and then connected to the gate pin 1 of the Q2 tube. The resistor R5 is reversely connected in parallel with the diode D7. The pin 1 of the Q2MOS tube is connected with resistor R8 and connected to the high-voltage emission ground TGND as a discharge resistor of the gate-source capacitor between pins 1 and 3 of the Q2MOS tube. The LC filtering circuit includes a 1000V 1A high-voltage power supply composed of a solid-state inductor L1, a capacitor C16 and a high-voltage capacitor C2 and connected to pin 2 of the Q1MOS tube. The first RC circuit includes a capacitor C18 and a resistor R15 connected in series. The capacitor C18 and the resistor R15 are connected in series to pin 2 of the Q2MOS tube.Pin 3 of Q2MOS is connected to the high-voltage transmitter ground TGND. The second RC circuit includes a high-voltage capacitor C17 and a resistor R13 connected in series and connected between pins 2 and 3 of Q1MOS. The low-voltage isolation ground GND and the high-voltage transmitter ground TGND are connected with a magnetic bead R12.

[0021] In this embodiment, Figure 1 As shown, the workflow is that the user sends instructions to the USB2.0 logic circuit of the device through the host computer software, and then the USB2.0 logic circuit transmits the instructions to the CPLD chip through the bus. The CPLD chip parses the corresponding switching channel and the transmission pulse time width and then executes the corresponding action and controls one of the 16 high-voltage square wave power transmission circuits to be turned on / off at the current time point to form a high-voltage transmission pulse. After that, the CPLD chip continues to execute the command to control the current transmission circuit to work or switches to the next transmission circuit according to the command and strictly follows the time interval loop given by the host computer (millisecond-level timing interval) until the host computer software gives a new stop command, and the entire device stops working and waits for a new host computer to start executing the command. In this embodiment, Figure 5 As shown, the working process of the high-voltage square wave power transmitting circuit is that after power-on, the CPLD controls the IO port of latch2 to output a high level by default. At this time, the 6th pin of the AD16 isolation chip also outputs a high level by default. Then, the 2nd pin of NSD1 is high and turns on the low-side MOS tube Q2. After Q2 is turned on to the low-voltage isolation ground, the 12V power supply charges C6 through the D1 diode. After a few microseconds, C6 is fully charged. At this time, if the USB interface receives the transmission command, the CPLD starts parsing and executes the action to output a 3.3V low-voltage pulse (the pulse time width command is adjustable) through the corresponding control of the IO port of latch1. The 7th pin of the corresponding AD16 isolation chip outputs a 5V isolated low-voltage pulse of the corresponding time width to the 1st pin of the NSD1 chip. Then, the NSD1 chip turns on the high-side MOS tube Q1. After Q1 is turned on, it is closed after the corresponding pulse time width and responds to the 1st pin of the P1 port with a 1000V high-voltage pulse of the corresponding time width.

[0022] In this implementation, if Figure 6As shown in the figure, the CPLD and the USB2.0 chip are connected by a 16-bit wide slave'fifo bus. The specific signals are 16-bit data USBFD1~USBFD16 (connected to pins 2~7, 9~17 and 19 of the CPLD in sequence), 2 address control lines FIFOADDR0~FIFOADDR1 (connected to pins 20~21 of the CPLD in sequence), storage flag lines FLAGB (storage full) (connected to pin 22 of the CPLD) and FLAGC (storage empty) (connected to pin 23 of the CPLD), as well as read and write enable lines SLOE, SLRD, SLWR (connected to pins 24~26 of the CPLD in sequence) and bus drive clock IFCLK (connected to pin 32 of the CPLD). The USB2.0 logic circuit receives commands from the host computer software through the USB2.0 interface and transmits them to the CPLD chip through the slavefifo bus to perform specific operations.

[0023] In this embodiment, a circuit structure of low-voltage control and high-voltage transmission isolation is adopted, and the low-voltage control uses CPLD (complex programmable logic device) to achieve extremely precise timing and equal-interval transmission control through an external active clock crystal oscillator, and in conjunction with the USB2.0 interface and control software, zero-error transmission-reception time extraction for subsequent data analysis can be achieved, providing a solid technical foundation for the observation of millisecond-level wave velocity changes in faults before earthquakes in rock deformation experiments.

[0024] In this embodiment, the high-voltage transmitting part adopts a parallel 16-way structure rather than a single transmitting and switching device structure, which allows the CPLD to arbitrarily and accurately control the opening / closing of any one of the 16 ways in time. The structure of a single transmitting and high-voltage switching device is prone to jitter of the switching actuator before and after the switching execution action of the switching device, which makes it difficult to achieve accurate time control. In addition, the currently known high-voltage switching devices composed of high-voltage relays or other high-voltage switching devices usually require at least several ms to execute actions, and the jitter time after each execution is uncertain (several ms to tens of ms), making it difficult to achieve fast (1ms) multi-channel switching high-voltage output.

[0025] Although the specific implementation of the present invention is described in detail in conjunction with the drawings, it should not be understood as limiting the scope of protection of this patent. Within the scope described in the claims, various modifications and variations that can be made by those skilled in the art without creative work still fall within the scope of protection of this patent.

Claims

1. A multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments, comprising a low-voltage logic control circuit and a high-voltage square wave power transmission circuit, characterized in that: The low-voltage logic control circuit includes a CPLD main controller circuit, a USB2.0 logic circuit and an isolation control circuit. The USB2.0 logic circuit and the isolation control circuit are both connected to the CLPD main control circuit. The low-voltage logic control circuit is connected to the high-voltage square wave power transmitting circuit. The USB2.0 logic circuit and the CLPD main control circuit are connected using a 16-bit wide Slavefifo bus.

2. A multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments as claimed in claim 1, characterized in that: The low-voltage logic control circuit includes a CPLD chip, a power-on reset circuit and an RC filter circuit. The power-on reset circuit includes a resistor R4 and a diode D1 connected in parallel and connected to a 3.3V power supply, and then connected in parallel to a capacitor C1 to a DGND digital ground and connected to pin 143 of a CLPD chip. The RC filter circuit includes a crystal oscillator CY1 with pin 2 connected to DGND, and pin 4 connected to a 3.3V power supply through a magnetic bead R5. Capacitors C2, C3 and C4 are connected in parallel and in series with the magnetic bead R5. Pin 30 of the CLPD chip is connected to pin 3 of the crystal oscillator CY1. Pins 1, 8, 37, 42, 55, 73, 84, 109, 127 and 141 of the CLPD chip are connected to a 3.3V power supply, and pins 18, 27, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123 and 144 of the CLPD chip are connected to a DGND digital ground.

3. A multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments as claimed in claim 1, characterized in that: The USB2.0 logic circuit includes a USB microcontroller CYU1, USB2.0, a clock oscillation circuit, an RC filter circuit and a power-on reset circuit. The 5th pin of the USB2.0 is connected with a resistor R9 and a capacitor C36. The clock oscillation circuit includes capacitors C26, C27 and a passive crystal oscillator Y1 to provide a working clock for the USB microcontroller CYU1. The 2nd pin of the USB microcontroller CYU1 is connected in series with a resistor R13 to DGND. The 22nd pin of the USB microcontroller CYU1 is connected in series with a resistor R14 to a 3.3V power supply and connected to the 5th pin of the LC1 storage chip. The 51st pin of the USB microcontroller CYU1 is connected in series with a resistor R14 to a 3.3V power supply. The 49th pin of the USB microcontroller CYU1 is connected with a diode D2, a resistor R8 and a capacitor C25 to form a power-on reset circuit. The 1st pin of the LC1 chip is connected in series with a resistor R16. And connected to the 8-pin VCC, the RC filter circuit includes a magnetic bead RC, a capacitor C45, a capacitor C46 and a capacitor C37 to filter out the high-frequency noise of the 3.3V power supply and is connected to the 8-pin of the LC1 chip, the 6, 14, 18, 24, 34, 39, 50 pins of the USB microcontroller CYU1 are connected to the 3.3V power supply, the 4, 7, 13, 17, 19, 33, 35, 48 pins of the USB microcontroller CYU1 are connected to the DGND digital ground, the 25, 26, 27, 28, 29, 30, 31, 32, 52, 53, 54, 55, 56, 1, 2, 3 pins of the USB microcontroller CYU1 are connected to the USBFD1~USBFD16 of the slavefifo bus in sequence, and the 44 and 45 pins of the USB microcontroller CYU1 are connected to the FIFOADDR0~ FIFOADDR1, the 37th and 38th pins of the USB microcontroller CYU1 are connected to the FLAGB and FLAGC of the slavefifo bus in sequence, the 42nd, 8th and 9th pins of the USB microcontroller CYU1 are connected to the SLOE, SLRD and SLWR of the slavefifo bus in sequence, and the 20th pin of the USB microcontroller CYU1 is connected to the IFCLK of the slavefifo bus.

4. A multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments as claimed in claim 1, characterized in that: The isolation control circuit includes 16-way isolation control circuits, and the isolation control circuit also includes a digital isolation chip AD16 and an RC filtering circuit. Pins 2 and 3 of the digital isolation chip AD16 are respectively connected to pins 70 and 71 of the CLPD chip, and pins 2 and 3 of the digital isolation chip AD16 of the other 15-way isolation control circuits are sequentially connected to pins 74 and 75 of the CPLD as the second route, pins 76 and 77 as the third route, pins 78 and 79 as the fourth route, pins 80 and 81 as the fifth route, pins 82 and 83 as the sixth route, pins 85 and 86 as the seventh route, pins 87 and 88 as the eighth route, pins 91 and 92 as the ninth route, pins 93 and 94 as the tenth route, and pins 95, 96 and 97 as the eighth route. Pin 96 is the 11th route, pins 97 and 98 are the 12th route, pins 100 and 101 are the 13th route, pins 102 and 103 are the 14th route, pins 105 and 106 are the 15th route, and pins 107 and 110 are the 16th route. Pins 6 and 7 of the digital isolation chip AD16 are connected to the on-off control pin of the high-voltage square wave power transmitting circuit. The RC filter circuit is composed of a magnetic bead R183, a capacitor C510, a capacitor C511 and a capacitor C512 to filter out the high-frequency noise of the 3.3V digital power supply and is connected to pin 1 of the digital isolation chip AD16. Pin 5 of the digital isolation chip AD16 is connected to the low-voltage isolation ground GND of the high-voltage square wave power transmitting circuit.

5. A multi-channel fast switching cyclic excitation device for inducing seismic waves in rock friction experiments as claimed in claim 1, characterized in that: The high-voltage square wave power transmitting circuit includes a half-bridge control chip NSD1, an RC filter circuit, a first diode limiter circuit, a second diode limiter circuit, an LC filter circuit, a first RC circuit and a second RC circuit. Pin 7 of the half-bridge control chip NSD1 is connected to a magnetic bead R6, a capacitor C3, a capacitor C4 and a capacitor C5 to form an RC filter circuit and is connected to a 12V working power supply, and filters out high-frequency digital noise of the 12V working power supply. The ground of the RC filter circuit is connected to a high-voltage transmitting ground TGND. Pin 3 of the half-bridge control chip NSD1 is a digital control ground connected to a low-voltage isolation ground GND. Pin 5 of the half-bridge control chip NSD1 is a high-voltage ground connected to a high-voltage generating ground TGND. ND, the 1st pin of the half-bridge control chip NSD1 is the start control pin of the high-side MOSFET tube of the half-bridge chip, and is connected in series with a resistor R4 and a positive electrode of a diode D6 connected in series to a 5V isolated power supply, the resistor R4 is connected in series with the negative electrode of a diode D5 connected to the low-voltage isolated ground GND, the first diode limiter circuit includes D5 and D6 in parallel, the 2nd pin of the half-bridge control core NSD1 is the start control pin of the low-side MOSFET tube of the half-bridge chip, and is connected in series with a resistor R9 and a positive electrode of a diode D4 connected to a 5V isolated power supply, the R9 is connected in series with the negative electrode of a diode D3 connected to the low-voltage isolated ground GND, the second diode limiter circuit includes a diode D3 and a diode D4, the Pin 1 and pin 2 of the half-bridge control chip NSD1 are also pulled down and connected to resistors R3 and R7 to the low voltage isolation ground respectively. Pin 7 of the half-bridge control chip NSD1 is connected to the positive electrode of the high-voltage diode D1, and the negative electrode of the D1 high-voltage diode is connected to pin 13 of the half-bridge control chip NSD1. Pin 13 of the half-bridge control chip NSD1 is connected to capacitor C6, and the other pin of the capacitor C6 is connected to pin 11 of the half-bridge control chip NSD1. Pin 11 of the half-bridge control chip NSD1 is simultaneously connected to the drain pin 2 of the Q2MOS tube and the source pin 3 of the Q1MOS tube and connected to pin 1 of the high-voltage output port P1 as a high-voltage pulse output. Pin 12 of the half-bridge control chip NSD1 is a high-side MOS. The high-side MOS tube is connected to the gate pin 1 of the Q1MOS tube after the output pin is turned on and connected to the resistor R1 in series. The pin 1 of the Q1MOS tube is connected to the resistor R5 and connected to the 11th pin of the half-bridge control chip NSD1 as the discharge resistor of the gate-source capacitor between the 1st pin and the 3rd pin of the Q1MOS. The 6th pin of the low-side MOS tube of the half-bridge control chip NSD1 is connected to the gate pin 1 of the Q2 tube after the output pin is turned on and connected to the resistor R5 in series. The resistor R5 is connected in reverse parallel to the diode D7. The pin 1 of the Q2MOS tube is connected to the resistor R8 and connected to the high-voltage emission ground TGND as the discharge resistor of the gate-source capacitor between the 1st pin and the 3rd pin of the Q2MOS tube. The LC filter circuit includes a 1000V 1A high-voltage power supply composed of a solid-state inductor L1, a capacitor C16 and a high-voltage capacitor C2 and connected to the 2nd pin of the Q1MOS tube.The first RC circuit includes a capacitor C18 and a resistor R15 connected in series, the capacitor C18 and the resistor R15 are connected in series to the 2nd pin of the Q2MOS tube, the 3rd pin of the Q2MOS tube is connected to the high-voltage emission ground TGND, the second RC circuit includes a high-voltage capacitor C17 and a resistor R13 connected in series and connected between the 2nd and 3rd pins of the Q1MOS tube, the low-voltage isolation ground GND and the high-voltage emission ground TGND are connected with a magnetic bead R12.

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