A base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit

Abstract

The present invention discloses a base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit, comprising: a startup module, a bandgap reference core module, a base current compensation module, a high-order logarithmic compensation module and a high-temperature zone segmented compensation module; wherein the startup module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature zone segmented compensation module are all connected to the power supply V DD The invention relates to a bandgap reference voltage circuit, a base current compensation module, a high-order logarithmic compensation module, and a high-temperature zone segment compensation module. ...

Description

Technical Field

[0001] The invention belongs to the technical field of analog circuits, and in particular relates to a bandgap reference voltage circuit without an operational amplifier with base compensation and high-order compensation. Background Art

[0002] Bandgap reference circuits play a vital role in the field of electronics. They provide a stable reference voltage that does not change with ambient temperature for various analog and digital circuits. The design of this circuit is based on the energy band gap of semiconductor materials, which can maintain the stability of voltage under different environmental conditions, such as temperature changes. This stability makes bandgap reference circuits very suitable for applications that require high accuracy and reliability. For example, in data converters, they ensure that analog signals can be accurately converted to digital signals.

[0003] In addition, bandgap reference circuits are also widely used in the field of power management. They help maintain the consistency of power supply voltage, which is essential for maintaining the stable operation of electronic devices. In dynamic storage and flash memory technology, bandgap reference circuits also play an important role. The stable voltage they provide is essential for the correct storage and reading of data.

[0004] As technology develops, the performance requirements for bandgap reference circuits are also increasing. Modern electronic systems not only require them to work stably at room temperature, but also to maintain performance at extreme temperatures, which is especially important for portable devices and industrial control systems. Therefore, the design and optimization of bandgap reference circuits is an active research area in the field of electronic engineering, and new technologies and methods are constantly being developed to meet these growing needs.

[0005] The traditional bandgap reference circuit uses bipolar transistor op amp clamping technology to obtain a current IPTAT (full name: Currents Proportional to Absolute Temperature) that is positively correlated with temperature and a current ICTAT (full name: Currents Complementary to Absolute Temperature) that is negatively correlated with temperature, so that the temperature coefficients of the two cancel each other out and obtain a voltage that is independent of temperature.

[0006] Figure 1 Figure 2 is the circuit schematic diagram of a traditional bandgap reference voltage circuit. Figure 1 , the ratio of the emitter area of ​​transistor Q11 to that of transistor Q12 is , then the expression of IPTAT positive temperature coefficient current is:

[0007] ;

[0008] in, is the thermal voltage, , is the ambient temperature (measured in Kelvin), is the Boltzmann constant, is the unit charge constant, and Both are current amplification factors.

[0009] Affected by the process and temperature, the current amplification factors of different transistors are limited, different from each other and change with temperature. The IPTAT current contains high-order terms, and the traditional reference voltage circuit cannot eliminate the impact of the current amplification factor.

[0010] The base-emitter voltage (VBE) of the transistor will become nonlinearly related to temperature due to uneven process manufacturing and process control. Assuming the temperature is , the temperature coefficient of the reference voltage is 0, then the expression of VBE is as follows:

[0011] ;

[0012] in, is the VBE value when the ambient temperature is 0, is the temperature coefficient, is the exponential coefficient of the PN junction current deviation from the PTAT characteristic, The ambient temperature is VBE value at .

[0013] so, Figure 1 The reference voltage The expression is:

[0014] .

[0015] However, the bipolar transistor op amp clamping technology only compensates the temperature characteristic curve in the first order. Since the current amplification factor of the bipolar transistor (full name: Bipolar Junction Transistor, referred to as BJT) has temperature curvature, and the current amplification factor is generally less than 100 times, IPTAT contains high-order terms related to temperature. The base emitter voltage VBE of the BJT transistor has temperature curvature, resulting in ICTAT containing high-order terms related to temperature. Therefore, the temperature characteristic curve presents a parabolic shape dominated by quadratic terms. In addition, the traditional bandgap reference circuit containing op amps uses op amps for clamping, and the offset voltage introduced by the op amps will also affect the accuracy of the reference voltage, and also introduce new noise. In addition, the temperature coefficient of the traditional reference voltage generation circuit is generally around 50ppm, which is difficult to meet the requirements of high precision and extremely low ambient temperature influence in the field of micro-electro-mechanical systems (MEMS) and industrial control. Summary of the invention

[0016] In order to solve the above problems existing in the prior art, the present invention provides a bandgap reference voltage circuit without an operational amplifier with base compensation and high-order compensation.

[0017] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0018] The present invention provides a base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit, comprising: a startup module, a bandgap reference core module, a base current compensation module, a high-order logarithmic compensation module and a high-temperature zone segment compensation module;

[0019] The startup module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature segment compensation module are all connected to the power supply V DD The start-up module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature zone segment compensation module are connected in sequence, and the high-order logarithmic compensation module is also interconnected with the start-up module and the bandgap reference core module respectively.

[0020] In some embodiments, the base current compensation module includes: PMOS tubes M13, M14 and M19-M22, transistor Q3, and NMOS tubes M15-M18 and M23-M26;

[0021] The source of M13, the source of M19, the source of M21 and the collector of Q3 are all connected to the power supply V DDThe gate of M13 is connected to the gate of the PMOS tube M5 and the gate of the PMOS tube M7 in the bandgap reference core module, the drain of M13 is connected to the source of M14, the gate of M14 is connected to the gate of the PMOS tube M6 and the gate of the PMOS tube M8 in the bandgap reference core module, the drain of M14 is connected to the drain of M15, the drain of M15 is connected to the gate of M17 after the gate connection, the source of M15 is connected to the drain of M16, the drain of M16 is connected to the gate of M18 after the gate connection, the source of M16 and the source of M18 are both grounded; the drain of M18 is connected to the source of M17, the drain of M17 is connected to the drain of M23 and the emitter of Q3 The source of M23 is connected to the drain of M24, the source of M24 and the source of M26 are both grounded, the gate of M24 is connected to the gate of M26, the drain of M26 is connected to the source of M25 after the gate is connected, the drain of M25 is connected to the drain of M22 after the gate is connected, the gate of M22 is connected to the gate of M20 and the gate of the PMOS tube M28 in the high-order logarithmic compensation module, the gate of M20 is connected to the base of Q3 after the gate-drain connection, the source of M20 is connected to the drain of M19, the gate of M19 is connected to the gate of M21 and the gate of the PMOS tube M27 in the high-order logarithmic compensation module, and the drain of M21 is connected to the source of M22.

[0022] In some embodiments, the high-order logarithmic compensation module includes: PMOS tubes M27-M30, M32-M37, transistor Q4, resistors R4 and R5, and NMOS tubes M31 and M49;

[0023] The gate of M28 is connected to the base current compensation module, the gate of M27 is connected to the base current compensation module, and the source of M27, the source of M29, the source of M32, the source of M34 and the source of M36 are all connected to the power supply V DD, the drain of M27 is connected to the source of M28, the drain of M28 is connected to the collector of Q4, the base of Q4 is connected to the collector, the emitter of Q4 is grounded, the gate of M29 is connected to the gate of the PMOS tube M5 in the bandgap reference core module and the gate of the PMOS tube M38 in the high temperature segment compensation module, the drain of M29 is connected to the source of M30, the gate of M30 is connected to the gate of the PMOS tube M6 in the bandgap reference core module and the gate of the PMOS tube M39 in the high temperature segment compensation module, the drain of M30 is connected to the drain of M31, the drain and gate of M31 are connected to the gate of M49, the source of M31 is connected to the collector of Q4, the source of M49 is connected to one end of R4, and the The other end is grounded, the drain of M49 is connected to the drain of M33, the source of M33 is connected to the drain of M32, the gate of M32 is connected to the gate of M34, the drain of M34 is connected to the source of M35, the gate of M35 is connected to the gate of M33, the drain of M35 is connected to the drain of M37, one end of R5, the gate of the PMOS tube M2 and the gate of the NMOS tube M3 in the startup module, and the drain of the NMOS tube M40 in the high temperature zone segmented compensation module, the other end of R5 is grounded, the source of M37 is connected to the drain of M36, the gate of M37 is connected to the gate of the PMOS tube M39 in the high temperature zone segmented compensation module, and the gate of M36 is connected to the gate of the PMOS tube M38 in the high temperature zone segmented compensation module.

[0024] In some embodiments, the base current compensation module includes a transistor Q3, wherein Q3 and Q4 are NPN transistors of the same type, and the ratio of the emitter area of ​​Q3 to that of Q4 is 4:1.

[0025] In some embodiments, the width-to-length ratios of M31 and M49 are the same.

[0026] In some embodiments, the high temperature zone segment compensation module includes: PMOS tubes M38, M39 and M44-M47, resistor R6, and NMOS tubes M40-M43 and M48;

[0027] The gate of M38 is connected to the gate of the PMOS tube M5 in the bandgap reference core module and the high-order logarithmic compensation module, the gate of M39 is connected to the gate of the PMOS tube M6 in the bandgap reference core module and the high-order logarithmic compensation module, and the source of M38, the source of M44 and the source of M46 are all connected to the power supply V DDThe drain of M38 is connected to the source of M39, the drain of M39 is connected to the gate of M48 and one end of R6, the other end of R6 is grounded, the drain of M40 is connected to the high-order logarithmic compensation module as the third end of the high-temperature segmented compensation module, the source of M40 is connected to the drain of M41, the source of M41 is grounded, the source of M43 is grounded, the drain-gate of M43 is connected to the gate of M41, and the drain of M43 is connected to the gate of M41. The electrode of M42 is connected to the source of M42, the gate of M42 is connected to the gate of M40, the drain of M42 is connected to the drain of M45 after the gate is connected, the source of M45 is connected to the drain of M44, the gate of M44 is connected to the gate of M46, the drain of M46 is connected to the source of M47 after the gate is connected, the gate of M47 is connected to the gate of M45, the drain of M47 is connected to the drain of M48 after the gate is connected, and the source of M48 is grounded.

[0028] In some embodiments, the bandgap reference core module includes: PMOS tubes M5-M8, resistors R1-R3, NMOS tubes M9-M12, and transistors Q1 and Q2;

[0029] The source of M5 and the source of M7 are both connected to the power supply V DD The gate of M5 is connected to the gate of M7 and then connected to the high temperature zone segment compensation module, the base current compensation module and the high order logarithmic compensation module. The gate of M6 is connected to the gate of M8 and then connected to the high temperature zone segment compensation module, the base current compensation module and the high order logarithmic compensation module. The gate of M5 is connected to the drain of M6, the drain of M5 is connected to the source of M6, the drain of M6 is connected to the startup module, and the drain of M6 is also connected to one end of R1, the other end of R1 is connected to the drain of M9, the gate of M6 and the gate of M8, the source of M9 is connected to the drain of M10, and M The gate of M9 is connected to the gate of M11, the gate of M10 is connected to the gate of M12, the source of M10 is connected to one end of R3, the other end of R3 is connected to the collector of Q1, the base of Q1 is connected to the collector, the emitter of Q1 and the emitter of Q2 are both grounded, the base of Q2 is connected to the collector, the collector of Q2 is connected to the source of M12, the gate of M12 is also connected to the drain of M11, the drain of M12 is connected to the source of M11, the drain of M11 is connected to one end of R2, the other end of R2 is connected to the drain of M8, the gate of M9 and the gate of M11, and the source of M8 is connected to the drain of M7.

[0030] In some embodiments, the emitter area ratio of Q1 and Q2 is 8:1.

[0031] In some embodiments, the startup module includes: PMOS tubes M1 and M2, and NMOS tubes M3 and M4;

[0032] The source of M1 is connected to the power supply V DD The gate and drain of M1 are connected, and then connected to the source of M2. The drain of M2 is connected to the gate of M4 and the drain of M3. The gate of M3 is connected to the gate of M2 and then connected to the high-order logarithmic compensation module. The source of M3 is grounded. The drain of M4 is connected to the drain of the PMOS tube M6 in the bandgap reference core module, and the source of M4 is grounded.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1) The bandgap reference voltage circuit of the present invention includes a base current compensation module, so it can compensate for the limited amplification factor of the transistor. The nonlinearity introduced with temperature changes produces an ideal current that is proportional to absolute temperature (PTAT), improving the accuracy and stability of the circuit.

[0035] 2) Since the bandgap reference voltage circuit of the present invention includes a high-order logarithmic compensation module, it can utilize a subthreshold MOS tube (MOS is the abbreviation of MOSFET, MOSFET is the metal-oxide-semiconductor field-effect transistor, and the full name of MOSFET in English is Metal-Oxide-Semiconductor Field-Effect Transistor) to generate a high-order temperature positively correlated current, which partially offsets the high-order terms of VBE to generate a more ideal absolute temperature complementary (Complementary to Absolute Temperature, CTAT) current, thereby further improving the accuracy and stability of the circuit.

[0036] 3) Since the bandgap reference voltage circuit of the present invention includes a high temperature zone segment compensation module, high temperature compensation can be achieved through a subthreshold current when the temperature is in the high temperature range.

[0037] 4) The bandgap reference voltage circuit of the present invention removes the traditional BG (full spelling in English: Bandgap) operational amplifier and adopts an operational amplifier-free structure, thereby avoiding the introduction of operational amplifier noise and avoiding the influence of operational amplifier offset voltage on the bandgap reference voltage.

[0038] 5) The bandgap reference voltage circuit of the present invention can significantly reduce the reference output temperature drift, specifically, it can reduce the typical TT (English full spelling: Typical Typical) process angular temperature drift from 42ppm / °C to 3.5ppm / °C, which is reduced by one order of magnitude.

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a circuit schematic diagram of a traditional bandgap reference voltage circuit provided by an embodiment of the present invention;

[0041] Figure 2 It is a circuit schematic diagram of a part of a base compensation plus high-order compensation op-amp-free bandgap reference voltage circuit provided by an embodiment of the present invention;

[0042] Figure 3 It is another circuit schematic diagram of a base compensation plus high-order compensation op-amp-free bandgap reference voltage circuit provided by an embodiment of the present invention;

[0043] Figure 4 is a temperature drift curve diagram of a conventional bandgap reference voltage circuit under the worst case provided by an embodiment of the present invention;

[0044] Figure 5 This is a temperature drift curve diagram of the bandgap reference voltage circuit of the present invention under the worst case provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0046] The embodiment of the present invention provides a base compensation and high-order compensation non-op-amp bandgap reference voltage circuit, the circuit includes: a startup module, a bandgap reference core module, a base current compensation module, a high-order logarithmic compensation module and a high-temperature segmented compensation module. The startup module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature segmented compensation module are all connected to the power supply V DD The start-up module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature zone segment compensation module are connected in sequence, and the high-order logarithmic compensation module is also interconnected with the start-up module and the bandgap reference core module respectively.

[0047] In some embodiments, the startup module includes: PMOS transistors M1 and M2, and NMOS transistors M3 and M4. Specifically, the source of M1 is connected to the power supply V DD The drain of M1 is connected to the source of M2, the drain of M2 is connected to the gate of M4 and the drain of M3, the gate of M3 is connected to the gate of M2 and then connected to the high-order logarithmic compensation module as the first end of the startup module, the source of M3 is grounded, the drain of M4 is connected to the third end of the bandgap reference core module as the second end of the startup module, and the source of M4 is grounded. Exemplarily, Figure 2 A schematic diagram of a part of the circuit of the base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit provided by the present invention; Figure 3This is another circuit schematic diagram of the base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit provided by the present invention. Figure 2 , 3 As shown, specifically, the gate of M3 is connected to the gate of M2 as the VBG terminal, and the VBG terminal is connected to the drains of the PMOS tubes M35 and M37 in the high-order logarithmic compensation module, the drain of the NMOS tube M40 and one end of R5, and the drain of M4 is connected to the drain of the PMOS tube M6 in the bandgap reference core module and one end of the resistor R1. The startup module can generate a bias voltage when the circuit is initially powered on.

[0048] In some embodiments, the bandgap reference core module includes: PMOS transistors M5-M8, resistors R1-R3, NMOS transistors M9-M12, and transistors Q1 and Q2. Specifically, the source of M5 and the source of M7 are both connected to the power supply V DD The gate of M5 is connected to the gate of M7 and then serves as the first end of the bandgap reference core module connected to the high temperature zone segment compensation module, the base current compensation module and the high order logarithmic compensation module. The gate of M6 is connected to the gate of M8 and then serves as the second end of the bandgap reference core module connected to the high temperature zone segment compensation module, the base current compensation module and the high order logarithmic compensation module. The gate of M5 is connected to the drain of M6, the drain of M5 is connected to the source of M6, and the drain of M6 is connected to the startup module as the third end of the bandgap reference core module; and the drain of M6 is also connected to one end of R1, the other end of R1 is connected to the drain of M9, the gate of M6 and the gate of M8, and M9 The source of M10 is connected to the drain of M10, the gate of M9 is connected to the gate of M11, the gate of M10 is connected to the gate of M12, the source of M10 is connected to one end of R3, the other end of R3 is connected to the collector of Q1, the base of Q1 is connected to the collector, the emitter of Q1 and the emitter of Q2 are both grounded, the base of Q2 is connected to the collector, the collector of Q2 is connected to the source of M12, the gate of M12 is also connected to the drain of M11, the drain of M12 is connected to the source of M11, the drain of M11 is connected to one end of R2, the other end of R2 is connected to the drain of M8, the gate of M9 and the gate of M11, and the source of M8 is connected to the drain of M7. Continue to refer to the above Figure 2 and Figure 3, the gate of M5 is connected to the gate of M7 as the VB1 terminal, which is not only connected to the gate of the PMOS tube M13 in the base current compensation module, but also to the gate of the PMOS tube M29 in the high-order logarithmic compensation module and the gate of the PMOS tube M38 in the high-temperature segment compensation module; the gate of M6 is connected to the gate of M8 as the VB2 terminal, which is not only connected to the gate of the PMOS tube M14 in the base current compensation module, but also to the gate of the PMOS tube M30 in the high-order logarithmic compensation module and the gate of the PMOS tube M39 in the high-temperature segment compensation module. Q1 and Q2 are both NPN tubes, and the emitter area ratio of Q1 and Q2 is 8:1.

[0049] In some embodiments, please continue to refer to the above Figure 2 and Figure 3 The base current compensation module includes: PMOS tubes M13, M14 and M19~M22, transistor Q3, and NMOS tubes M15~M18 and M23~M26. Specifically, the source of M13, the source of M19, the source of M21 and the collector of Q3 are all connected to the power supply V DD , the gate of M13 is connected to the VB1 terminal, the drain of M13 is connected to the source of M14, the gate of M14 is connected to the VB2 terminal, the drain of M14 is connected to the drain of M15, the drain-gate of M15 is connected to the gate of M17, the source of M15 is connected to the drain of M16, the drain-gate of M16 is connected to the gate of M18, the source of M16 and the source of M18 are both grounded; the drain of M18 is connected to the source of M17, the drain of M17 is connected to the drain of M23 and the emitter of Q3, the source of M23 is connected to the drain of M24, the source of M24 and the source of M26 are both grounded, the gate of M24 is connected to the gate of M26, and the source of M26 is connected to the The drain-gate is connected to the source of M25, the drain-gate of M25 is connected to the drain of M22, the gate-drain of M20 is connected to the gate of M22, and the end after M20 and M22 are connected is used as the B end, the B end is connected to the gate of the PMOS tube M28 in the high-order logarithmic compensation module, the gate-drain of M20 is also connected to the base of Q3, the source of M20 is connected to the drain of M19, the gate-drain of M19 is connected to the gate of M21, and the end after M19 and M21 are connected is used as the A end, wherein the A end is connected to the gate of the PMOS tube M27 in the high-order logarithmic compensation module, and the drain of M21 is connected to the source of M22.

[0050] In some embodiments, please continue to refer to the above Figure 3, the high-order logarithmic compensation module includes: PMOS tubes M27~M30, M32~M37, transistor Q4, resistors R4 and R5, and NMOS tubes M31 and M49. Specifically, the gate of M28 serves as the first end of the high-order logarithmic compensation module, the gate of M27 serves as the second end of the high-order logarithmic compensation module, and the source of M27, the source of M29, the source of M32, the source of M34, and the source of M36 are all connected to the power supply V DD , the drain of M27 is connected to the source of M28, the drain of M28 is connected to the collector of Q4, the base of Q4 is connected to the collector, the emitter of Q4 is grounded, the gate of M29 is connected to the VB1 terminal, the drain of M29 is connected to the source of M30, the gate of M30 is connected to the VB2 terminal, the drain of M30 is connected to the drain of M31, the drain and gate of M31 are connected to the gate of M49, the source of M31 is connected to the collector of Q4, the source of M49 is connected to one end of R4, the other end of R4 is grounded, the drain of M49 is connected to the drain of M33, the source of M33 is connected to the drain of M32, the gate of M32 The gate of M34 is connected, the drain of M34 is connected to the source of M35, the gate of M35 is connected to the gate of M33, the drain of M35 is connected to the drain of M37, one end of R5, the gate of M2 and the gate of M3, and the drain of NMOS tube M40 in the high temperature zone segmented compensation module, wherein the drain of M35 is connected to the drain of M37 and then connected to the VBG end, the other end of R5 is grounded, the source of M37 is connected to the drain of M36, the gate of M37 is connected to the gate of PMOS tube M39 in the high temperature zone segmented compensation module, and the gate of M36 is connected to the gate of PMOS tube M38 in the high temperature zone segmented compensation module. Among them, M=4 for Q3 and M=1 for Q4, which respectively indicate that the emitter area of ​​Q3 tube is four times the emitter area of ​​the basic NPN tube, and the emitter area of ​​Q4 tube is one times the emitter area of ​​the basic NPN tube.

[0051] In some embodiments, please continue to refer to the above Figure 3 The high temperature zone segment compensation module includes: PMOS tubes M38, M39 and M44~M47, resistor R6, and NMOS tubes M40~M43 and M48. Specifically, the gate of M38 is connected to the VB1 terminal as the first terminal of the high temperature zone segment compensation module, the gate of M39 is connected to the VB2 terminal as the second terminal of the high temperature zone segment compensation module, and the source of M38, the source of M44 and the source of M46 are all connected to the power supply V DDThe drain of M38 is connected to the source of M39, the drain of M39 is connected to the gate of M48 and one end of R6, the other end of R6 is grounded, the drain of M40 is connected to the VBG end, the source of M40 is connected to the drain of M41, the source of M41 is grounded, the source of M43 is grounded, the drain-gate of M43 is connected and then connected to the gate of M41, the drain of M43 is connected to the source of M42, the gate of M42 is connected to the gate of M40, the drain-gate of M42 is connected and then connected to the drain of M45, the source of M45 is connected to the drain of M44, the gate of M44 is connected to the gate of M46, the drain-gate of M46 is connected and then connected to the source of M47, the gate of M47 is connected to the gate of M45, the drain-gate of M47 is connected and then connected to the drain of M48, and the source of M48 is grounded.

[0052] The following continues to combine the above Figure 2 and Figure 3 , some working principles of the circuit provided by the present invention are explained.

[0053] like Figure 2 and Figure 3 As shown, Q3 and Q4 are both NPN tubes of the same type, so the current amplification factor of Q3 and Q4 is the same. M19~M22 form a current mirror, which copies the base current of Q3 to Q4 in a 1:1 ratio, thus obtaining: ,in, represents the collector current of Q4, represents the base current of Q3, represents the current that is positively correlated with temperature, and, is the source current of M14, and, as Figure 2 and Figure 3 As shown, the source current of M14 is equal to the source current of M30 and M37 through the current mirror; represents the current amplification factor. So for Q4, the collector current Exactly equal to Obviously, it is not affected by the current magnification and compensates for the limited magnification of the transistor. The nonlinearity introduced by temperature changes can be That is, the present invention uses the same type of NPN transistors Q3 and Q4, and replicates the base current of Q3 through current mirrors M19-M22, so that the collector current of Q4 is exactly equal to , not affected by the current magnification The influence of the transistor is compensated for by the limited amplification factor. The nonlinearity introduced with temperature changes can produce an ideal PTAT current, improving the accuracy and stability of the circuit.

[0054] Continue to refer to the above Figure 3 , the width-to-length ratios of M31 and M49 are the same and large enough to operate in the subthreshold region. The source voltage of M31 and the source voltage of M49 The difference expression is: ,in, is the subthreshold constant, , is the Boltzmann constant, is the ambient temperature, is the unit charge constant, represents the current that is negatively correlated with temperature, and, is the source current of M35. The bandgap reference core module generates After base compensation, it becomes a more ideal current that is positively correlated with temperature. The drain current of M31 is It can be expressed as: , is the temperature-dependent voltage on resistor R3, The temperature at which the slope of the tangent to the temperature drift curve of resistor R3 is 0 Assuming the drain current of M35 is Ignoring the high-order temperature coefficients, the current It can be expressed as: , is the temperature-dependent voltage on resistor R4, The temperature at which the slope of the tangent to the temperature drift curve of resistor R4 is 0 The voltage value below for The relative first-order temperature coefficient of , ,get: , and Respectively represent the temperature when the tangent slope of the temperature drift curve on the resistors R1 and R2 is 0 The latter two terms are used for high-order compensation. It can be seen that the CTAT current provided by the subthreshold MOS tube has the following advantages: first, the TlnT term voltage is provided, which can partially offset the TlnT term of VBE and improve the temperature drift performance; and the variable in the compensation term Since all resistors in the circuit are of the same type, represents a constant that is independent of temperature. Finally, the parameter Insensitive to process, the parameters can be adjusted by adjusting the channel width W of M31 and M49 .

[0055] Continue to refer to the above Figure 3In order to make the op amp-free bandgap reference voltage circuit provided by the present invention work in a wider temperature range, the present invention adds high temperature compensation to perform segmented curvature compensation. When the temperature is low, the voltage division on the resistor R6 is small, M48 is in the cut-off region, and no compensation current is generated. On the contrary, when the temperature is higher than a certain level, M48 enters the subthreshold region, and the source current I of M45 hightemp It can be used as the temperature compensation current in the high temperature range. M40 and M41 extract weak compensation current to correct the curvature of the high temperature section, and the temperature range of high temperature compensation can be adjusted by adjusting the resistance value of R6.

[0056] The present invention introduces base compensation for IPTAT curvature correction, introduces a high-order compensation circuit for ICTAT curvature compensation, and introduces segmented curvature compensation for high-temperature intervals that are greatly affected by the process, thereby improving the accuracy and stability of the bandgap reference voltage circuit. Specifically, the present invention has the following beneficial effects:

[0057] 1) Through the base current compensation module, the nonlinearity introduced by the limited amplification factor β of the transistor with temperature changes can be compensated to generate an ideal PTAT current, thereby improving the accuracy and stability of the circuit.

[0058] 2) Through the high-order logarithmic compensation module, the subthreshold MOS tube can be used to generate a high-order temperature positively correlated current, which can be partially offset by the high-order terms of VBE to generate an ideal CTAT current, further improving the accuracy and stability of the circuit.

[0059] 3) By removing the traditional BG op amp and adopting an op amp-free structure, the introduction of op amp noise is avoided and the impact of op amp offset voltage on the bandgap reference voltage is avoided; and a current mirror structure is used to power the bandgap core circuit, thereby improving the power supply rejection ratio.

[0060] 4) Adopt segmented compensation. Specifically, when the temperature is in a non-high temperature range, no compensation current is generated, and when the temperature is in a high temperature range, high temperature compensation is achieved through a subthreshold current.

[0061] 5) The reference output temperature drift can be significantly reduced through compensation of the base current compensation module, the high-order logarithmic compensation module and the high-temperature zone segment compensation module.

[0062] Figure 4 This is the temperature drift curve of the traditional bandgap reference voltage circuit under the worst case; Figure 5 The worst case temperature drift curve of the bandgap reference voltage circuit provided by the present invention. Specifically, Figure 4 and Figure 5 The horizontal axis is temperature (°C), and the vertical axis is output reference voltage (V). Figure 4 The typical TT process angular temperature drift is 42ppm / ℃. Figure 5The typical TT process angular temperature drift is 3.5ppm / ℃. Obviously, the reference output temperature drift is reduced by one order of magnitude through the compensation structure of the present invention.

[0063] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0064] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0065] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0066] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit, characterized in that: include: Start-up module, bandgap reference core module, base current compensation module, high-order logarithmic compensation module and high-temperature zone segment compensation module; The startup module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature segment compensation module are all connected to the power supply V DD The start-up module, the bandgap reference core module, the base current compensation module, the high-order logarithmic compensation module and the high-temperature zone segment compensation module are connected in sequence, and the high-order logarithmic compensation module is also interconnected with the start-up module and the bandgap reference core module respectively; The base current compensation module includes: PMOS tubes M13, M14 and M19-M22, transistor Q3, and NMOS tubes M15-M18 and M23-M26; The source of M13, the source of M19, the source of M21 and the collector of Q3 are all connected to the power supply V DD The gate of M13 is connected to the gate of the PMOS tube M5 and the gate of the PMOS tube M7 in the bandgap reference core module, the drain of M13 is connected to the source of M14, the gate of M14 is connected to the gate of the PMOS tube M6 and the gate of the PMOS tube M8 in the bandgap reference core module, the drain of M14 is connected to the drain of M15, the drain of M15 is connected to the gate of M17 after the gate connection, the source of M15 is connected to the drain of M16, the drain of M16 is connected to the gate of M18 after the gate connection, the source of M16 and the source of M18 are both grounded; the drain of M18 is connected to the source of M17, the drain of M17 is connected to the drain of M23 and the emitter of Q3 The source of M23 is connected to the drain of M24, the source of M24 and the source of M26 are both grounded, the gate of M24 is connected to the gate of M26, the drain of M26 is connected to the source of M25 after the gate is connected, the drain of M25 is connected to the drain of M22 after the gate is connected, the gate of M22 is connected to the gate of M20 and the gate of the PMOS tube M28 in the high-order logarithmic compensation module, the gate of M20 is connected to the base of Q3 after the gate-drain connection, the source of M20 is connected to the drain of M19, the gate of M19 is connected to the gate of M21 and the gate of the PMOS tube M27 in the high-order logarithmic compensation module, and the drain of M21 is connected to the source of M22.

2. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 1, characterized in that: The high-order logarithmic compensation module includes: PMOS tubes M27-M30, M32-M37, transistor Q4, resistors R4 and R5, and NMOS tubes M31 and M49; The gate of M28 is connected to the base current compensation module, the gate of M27 is connected to the base current compensation module, and the source of M27, the source of M29, the source of M32, the source of M34 and the source of M36 are all connected to the power supply V DD , the drain of M27 is connected to the source of M28, the drain of M28 is connected to the collector of Q4, the base of Q4 is connected to the collector, the emitter of Q4 is grounded, the gate of M29 is connected to the gate of the PMOS tube M5 in the bandgap reference core module and the gate of the PMOS tube M38 in the high temperature segment compensation module, the drain of M29 is connected to the source of M30, the gate of M30 is connected to the gate of the PMOS tube M6 in the bandgap reference core module and the gate of the PMOS tube M39 in the high temperature segment compensation module, the drain of M30 is connected to the drain of M31, the drain and gate of M31 are connected to the gate of M49, the source of M31 is connected to the collector of Q4, the source of M49 is connected to one end of R4, and the The other end is grounded, the drain of M49 is connected to the drain of M33, the source of M33 is connected to the drain of M32, the gate of M32 is connected to the gate of M34, the drain of M34 is connected to the source of M35, the gate of M35 is connected to the gate of M33, the drain of M35 is connected to the drain of M37, one end of R5, the gate of the PMOS tube M2 and the gate of the NMOS tube M3 in the startup module, and the drain of the NMOS tube M40 in the high temperature zone segmented compensation module, the other end of R5 is grounded, the source of M37 is connected to the drain of M36, the gate of M37 is connected to the gate of the PMOS tube M39 in the high temperature zone segmented compensation module, and the gate of M36 is connected to the gate of the PMOS tube M38 in the high temperature zone segmented compensation module.

3. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 2, characterized in that: Q3 and Q4 are the same type of NPN tubes, and the ratio of the emitter area of ​​Q3 and Q4 is 4:

1.

4. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 2, characterized in that: The M31 and M49 have the same width-to-length ratio.

5. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 1, characterized in that: The high temperature zone segment compensation module includes: PMOS tubes M38, M39 and M44-M47, resistor R6, and NMOS tubes M40-M43 and M48; The gate of M38 is connected to the gate of the PMOS tube M5 in the bandgap reference core module and the high-order logarithmic compensation module, the gate of M39 is connected to the gate of the PMOS tube M6 in the bandgap reference core module and the high-order logarithmic compensation module, and the source of M38, the source of M44 and the source of M46 are all connected to the power supply V DD The drain of M38 is connected to the source of M39, the drain of M39 is connected to the gate of M48 and one end of R6, the other end of R6 is grounded, the drain of M40 is connected to the high-order logarithmic compensation module, the source of M40 is connected to the drain of M41, the source of M41 is grounded, the source of M43 is grounded, the drain-gate of M43 is connected and then connected to the gate of M41, the drain of M43 is connected to the source of M42, the gate of M42 is connected to the gate of M40, the drain-gate of M42 is connected and then connected to the drain of M45, the source of M45 is connected to the drain of M44, the gate of M44 is connected to the gate of M46, the drain-gate of M46 is connected and then connected to the source of M47, the gate of M47 is connected to the gate of M45, the drain-gate of M47 is connected and then connected to the drain of M48, and the source of M48 is grounded.

6. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 1, characterized in that: The bandgap reference core module includes: PMOS tubes M5-M8, resistors R1-R3, NMOS tubes M9-M12, and transistors Q1 and Q2; The source of M5 and the source of M7 are both connected to the power supply V DD The gate of M5 is connected to the gate of M7 and then connected to the high temperature zone segment compensation module, the base current compensation module and the high order logarithmic compensation module. The gate of M6 is connected to the gate of M8 and then connected to the high temperature zone segment compensation module, the base current compensation module and the high order logarithmic compensation module. The gate of M5 is connected to the drain of M6, the drain of M5 is connected to the source of M6, the drain of M6 is connected to the startup module, and the drain of M6 is also connected to one end of R1, the other end of R1 is connected to the drain of M9, the gate of M6 and the gate of M8, the source of M9 is connected to the drain of M10, and M The gate of M9 is connected to the gate of M11, the gate of M10 is connected to the gate of M12, the source of M10 is connected to one end of R3, the other end of R3 is connected to the collector of Q1, the base of Q1 is connected to the collector, the emitter of Q1 and the emitter of Q2 are both grounded, the base of Q2 is connected to the collector, the collector of Q2 is connected to the source of M12, the gate of M12 is also connected to the drain of M11, the drain of M12 is connected to the source of M11, the drain of M11 is connected to one end of R2, the other end of R2 is connected to the drain of M8, the gate of M9 and the gate of M11, and the source of M8 is connected to the drain of M7.

7. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 6, characterized in that: The emitter area ratio of Q1 and Q2 is 8:

1.

8. The base compensation plus high-order compensation non-op-amp bandgap reference voltage circuit according to claim 1, characterized in that: The startup module includes: PMOS tubes M1 and M2, and NMOS tubes M3 and M4; The source of M1 is connected to the power supply V DD The gate and drain of M1 are connected, and then connected to the source of M2. The drain of M2 is connected to the gate of M4 and the drain of M3. The gate of M3 is connected to the gate of M2 and then connected to the high-order logarithmic compensation module. The source of M3 is grounded. The drain of M4 is connected to the drain of the PMOS tube M6 in the bandgap reference core module, and the source of M4 is grounded.

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