Scheduling method and device, electronic equipment and storage medium
By using bit bits to represent the priority and state of the task function in task scheduling, efficient scheduling of task functions is achieved, solving the problems of large resource occupation and complex scheduling in the existing technology, and improving scheduling efficiency.
Patent Information
- Application Number
- CN202411610959.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-02-18
AI Technical Summary
In the prior art, task scheduling occupies too much internal resources and the scheduling process is complicated, resulting in a reduced efficiency of scheduling tasks.
By determining the list of task functions and sorting the corresponding number of bit bits, the bit bit represents the priority and status of the task function. If the bit bit of the target task function is 1, it will be scheduled and the priority will be followed after success Get the next task function until all task functions are completed.
This method saves resources within the system by effectively using bit bits to represent the task status, reduces the complexity of the scheduling process, and greatly improves the efficiency of the scheduling task.
Smart Images
Figure CN119473551A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of data processing technology, and in particular, relates to a scheduling method, device, electronic device and storage medium. Background Art
[0002] In the related art, in the scheduler of the operating system, the scheduling of tasks mainly adopts the following two methods: the first method is to execute tasks in turn in the main loop in sequence, and the second method is to schedule tasks in a polling manner. Since each task is an independent task stack, these two scheduling methods will cause excessive internal resources to be occupied, the scheduling process is complicated, and the efficiency of scheduling tasks is reduced. Summary of the invention
[0003] The disclosed embodiment provides a solution to solve the problems in the related art that too much internal resources are occupied, the scheduling process is complicated, and the efficiency of the scheduling task is reduced.
[0004] In a first aspect, the present disclosure provides a scheduling method, the method comprising:
[0005] Determine a task function list, wherein the task function list includes a plurality of task functions sorted by priority;
[0006] Determine a preset number of bits corresponding to the task function list, wherein the preset number of bits correspond to the priorities of the multiple task functions from high to low, and the corresponding bit is set to 0 when the task function is in a suspended state, and the corresponding bit is set to 1 when the task function is in a ready state;
[0007] In response to a task function trigger response, obtaining a target task function in the task function list;
[0008] If the bit corresponding to the target task function is 1, schedule the target task function to run;
[0009] If it is detected that the target task function runs successfully, the next task function is obtained according to the priority level until all task functions in the task function list are completed.
[0010] In a second aspect, the present disclosure provides a scheduling device, the device comprising:
[0011] A determination unit, used to determine a task function list, wherein the task function list includes a plurality of task functions sorted according to priority;
[0012] The determining unit is further used to determine a preset number of bits corresponding to the task function list, wherein the preset number of bits respectively correspond to the priorities of the multiple task functions from high to low, and when the task function is in a suspended state, the corresponding bit is set to 0, and when the task function is in a ready state, the corresponding bit is set to 1;
[0013] An acquisition unit, configured to acquire a target task function in the task function list in response to a task function trigger response;
[0014] A scheduling unit, configured to schedule the target task function to run if the bit corresponding to the target task function is 1;
[0015] The detection unit is used to obtain the next task function according to the priority level if it is detected that the target task function is successfully executed, until all the task functions in the task function list are completed.
[0016] In a third aspect, the present disclosure provides an electronic device, including:
[0017] Processor; and
[0018] A memory, configured to store executable instructions of the processor;
[0019] The processor is configured to execute any method in the first aspect or any possible implementation of the first aspect by executing the executable instructions.
[0020] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the computer program implements any method in the first aspect or any possible implementation of the first aspect.
[0021] The technical solution provided by the present disclosure is to determine a task function list, wherein the task function list includes multiple task functions sorted by priority; determine a preset number of bits corresponding to the task function list, wherein the preset number of bits correspond to the priorities of the multiple task functions from high to low, and the corresponding bit is set to 0 when the task function is in a suspended state, and the corresponding bit is set to 1 when the task function is in a ready state; in response to a task function trigger response, obtain the target task function in the task function list; if the bit corresponding to the target task function is 1, schedule the target task function to run; if it is detected that the target task function runs successfully, obtain the next task function according to the priority level until all task functions in the task function list are completed. The technical solution provided by each embodiment of the present disclosure represents whether the task function is suspended or ready through the numerical value on the preset number of bits, and if the bit corresponding to the target task function is 1, schedule the target task function to run, if it is detected that the target task function runs successfully, obtain the next task function according to the priority level until all task functions in the task function list are completed, saving resources within the system, reducing the scheduling process, and greatly improving the efficiency of scheduling. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0023] Figure 1 A flowchart of a scheduling method provided by an embodiment of the present disclosure;
[0024] Figure 2 A flowchart of another scheduling method provided by an embodiment of the present disclosure;
[0025] Figure 3 A schematic diagram of the structure of a scheduling device provided in one embodiment of the present disclosure;
[0026] Figure 4 A schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0027] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.
[0028] The terms "first" and "second" and the like in the specification, claims, and drawings of the disclosed embodiments are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the disclosed embodiments described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.
[0029] The scheduling method provided in the embodiments of the present disclosure may be run on a terminal device, a management server or a single-chip microcomputer. The terminal device may be a local terminal device. The management server may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.
[0030] In the related art, in the scheduler of the operating system, the scheduling of tasks mainly adopts the following two methods: the first method is to execute tasks in turn in the main loop in sequence, and the second method is to schedule tasks in a polling manner. Since each task is an independent task stack, these two scheduling methods will cause excessive internal resources to be occupied, the scheduling process is complicated, and the efficiency of scheduling tasks is reduced.
[0031] The following specific embodiments are used to describe in detail the technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.
[0032] Figure 1 A flowchart of a scheduling method provided by an exemplary embodiment of the present disclosure is provided. The method can be applied to various devices with data processing functions. Taking the method applied to a single-chip microcomputer as an example, the scheme at least includes the following steps S101-S105:
[0033] S101, determine a task function list.
[0034] In some embodiments, the task function list includes a plurality of task functions sorted by priority.
[0035] In other embodiments, the task function list also includes a function entry pointer corresponding to each task function, and each function entry pointer is sorted from high to low, or from low to high according to the priority of the task function.
[0036] Among them, the function entry pointer is used to call the function, which is a pointer variable pointing to the function, that is, an entry address of the task function.
[0037] S102, determining the task state variables corresponding to the task function list.
[0038] The task status variable is represented by a preset number of bits.
[0039] In some embodiments, a byte has 8 bits. Therefore, in actual calculation, the preset number is preferably 8. It can also be other numbers of bits, which can be set according to actual conditions.
[0040] In other embodiments, the task state variable may be represented by a string of letters, which may be set according to actual conditions.
[0041] In some embodiments, the preset number of bits correspond to the priorities of the multiple task functions from high to low, wherein the corresponding bit is set to 0 when the task function is in a suspended state, and the corresponding bit is set to 1 when the task function is in a ready state.
[0042] Specifically, for example, the task function list contains eight task functions, which are task function 1 to task function 8 according to priority, among which task function 1 to task function 4 are in ready state, and task function 5 to task function 8 are in suspended state, and the eight bits are 11110000.
[0043] In some embodiments, the suspended state refers to that the code data resources of the process temporarily leave the memory and enter the peripheral device. Specifically, in this embodiment, the task function being in the suspended state means that the task function is not scheduled.
[0044] In some embodiments, the ready state means that the process has been allocated all necessary resources except the CPU and can be executed immediately as long as the CPU permission is obtained.
[0045] In some embodiments, the preset number of bits correspond one-to-one to the priorities of the multiple task functions from high to low, or from high to low.
[0046] In this embodiment, the high bit refers to the leftmost position, and the low bit refers to the rightmost position.
[0047] Specifically, for example, the task function list includes eight task functions, which are task function 1 to task function 8 according to the priority level, among which task function 1 to task function 4 are in ready state, and task function 5 to task function 8 are in suspended state. The eight bits from low to high correspond one-to-one with the priorities of the multiple task functions from high to low, which can be 00001111; the eight bits from low to high correspond one-to-one with the priorities of the multiple task functions from high to low, which can be 11110000.
[0048] In some embodiments, the preset number is greater than or equal to the number of task functions in the task function list.
[0049] Specifically, for example, the task function list contains eight task functions, which are task function 1 to task function 8 according to priority, among which task function 1 to task function 4 are in ready state, task function 5 to task function 8 are in suspended state, and the preset number is 16, then the 16 bits are 0000000011110000 or 11110000000000000.
[0050] In this embodiment, if the preset number is greater than the number of task functions in the task function list, the redundant bits are set to 0 or 1. The specific setting can be made according to the actual situation.
[0051] S103, in response to a task function triggering response, obtaining a target task function in the task function list.
[0052] In some embodiments, in response to a task function trigger response, a task function with the highest priority in the task function list is obtained, and the task function is used as a target task function.
[0053] Specifically, taking a single-chip microcomputer product as an example, if the single-chip microcomputer wants to call each task function in the task function list, after responding to the task function trigger response, the task function with the highest priority in the task function list will be used as the target task function, and then the target task function will be processed.
[0054] S104: If the bit corresponding to the target task function is 1, schedule the target task function to run.
[0055] In some embodiments, scheduling the target task function to run includes: dividing the target task function into a plurality of target subtask functions, and scheduling the plurality of target subtask functions to run.
[0056] Specifically, when the bit corresponding to the target task function is 1, it means that the target task function is in a ready state, so it can be scheduled for operation. In order to increase the speed of running the target task function, the target task function can be divided into multiple target sub-task functions, and all target sub-task functions can be scheduled simultaneously.
[0057] For example, the task corresponding to the target task function is to copy, save and share data A. This target task function can be divided into two target sub-task functions, namely, copying and saving data A, and sharing data A, thereby realizing the simultaneous copying and saving of data A, and sharing of data A. This operation method can greatly improve the running speed of the target task function.
[0058] S105: If it is detected that the target task function is successfully executed, the next task function is obtained according to the priority level until all the task functions in the task function list are completed.
[0059] In some embodiments, after detecting that the target task function is executed successfully, the method further includes: setting a bit corresponding to the target task function to 0.
[0060] Specifically, in order to ensure that the target task function that has been successfully run is repeatedly run, after detecting that the target task function has been successfully run, the running state of the target task function is adjusted to a suspended state, that is, the bit corresponding to the target task function is set to 0.
[0061] In some embodiments, the method further includes: if the bit corresponding to the target task function is 0, obtaining the next task function according to the priority level until all task functions in the task function list are completed.
[0062] Specifically, when the bit corresponding to the target task function is 0, the running state of the target task function is a suspended state, which means that the target task function does not need to be scheduled, so it is necessary to determine the next task function as the new target task function according to the priority level of the task function.
[0063] For example, the task function list includes eight task functions, which are task function 1 to task function 8 according to the priority level, wherein task function 1 to task function 4 are in suspended state, task function 5 to task function 8 are in ready state, 8 bits are 00001111, and when the target task function is task function 4, the bit corresponding to task function 4 is 0, so it is not necessary to schedule task function 4, and then the task function 5 of the next priority level of task function 4 is used as the target task function, and the processing is continued until all task functions in the task function list are completed. In this embodiment, in the task function list, when there is a target task function in suspended state, when calling, the target task function is not called, but the next task function is obtained according to the priority level. Through this operation mode, unnecessary workload can be reduced, and the efficiency of scheduling can be improved.
[0064] In some embodiments, after all the task functions in the task function list are completed, the method further comprises: re-determining a preset number of bits corresponding to the task function list according to the running status of each task function in the task function list. Specifically,
[0065] In order to better understand the present solution, a specific embodiment is provided below to further illustrate the scheduling solution of the present disclosure. Figure 2 As shown, the details are as follows:
[0066] The task function list contains three task functions, which are task function 1, task function 2, and task function 3 in descending order of priority. The bit corresponding to task function 1 is 1, the bit corresponding to task function 2 is 0, and the bit corresponding to task function 3 is 1.
[0067] S201, in response to a task function trigger response, obtaining task function 1 in a task function list.
[0068] S202, determine whether the bit corresponding to task function 1 is 1.
[0069] S203: If yes, schedule task function 1 to run.
[0070] S204: If it is detected that task function 1 runs successfully, task function 2 is obtained according to the priority level.
[0071] S205: If not, obtain task function 2 according to the priority level.
[0072] S206, determining whether the bit corresponding to task function 2 is 1.
[0073] S207: If yes, schedule task function 2 to run.
[0074] S208: If it is detected that task function 2 runs successfully, task function 3 is obtained according to the priority level.
[0075] S209: If not, obtain task function 3 according to the priority level.
[0076] S210, determining whether the bit corresponding to task function 3 is 1.
[0077] S211, if yes, schedule task function 3 to run.
[0078] S212: If it is detected that task function 3 runs successfully, end the operation.
[0079] S213, if not, end the operation.
[0080] The technical solution provided by the present disclosure is to determine a task function list, wherein the task function list includes multiple task functions sorted by priority; determine a preset number of bits corresponding to the task function list, wherein the preset number of bits correspond to the priorities of the multiple task functions from high to low, and the corresponding bit is set to 0 when the task function is in a suspended state, and the corresponding bit is set to 1 when the task function is in a ready state; in response to a task function trigger response, obtain the target task function in the task function list; if the bit corresponding to the target task function is 1, schedule the target task function to run; if it is detected that the target task function runs successfully, obtain the next task function according to the priority level until all task functions in the task function list are completed. The technical solution provided by each embodiment of the present disclosure represents whether the task function is suspended or ready through the numerical value on the preset number of bits, and if the bit corresponding to the target task function is 1, schedule the target task function to run, if it is detected that the target task function runs successfully, obtain the next task function according to the priority level until all task functions in the task function list are completed, saving resources within the system, reducing the scheduling process, and greatly improving the efficiency of scheduling.
[0081] Figure 3 A schematic diagram of the structure of a scheduling device provided by an exemplary embodiment of the present disclosure;
[0082] The device includes: a determination unit 301, an acquisition unit 302, a scheduling unit 303 and a detection unit 304;
[0083] A determination unit 301 is used to determine a task function list, wherein the task function list includes a plurality of task functions sorted by priority;
[0084] The determining unit 301 is further used to determine a preset number of bits corresponding to the task function list, wherein the preset number of bits respectively correspond to the priorities of the multiple task functions from high to low, and when the task function is in a suspended state, the corresponding bit is set to 0, and when the task function is in a ready state, the corresponding bit is set to 1;
[0085] An acquisition unit 302 is used to acquire a target task function in the task function list in response to a task function trigger response;
[0086] A scheduling unit 303 is used to schedule the target task function to run if the bit corresponding to the target task function is 1;
[0087] The detection unit 304 is used to obtain the next task function according to the priority level if it is detected that the target task function is successfully executed, until all the task functions in the task function list are completed.
[0088] In some embodiments, after detecting that the target task function is executed successfully, the device is further used to: set the bit corresponding to the target task function to 0.
[0089] In some embodiments, the preset number of bits correspond one-to-one to the priorities of the multiple task functions from high to low, or from high to low.
[0090] In some embodiments, the preset number is greater than or equal to the number of task functions in the task function list.
[0091] In some embodiments, the scheduling of the target task function execution, the apparatus is further configured to:
[0092] The target task function is divided into a plurality of target subtask functions, and the plurality of target subtask functions are scheduled to run.
[0093] In some embodiments, the device is further used to:
[0094] If the bit corresponding to the target task function is 0, the next task function is obtained according to the priority level until all task functions in the task function list are completed.
[0095] In some embodiments, until all the task functions in the task function list are completed, the device is further used to:
[0096] According to the running status of each task function in the task function list, a preset number of bits corresponding to the task function list is re-determined.
[0097] The technical solution provided by the present disclosure is to determine a task function list, wherein the task function list includes multiple task functions sorted by priority; determine a preset number of bits corresponding to the task function list, wherein the preset number of bits correspond to the priorities of the multiple task functions from high to low, and the corresponding bit is set to 0 when the task function is in a suspended state, and the corresponding bit is set to 1 when the task function is in a ready state; in response to a task function trigger response, obtain the target task function in the task function list; if the bit corresponding to the target task function is 1, schedule the target task function to run; if it is detected that the target task function runs successfully, obtain the next task function according to the priority level until all task functions in the task function list are completed. The technical solution provided by each embodiment of the present disclosure represents whether the task function is suspended or ready through the numerical value on the preset number of bits, and if the bit corresponding to the target task function is 1, schedule the target task function to run, if it is detected that the target task function runs successfully, obtain the next task function according to the priority level until all task functions in the task function list are completed, saving resources within the system, reducing the scheduling process, and greatly improving the efficiency of scheduling.
[0098] It should be understood that the device embodiment and the method embodiment may correspond to each other, and similar descriptions may refer to the method embodiment. To avoid repetition, no further description is given here. Specifically, the device may perform the above method embodiment, and the above and other operations and / or functions of each module in the device are the corresponding processes in each method in the above method embodiment, respectively, and no further description is given here for the sake of brevity.
[0099] The above describes the device of the embodiment of the present disclosure from the perspective of the functional module in conjunction with the accompanying drawings. It should be understood that the functional module can be implemented in hardware form, can be implemented by instructions in software form, and can also be implemented by a combination of hardware and software modules. Specifically, the steps of the method embodiment in the embodiment of the present disclosure can be completed by the hardware integrated logic circuit and / or software form instructions in the processor, and the steps of the method disclosed in conjunction with the embodiment of the present disclosure can be directly embodied as a hardware decoding processor to execute, or a combination of hardware and software modules in the decoding processor to execute. Optionally, the software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method embodiment in conjunction with its hardware.
[0100] Figure 4 is a schematic block diagram of an electronic device provided by an embodiment of the present disclosure, and the electronic device may include:
[0101] The memory 401 and the processor 402, the memory 401 is used to store the computer program and transmit the program code to the processor 402. In other words, the processor 402 can call and run the computer program from the memory 401 to implement the method in the embodiment of the present disclosure.
[0102] For example, the processor 402 may be configured to execute the above method embodiments according to instructions in the computer program.
[0103] In some embodiments of the present disclosure, the processor 402 may include but is not limited to:
[0104] General-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.
[0105] In some embodiments of the present disclosure, the memory 401 includes but is not limited to:
[0106] Volatile memory and / or non-volatile memory. Among them, the non-volatile memory can be read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).
[0107] In some embodiments of the present disclosure, the computer program may be divided into one or more modules, which are stored in the memory 401 and executed by the processor 402 to complete the method provided by the present disclosure. The one or more modules may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.
[0108] like Figure 4 As shown, the electronic device may also include:
[0109] The transceiver 403 may be connected to the processor 402 or the memory 401 .
[0110] The processor 402 may control the transceiver 403 to communicate with other devices, specifically, to send information or data to other devices, or to receive information or data sent by other devices. The transceiver 403 may include a transmitter and a receiver. The transceiver 403 may further include an antenna, and the number of antennas may be one or more.
[0111] It should be understood that the various components in the electronic device are connected via a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus and a status signal bus.
[0112] The present disclosure also provides a computer storage medium on which a computer program is stored, and when the computer program is executed by a computer, the computer can perform the method of the above method embodiment. In other words, the present disclosure embodiment also provides a computer program product containing instructions, and when the instructions are executed by a computer, the computer can perform the method of the above method embodiment.
[0113] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a solid state disk (solid state disk, SSD)), etc.
[0114] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.
[0115] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0116] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. For example, each functional module in each embodiment of the present disclosure may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
[0117] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A scheduling method, characterized in that: The method comprises: Determine a task function list, wherein the task function list includes a plurality of task functions sorted by priority; Determine a task state variable corresponding to the task function list, wherein the task state variable is represented by a preset number of bits, wherein the preset number of bits correspond to the priorities of the multiple task functions from high to low, and when the task function is in a suspended state, the corresponding bit is set to 0, and when the task function is in a ready state, the corresponding bit is set to 1; In response to a task function trigger response, obtaining a target task function in the task function list; If the bit corresponding to the target task function is 1, schedule the target task function to run; If it is detected that the target task function runs successfully, the next task function is obtained according to the priority level until all task functions in the task function list are completed.
2. The method according to claim 1, characterized in that After detecting that the target task function is executed successfully, the method further includes: setting a bit corresponding to the target task function to 0.
3. The method according to claim 1, characterized in that The preset number of bits correspond one-to-one to the priorities of the multiple task functions from high to low, or from high to low.
4. The method according to claim 3, characterized in that The preset number is greater than or equal to the number of task functions in the task function list.
5. The method according to claim 1, characterized in that The scheduling of the target task function to run includes: The target task function is divided into a plurality of target subtask functions, and the plurality of target subtask functions are scheduled to run.
6. The method according to claim 1, characterized in that The method further comprises: If the bit corresponding to the target task function is 0, the next task function is obtained according to the priority level until all task functions in the task function list are completed.
7. The method according to claim 1, characterized in that After all the task functions in the task function list have been executed, the method further comprises: According to the running status of each task function in the task function list, a preset number of bits corresponding to the task function list is re-determined.
8. A scheduling device, characterized in that: The device comprises: A determination unit, used to determine a task function list, wherein the task function list includes a plurality of task functions sorted according to priority; The determining unit is further used to determine a preset number of bits corresponding to the task function list, wherein the preset number of bits respectively correspond to the priorities of the multiple task functions from high to low, and when the task function is in a suspended state, the corresponding bit is set to 0, and when the task function is in a ready state, the corresponding bit is set to 1; An acquisition unit, configured to acquire a target task function in the task function list in response to a task function trigger response; A scheduling unit, configured to schedule the target task function to run if the bit corresponding to the target task function is 1; The detection unit is used to obtain the next task function according to the priority level if it is detected that the target task function is successfully executed, until all the task functions in the task function list are completed.
9. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to perform the method of any one of claims 1 to 7 by executing the executable instructions.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.