Method and device for converting AXI bus from low bit width to high bit width and low delay, terminal and data transmission system

Abstract

The invention provides an AXI bus low-bit-width-to-high-bit-width low-delay conversion method and device, a terminal and a data transmission system, and the method comprises the steps: receiving an AXI transmission command transmitted from a low-bit-width data end to a high-bit-width data end, and transmitting the received to-be-transmitted data subjected to bit width conversion through an AXI bus according to a preset transmission mode, and when a data channel response signal is received, ending the operation of the current command. According to the invention, the delay of data reading and writing is reduced in bit width conversion, and the efficiency of the AXI bus can be further improved.

Description

Technical Field

[0001] The present invention relates to the field of data transmission, and in particular to a method, device, terminal and data transmission system for converting an AXI bus from low bit width to high bit width with low delay. Background Art

[0002] The AXI protocol is an on-chip bus for high performance, high bandwidth, and low latency. The AXI bus is a multi-channel transmission bus that sends write addresses, write data, write responses, read addresses, read data, and responses in different channels. Master devices and slave devices can be flexibly connected based on the AXI bus, but when the data bit widths of the master and slave devices are inconsistent, the data bit widths need to be matched through a bus bit width conversion device. In the AXI protocol, processing data transmission from a low-bit width data end to a high-bit width data end is a common requirement, especially when data from different sources (such as peripherals, smaller processor cores, etc.) needs to be integrated into a wider data bus or processing unit. The AXI protocol itself supports flexible data widths, but automatic conversion directly from a fixed low bit width to a high bit width is not a feature directly provided by the AXI protocol. This usually requires additional logic design at the source or destination of the data transmission to achieve.

[0003] In the existing AXI bus data low-width to high-width conversion device design, the data is generally written into a storage space such as FIFO (First In First Out) or RAM (Random Access Memory) in each channel first, and then the data is read from the storage space such as FIFO or RAM, which inevitably increases the delay of AXI bus data conversion and reduces the efficiency of the AXI bus. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method, device, terminal and data transmission system for converting low-bit-width to high-bit-width with low delay of an AXI bus, so as to solve the technical problem that in the prior art, data is first written into a storage space such as a FIFO or RAM in each channel, and then the data is read from the storage space such as the FIFO or RAM, which inevitably increases the delay of the AXI bus data conversion and reduces the efficiency of the AXI bus.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for converting low-bit-width to high-bit-width with low latency of an AXI bus, the method comprising: receiving a data transmission command sent from a low-bit-width data end to a high-bit-width data end; sending data converted from the received data to be sent through the AXI bus according to a preset sending mode; and ending the operation of the current data transmission command when a data channel response signal is received.

[0006] In an embodiment of the present invention, the data transmission command corresponds to a transmission type, which includes: a data address, a data bit width, and a data transmission length.

[0007] In one embodiment of the present invention, the method includes: receiving a write address transmission signal transmitted by a low-width data end through a write address channel, sending high-width data that has undergone bit width conversion from low-width data transmitted by the low-width data end through the write data channel to a high-width data end through an AXI bus using a preset write transmission mode, and ending the current write data transmission operation when receiving a write response channel signal fed back by the high-width data end through a write response channel after data writing is completed.

[0008] In one embodiment of the present invention, the preset write transmission mode includes: a first preset write transmission mode, including: based on the data bit width size in the write address transmission signal and the data transmission length, matching the data bit width size for the high bit width data end, and adjusting the data transmission length accordingly; whenever the received low bit width data reaches the data bit width size of the high bit width data end through shift registration, the data is sent to the high bit width data end until all the data is sent; a second preset write transmission mode, including: mapping the low bit width data received in sequence to the high bit width data bits adapted to the high bit width data end according to the write address in the write address transmission signal, and using the valid byte signal to identify the valid low bit width data in the current high bit width data, and sending it to the high bit width data end until all the data is sent.

[0009] In one embodiment of the present invention, the method includes: receiving a read address transmission signal transmitted by a low-width data end through a read address channel, sending low-width data converted from high-width data transmitted by the high-width data end through the read data channel to the low-width data end through an AXI bus using a preset read transmission mode, and ending the current read data transmission operation when receiving a read response channel signal fed back by the high-width data end through a read data response channel after data reading is completed.

[0010] In one embodiment of the present invention, the preset read and send mode includes: a first preset read and send mode, including: based on the data bit width size in the read address transmission signal and the data transmission length, matching the data bit width size for the high bit width data end, and adjusting the data transmission length accordingly; shifting and converting the high bit width data received in sequence into low bit width data according to the data bit width size in the read address transmission command, and sending them to the low bit width data end in sequence until all the data are sent; a second preset read and send mode, including: according to the read address in the read channel transmission signal, intercepting the corresponding low bit width data in the received high bit width data, and sending them to the low bit width data end in sequence until all the data are sent.

[0011] In one embodiment of the present invention, the high-bitwidth data received in the second preset read transmission mode is obtained by the high-bitwidth data end mapping each read data required by the low-bitwidth data end to the adapted high-bitwidth data bit according to the read address.

[0012] To achieve the above-mentioned purpose and other related purposes, the present invention provides an AXI bus low-width to high-width low-delay conversion device, which is arranged between the low-width data end and the high-width data end, and the device is used for the AXI bus low-width to high-width low-delay conversion method.

[0013] To achieve the above-mentioned purpose and other related purposes, the present invention provides an electronic terminal, comprising: one or more memories and one or more processors; the one or more memories are used to store computer programs; the one or more processors are connected to the memories and are used to run the computer program to execute the AXI bus low-width to high-width low-latency conversion method.

[0014] To achieve the above-mentioned purpose and other related purposes, the present invention provides a data transmission system based on the conversion of low-width to high-width and low-latency of an AXI bus, the system comprising: a low-width data terminal, a high-width data terminal and an AXI bus low-width to high-width and low-latency conversion device capable of executing the AXI bus low-width to high-width and low-latency conversion method; wherein the AXI bus low-width to high-width and low-latency conversion device is arranged between the low-width data terminal and the high-width data terminal.

[0015] As described above, the present invention is a method, device, terminal and data transmission system for converting low bit width to high bit width with low delay of AXI bus, which has the following beneficial effects: the present invention receives an AXI transmission command sent from a low bit width data end to a high bit width data end, and sends data converted from the received data to be sent through the AXI bus according to a preset transmission mode, and ends the operation of the current command when a data channel response signal is received. The present invention reduces the delay of data reading and writing in bit width conversion, and can further improve the efficiency of the AXI bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic flow chart of a method for converting an AXI bus from low bit width to high bit width with low latency in one embodiment of the present invention.

[0017] Figure 2 Shown is a schematic flow chart of a write data transmission operation in an embodiment of the present invention.

[0018] Figure 3 It is a schematic diagram showing the flow of a read data transmission operation in one embodiment of the present invention.

[0019] Figure 4 Shown is a schematic structural diagram of an electronic terminal in an embodiment of the present invention.

[0020] Figure 5 It is a schematic diagram of the structure of a data transmission system based on AXI bus low-bit width to high-bit width and low-delay conversion in one embodiment of the present invention.

[0021] Figure 6 It is a schematic diagram of the structure of a data transmission system based on low bit width to high bit width conversion between a master end and a slave end in one embodiment of the present invention.

[0022] Figure 7 It is a schematic diagram of the structure of a data transmission system based on AXI bus low-bit width to high-bit width and low-delay conversion in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0025] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0026] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0027] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0028] The present invention provides an AXI bus low-bit width to high-bit width low-delay conversion method, receiving an AXI transmission command sent from a low-bit width data end to a high-bit width data end, and sending data converted from the received data to be sent through the AXI bus according to a preset sending mode, and when a data channel response signal is received, the operation of the current command is terminated. The present invention reduces the delay of data reading and writing in bit width conversion, and can further improve the efficiency of the AXI bus.

[0029] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0030] like Figure 1 A flowchart of a method for converting a low-bit-width AXI bus to a high-bit-width low-latency bus in an embodiment of the present invention is shown.

[0031] The method comprises:

[0032] Step S1: receiving a data transmission command sent from a low-bit-width data terminal to a high-bit-width data terminal.

[0033] Step S2: sending the data to be sent after bit width conversion through the AXI bus according to a preset sending mode.

[0034] Step S3: When the data channel response signal is received, the operation of the current data transmission command is terminated.

[0035] In one embodiment, when the low-width data terminal needs to send data to the high-width data terminal, a data transfer command corresponding to a transfer type (such as read / write) is first issued. In this scenario, the command specifically indicates that the data will be transferred from the low-width data terminal to the high-width data terminal.

[0036] Data transmission commands include at least the following:

[0037] Data address, which gives the address of the first data in a burst transfer; if the transfer type is a write transfer, it is the write address; if the transfer type is a read transfer, it is the read address.

[0038] Data transfer length, giving the exact number of data in a burst transfer;

[0039] The data bit width indicates the size of the data transmitted in a single time.

[0040] The transmission types involved in the present invention are write data transmission and read data transmission. Now, in conjunction with the following specific embodiments, the method for converting the low-bit width of the AXI bus to a high-bit width with low latency under the two transmission modes is described.

[0041] In one embodiment, if the low-width data end has a need to write data to the high-width data end, a write command needs to be sent first; in the AXI protocol, a write operation usually involves multiple channels, including a write address channel (AW), a write data channel (W), and a write response channel (B). Figure 2 , the specific conversion methods include:

[0042] Receive the write address channel signal sent by the low-bit-width data end through the write address channel. This signal will contain key information such as write address, data bit width, data transmission length, etc.

[0043] Receive low-bit-width data sent by the low-bit-width data end through a write data channel; wherein the low-bit-width data is implemented as a write data channel signal, which at least includes: write data (WDATA) and a write byte valid signal (WSTRB).

[0044] The high-bit-width data after bit-width conversion is sent to the high-bit-width data terminal through the AXI bus using the preset write-send mode;

[0045] When the write response channel signal fed back by the high-bit-width data end through the write response channel after the data writing is completed is received, the current write data transmission operation is ended; wherein, the write response channel signal (BRESP) indicates the status of the write operation, such as whether the write operation is successful or failed.

[0046] In one embodiment, the preset write transmission modes include the following two modes, which can be set according to requirements:

[0047] The first preset write transmission mode mainly adjusts and matches the data width size (AWSIZE) and data transmission length (AWLEN) to the requirements of the high-width data end according to the width and data transmission length of the low-width data, and then combines and sends the data. The specific modes include:

[0048] Since the bit widths of the low-width data end and the high-width data end are inconsistent, the data bit width size (AWSIZE) and the data transmission length (AWLEN) need to be matched and converted. The data bit width size (AWSIZE) and the data transmission length (AWLEN) in the write address transmission signal sent by the low-width data end are matched to the data bit width size of the high-width data end, and the data transmission length is adjusted accordingly; this usually involves increasing AWSIZE and reducing AWLEN accordingly, because the total length of the data is fixed at the byte level, but when it is sent at a high bit width, the number of transmission units required will be reduced.

[0049] Whenever the received low-bit-width data reaches the data bit width size of the high-bit-width data terminal through shift register, the data is sent to the high-bit-width data terminal until all the data are sent.

[0050] The advantage of this mode is that the number of data sent is small, and it can adapt to the data transmission requirements of different bit widths. By dynamically adjusting the transmission length and packaging method, it ensures the smooth transmission of data. By adjusting data packaging and transmission length, the risk of data loss and damage during transmission is reduced, and the integrity of the data is guaranteed.

[0051] The second preset write transmission mode mainly maps the low-width data to the corresponding position of the high-width data according to the write address, and uses the valid byte signal to identify the valid data part. The specific modes include:

[0052] The low-width data received in sequence are mapped to the high-width data bits adapted to the high-width data end according to the write address in the write address transmission command, and the valid low-width data in the current high-width data is identified by a valid byte signal, and sent to the high-width data end until all the data of the data transmission length in the write address transmission command are sent.

[0053] Specifically, the data from the low-width data end is received in sequence, and the data is mapped to the high-width data bit according to the write address in the write address transmission command. For the data bit that does not contain valid low-width data, the bit is kept unchanged or set to an invalid value. A valid byte signal is used to identify which bytes in the high-width data are valid low-width data, and is sent to the high-width data end until all the data is sent. The valid byte signal is such as the WSTRB signal in the AXI protocol. The WSTRB signal is a binary vector with the same bit width as the slave data, but contains only two values: 0 (indicating invalid data) and 1 (indicating valid data).

[0054] This mode reduces the data packing and unpacking overhead during transmission and avoids unnecessary bit width conversion, thus significantly improving the efficiency of data transmission. There is no need to match AWSIZE and AWLEN, making the data transmission process more direct and simple, reducing processing steps and potential sources of error, and improving system stability and reliability.

[0055] The two preset write and send modes each have their own characteristics and advantages. The first preset write and send mode is more suitable for scenarios that need to process data transmission of different bit widths, and ensures data integrity and efficient transmission through flexible data packaging and transmission length adjustment. The second preset write and send mode is more suitable for scenarios with high requirements for data transmission efficiency, and improves data transmission efficiency and overall system performance by simplifying the processing flow and reducing overhead. In actual applications, the appropriate mode should be selected according to specific needs and system environment.

[0056] For example, if the master end is a low-width data end with a data width of 8 bits, and the slave end is a high-width data end with a data width of 16 bits, and data needs to be written from the master end to the slave end, the write address transmission signal sent by the master end specifies that the write address is 0, the bit width is 8 bits, and the write length is 8 (D0, D1, D2, D3, D4, D5, D6, D7).

[0057] The method of using the first preset write transmission mode specifically includes: firstly matching the data bit width and length sent from the master end to the specifications required by the slave end, the data bit width becomes 16 bits, and the length becomes 4; firstly shifting and registering the master end data, obtaining the first complete data D00{D1, D0} to be sent from the slave end, sending the data D00 to the slave end, and then continuing to send the next data D01{D3, D2} to be sent after the slave end obtains it, until the sending of D02{D5, D4} and D03{D7, D6} is completed;

[0058] The method of adopting the second preset write transmission mode specifically includes: according to the bit width and length transmitted from the master end, each data sent from the master end is mapped to the high-bit width data bit of the slave end according to the address. Since the slave end is 16 bits wide, each master end data will occupy one byte (8 bits) of the slave end data, and the other byte (8 bits) will be regarded as invalid data (usually represented by xx), and at the same time, a corresponding WSTRB signal is generated for each slave end data. For each slave end data, the WSTRB signal will have two bits, one corresponding to the lower 8 bits of the slave end data, and the other corresponding to the upper 8 bits. For the master end D0, its corresponding data on the slave end is D00{xx, D0} (xx represents invalid data), and wstrb00 is 2'b01 (0 represents invalid data, 1 represents valid data); for the master end data D1, its corresponding data on the slave end is D01{D1, xx}, and wstrb01 is 2'b10; for the master end D2, its corresponding data on the slave end is D02{xx, D2}, and wstrb02 is 2'b01; for the master end data D3, its corresponding data on the slave end is D03{D3, xx}, and wstrb01 is 2'b10; and so on until the last master end data D7, its corresponding data on the slave end is D07{D7, xx} and wstrb07 is 2'b10, and the writing is completed.

[0059] In one embodiment, if the low-width data end has a data read requirement from the high-width data end, a read command needs to be sent first; in the AXI protocol, a read operation usually involves multiple channels, including a read address channel (AR) and a read data response channel (R), wherein the read data response channel includes a read data channel. Figure 3 , the specific conversion methods include:

[0060] Receive the read address transmission signal transmitted by the low-bit-width data end through the read address channel. This signal will contain key information such as the read address, data bit width, and data transmission length;

[0061] Receive high-bit-width data transmitted by the high-bit-width data end through a read data channel; wherein the high-bit-width data is implemented as a read data channel signal, including at least: read-in data (RDATA), a read response (RRESP) and a read byte valid signal (RVALID).

[0062] Using a preset read-send mode, the converted low-bit-width data is sent to the low-bit-width data terminal through the AXI bus;

[0063] When receiving the read response channel signal fed back by the high-bit-width data end through the read data response channel after the data is read, the current read data transmission operation is terminated, wherein the read response channel signal indicates the status of the read operation, such as success or failure of the read operation.

[0064] In one embodiment, the preset read and send modes include the following two, which can be set according to requirements:

[0065] The first preset read transmission mode includes: since the bit widths of the low-bit width data end and the high-bit width data end are inconsistent, it is necessary to match and convert the data bit width size (ARSIZE) and the data transmission length (ARLEN). The data bit width size (ARSIZE) and the data transmission length (ARLEN) in the read address transmission signal are used to match the data bit width size of the high-bit width data end, and the data transmission length is adjusted accordingly.

[0066] The sequentially received high-bit-width data are shifted and converted into low-bit-width data according to the data bit-width size in the read address transmission command, and are sequentially sent to the low-bit-width data terminal until all the data are sent.

[0067] This mode enables processing of data read requests of different bit widths and lengths, thus meeting diverse data interaction requirements. By matching and converting bit widths before sending data, it can ensure that the data sent to the low-bit width data end meets the requirements in both bit width and length, thus avoiding data truncation or misalignment and ensuring data integrity.

[0068] The second preset read and send mode includes:

[0069] In this mode, the read address transfer command of the low-width data end is sent directly, and there is no need to match and convert ARSIZE and ARLEN. The high-width data end maps each read data required in the low-width data end read address transfer command to the adaptable high-width data bit according to the read address to obtain high-width data.

[0070] According to the read address in the read channel transmission signal, the corresponding low-bit-width data is intercepted from the received high-bit-width data, and is sent to the low-bit-width data end in sequence until all the data is sent.

[0071] This mode does not require additional matching or conversion of ARSIZE and ARLEN, thus simplifying the processing flow of data reading and sending. This enables the system to process data read requests more efficiently, reducing processing complexity and latency. Since the required data is directly retrieved and intercepted from the high-bit width data end, the intermediate links of data conversion and processing are reduced, thus significantly improving the efficiency of data transmission.

[0072] The two preset read and send modes each have their own advantages, and which mode to choose depends on the specific application scenario and requirements. If the system needs to process data read requests of multiple bit widths and lengths, and has high requirements for data integrity and performance, the first preset read and send mode may be more suitable. If the system mainly processes data read requests of fixed bit widths and lengths, and has high requirements for data transmission efficiency and resource consumption, the second preset read and send mode may be more suitable.

[0073] For example, if the master end is a low-width data end with a data width of 8 bits, and the slave end is a high-width data end with a data width of 16 bits, the master end needs to read data from the slave end, and the read address transmission signal sent by the master end specifies that the read address is 0, the bit width is 8 bits, and the read length is 8 (D0, D1, D2, D3, D4, D5, D6, D7).

[0074] The method of using the first preset read and send mode specifically includes: first matching the data bit width and data transmission length sent from the master end to the specifications required by the slave end, the data bit width of the slave end becomes a 16-bit specification, and the length becomes 4; first obtaining the first slave end data D00{D1, D0} and shifting it, and after obtaining the first complete data D0 to be read from the master end, the data D0 is sent to the master end, and then the slave end data continues to shift to obtain the next data D1 to be read and continues to send it to the master end; then obtaining the next slave end data D01, and obtaining the data D2 and D3 required by the master end by shifting; and then continuing to read the slave end data until the slave end data D7 to be sent is sent.

[0075] The method of adopting the second preset read and send mode specifically includes: for the first data D00 read from the slave end, re-mapping it to the first data D0 of the master end data according to the address, taking the lower 8 bits of D00 and sending it to the master end; then the second data D1 of the master end maps the upper 8 bits of the second data D01 from the slave end; then the third data D2 of the master end maps the lower 8 bits of the third data D02 from the slave end; then the fourth data D3 of the master end maps the upper 8 bits of the fourth data D03 from the slave end; and so on until the last master end data D7 maps the upper 8 bits of the eighth data D07 from the slave end and the reading is completed.

[0076] It should be noted that, in addition to the AXI bus, the bus system used in the present invention may also be an Advanced High-performance Bus (AHB), a high-performance, high-throughput bus architecture, or a custom bus that requires data bit width conversion.

[0077] Similar to the principle of the above-mentioned embodiment, the present invention provides an AXI bus low-width to high-width low-delay conversion device, which is arranged between the low-width data end and the high-width data end; the device is used to receive a data transmission command sent from the low-width data end to the high-width data end; send data that has undergone bit width conversion from the received data to be sent through the AXI bus according to a preset sending mode; and when a data channel response signal is received, end the operation of the current data transmission command.

[0078] Since the implementation principle of the AXI bus low-bit-width to high-bit-width low-delay conversion device has been described in the aforementioned embodiment, it will not be repeated here.

[0079] The method for converting the low bit width of the AXI bus to the high bit width and low latency provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the electronic terminal, please refer to Figure 4 , is an optional hardware structure diagram of an AXI bus low-width to high-width low-latency conversion terminal 1000 provided in an embodiment of the present invention. The terminal 1000 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010 and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It can be understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1005 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 4 In the specification, various buses are labeled as bus systems.

[0080] The user interface 1009 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0081] It is understood that the memory 1002 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0082] The memory 1002 in the embodiment of the present invention is used to store various categories of data to support the operation of the terminal 1000. Examples of these data include: any executable program for operating on the terminal 1000, such as an operating system 10021 and an application 10022; the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 10022 may include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The method for converting the low-bit width to high-bit width low-latency of the AXI bus provided in the embodiment of the present invention may be included in the application 10022.

[0083] The method disclosed in the above embodiment of the present invention can be applied to the processor 1001, or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 1001 or the instruction in the form of software. The above processor 1001 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The processor 1001 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0084] In an exemplary embodiment, the terminal 1000 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0085] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0086] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0087] like Figure 5 A structural schematic diagram of a data transmission system based on low-bit-width to high-bit-width and low-delay conversion of an AXI bus in an embodiment of the present invention is shown.

[0088] The data transmission system includes: a low-width data terminal 1, a high-width data terminal 2, and an AXI bus low-width to high-width low-delay conversion device 3; the AXI bus low-width to high-width low-delay conversion device 3 is arranged between the low-width data terminal 1 and the high-width data terminal 2. The AXI bus low-width to high-width low-delay conversion device 3 can implement the AXI bus low-width to high-width low-delay conversion method in the above embodiment;

[0089] The AXI bus low-width to high-width low-latency conversion device 3 receives the data transmission command sent by the low-width data terminal 1; receives the data to be sent and sends the data to be sent through the AXI bus after the bit width conversion according to the preset sending mode; when the data channel response signal is received, the operation of the current data transmission command is terminated.

[0090] It should be noted that if the AXI bus low-width to high-width low-delay conversion device 3 is set in the AXI bus system, it is equivalent to being directly connected between the low-width data terminal 1 and the high-width data terminal 2. Figure 5 For example, Figure 6The low-width data end 1 is usually the master end, and the high-width data end 2 is usually the slave end. The width conversion module is located between the master end and the slave end, and communicates with the slave end and the master end through the master port M and the slave port S respectively.

[0091] If the AXI bus low-width to high-width low-delay conversion device 3 is independently set up with the AXI bus system, the AXI bus low-width to high-width low-delay conversion device 3 is connected between the low-width data terminal 1 and the AXI bus system 4, and the AXI bus system is connected to the high-width data terminal 2, such as Figure 7 shown.

[0092] In summary, the AXI bus low-bit width to high-bit width low-delay conversion method, device, terminal and data transmission system of the present invention receive an AXI transmission command sent from a low-bit width data end to a high-bit width data end, send the data to be sent through the AXI bus according to a preset transmission mode after bit width conversion, and when the data channel response signal is received, end the operation of the current command. The present invention reduces the delay of data reading and writing in bit width conversion, and can further improve the efficiency of the AXI bus. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for converting low bit width of an AXI bus to high bit width with low latency, characterized in that: The method comprises: Receiving a data transmission command sent from a low-bit-width data terminal to a high-bit-width data terminal; Sending data converted from the received data to be sent through the AXI bus according to a preset sending mode; When the data channel response signal is received, the operation of the current data transmission command is terminated.

2. The method for converting a low bit width of an AXI bus to a high bit width with low latency according to claim 1, characterized in that: The data transmission command corresponds to a transmission type, which includes: a data address, a data bit width size, and a data transmission length.

3. The method for converting an AXI bus from low bit width to high bit width with low latency according to claim 1, characterized in that: The method comprises: Receive a write address transmission signal transmitted by the low-width data end through the write address channel, use a preset write send mode to send the low-width data transmitted by the low-width data end through the write data channel to the high-width data end through the AXI bus after the bit width conversion of the high-width data, and when receiving a write response channel signal fed back by the high-width data end through the write response channel after the data writing is completed, end the current write data transmission operation.

4. The method for converting an AXI bus from low bit width to high bit width with low latency according to claim 1, characterized in that: The preset write-send mode includes: The first preset write transmission mode includes: Based on the data bit width size and data transmission length in the write address transmission signal, matching the data bit width size for the high bit width data end is performed, and the data transmission length is adjusted accordingly; Whenever the received low-bit-width data reaches the data bit width size of the high-bit-width data terminal through shift register, the data is sent to the high-bit-width data terminal until all the data is sent; The second preset write transmission mode includes: The low-width data received in sequence are mapped to the high-width data bits adapted to the high-width data end according to the write address in the write address transmission signal, and at the same time, the valid low-width data in the current high-width data is identified by the valid byte signal and sent to the high-width data end until all the data are sent.

5. The method for converting a low bit width of an AXI bus to a high bit width with low latency according to claim 1, characterized in that: The method comprises: Receive a read address transmission signal transmitted by the low-width data end through the read address channel, use a preset read transmission mode to send low-width data converted from high-width data transmitted by the high-width data end through the read data channel to the low-width data end through the AXI bus, and when receiving a read response channel signal fed back by the high-width data end through the read data response channel after data reading is completed, end the current read data transmission operation.

6. The method for converting a low bit width of an AXI bus to a high bit width with low latency according to claim 1, characterized in that: The preset read and send mode includes: The first preset read and send mode includes: Based on the data bit width size and data transmission length in the read address transmission signal, matching the data bit width size for the high bit width data end is performed, and the data transmission length is adjusted accordingly; The sequentially received high-bit-width data are shifted and converted into low-bit-width data according to the data bit-width size in the read address transmission command, and sent to the low-bit-width data end in sequence until all the data are sent; The second preset read and send mode includes: According to the read address in the read channel transmission signal, the corresponding low-bit-width data is intercepted from the received high-bit-width data, and is sent to the low-bit-width data end in sequence until all the data is sent.

7. The method for converting an AXI bus from low bit width to high bit width with low latency according to claim 1, characterized in that: The high-bitwidth data received in the second preset read transmission mode is obtained by mapping each read data required by the low-bitwidth data end to the adapted high-bitwidth data bit according to the read address by the high-bitwidth data end.

8. An AXI bus low-width to high-width low-delay conversion device, characterized in that: The device is arranged between the low-bit-width data terminal and the high-bit-width data terminal, and is used to execute the AXI bus low-bit-width to high-bit-width low-delay conversion method according to any one of claims 1 to 7.

9. An electronic terminal, characterized in that: include: one or more memories and one or more processors; The one or more memories are used to store computer programs; The one or more processors, connected to the memory, are configured to run the computer program to perform the method according to any one of claims 1 to 7.

10. A data transmission system based on AXI bus low bit width to high bit width low delay conversion, characterized in that: The system includes: a low-width data terminal, a high-width data terminal, and the AXI bus low-width to high-width low-delay conversion device as described in claim 8; wherein the AXI bus low-width to high-width low-delay conversion device is arranged between the low-width data terminal and the high-width data terminal.

Images