Method for implementing real-time simulation on FPGA using fixed-point arithmetic

Abstract

The application discloses a method for implementing real-time simulation on an FPGA using fixed-point operation, which comprises the following steps: performing normalization processing on differential equations of a simulated system to obtain normalized differential equations; performing discretization processing on the normalized differential equations to obtain normalized difference equations; converting the normalized difference equations into corresponding hardware descriptions based on fixed-point operation; and deploying the hardware descriptions on the FPGA after synthesis to run. In this way, the simulated system with different numerical scales can be converted to a unified numerical scale through normalization, and then simulation calculation can be implemented on the FPGA based on fixed-point operation, so that the cost of real-time simulation is greatly reduced, and the simulation frequency and simulation accuracy are improved.

Description

Technical Field

[0001] This application relates to the field of real-time simulation technology, and in particular to a method for implementing real-time simulation on an FPGA using fixed-point arithmetic. Background Technology

[0002] In modern real-time simulation systems, FPGAs, as a flexible and programmable hardware platform, are widely used in fields requiring high-performance, low-latency processing, especially in applications demanding high-speed real-time simulation. FPGAs can provide step sizes of less than 1 microsecond, making high-speed real-time simulation possible.

[0003] Real-time simulation systems typically require numerical solutions to differential equations to simulate the dynamic behavior of the system. However, traditionally, to maintain versatility across simulations at different numerical scales, existing solutions often use floating-point arithmetic for numerical solutions. But implementing floating-point arithmetic on an FPGA consumes a lot of hardware resources, significantly increasing system costs and slowing down computation speed, thus limiting the system's performance and cost-effectiveness.

[0004] Fixed-point arithmetic is a more efficient method for numerical representation and computation. By representing values ​​with integers of fixed bit width, it can save hardware resources and increase computation speed. Therefore, using fixed-point arithmetic for numerical solutions can significantly save hardware resources and accelerate computation. However, the range of values ​​represented by fixed-point numbers is limited, making it difficult to adapt to simulation requirements at different numerical scales.

[0005] Therefore, an optimized scheme for implementing real-time simulation on FPGA using fixed-point arithmetic is desired.

[0006] Application content

[0007] This application's summary section is provided to briefly introduce the concepts, which will be described in detail in the subsequent detailed description section. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] This application also provides a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, which includes:

[0009] The differential equations of the simulated system are normalized to obtain normalized differential equations;

[0010] The standardized differential equation is discretized to obtain a standardized difference equation;

[0011] The standardized difference equations are transformed into corresponding hardware descriptions based on fixed-point arithmetic; and

[0012] The hardware description is then synthesized and deployed on an FPGA.

[0013] In the above method for implementing real-time simulation on an FPGA using fixed-point arithmetic, the differential equation of the simulated system is normalized to obtain a normalized differential equation, including: selecting base values ​​for the variables and constants in the differential equation; dividing the variables and constants by the corresponding base values ​​to obtain the corresponding normalized values; and replacing the variables and constants in the differential equation with the corresponding normalized values ​​to obtain the normalized differential equation.

[0014] In the above method for implementing real-time simulation on FPGA using fixed-point arithmetic, the discretization process is any one of Euler method, trapezoidal method, explicit and implicit Runge-Kutta method, and Bausch algorithm.

[0015] In the above method for implementing real-time simulation on an FPGA using fixed-point arithmetic, the transformation of the per-unit difference equation into a corresponding hardware description based on fixed-point arithmetic includes: uploading the per-unit difference equation to a cloud server; on the cloud server, performing variable-granularity-based equation description segmentation on the per-unit difference equation to obtain a sequence of equation variables; passing the sequence of equation variables through a variable embedding encoder to obtain a sequence of equation variable embedding encoding vectors; performing semantic encoding on the sequence of equation variable embedding encoding vectors to obtain equation semantic encoding features; generating the hardware description based on the equation semantic encoding features, and returning the hardware description to the FPGA.

[0016] In the above method for implementing real-time simulation on an FPGA using fixed-point arithmetic, semantic encoding of the sequence of equation variable embedding encoding vectors to obtain equation semantic encoding features includes: passing the sequence of equation variable embedding encoding vectors through a semantic encoder based on a converter structure to obtain equation semantic encoding feature vectors as the equation semantic encoding features.

[0017] In the above-described method for implementing real-time simulation on an FPGA using fixed-point arithmetic, the method is characterized in that the sequence of equation variable embedded encoding vectors is passed through a semantic encoder based on a converter structure to obtain an equation semantic encoding feature vector as the equation semantic encoding feature, which includes: passing the sequence of equation variable embedded encoding vectors through the semantic encoder based on the converter structure to obtain multiple equation variable feature vectors; and concatenating the multiple equation variable feature vectors to obtain the equation semantic encoding feature vector.

[0018] In the above method for implementing real-time simulation on an FPGA using fixed-point arithmetic, generating the hardware description based on the equation semantic encoding features and returning the hardware description to the FPGA includes: passing the equation semantic encoding feature vector through a hardware description generator based on an adversarial generative network to obtain the hardware description; and returning the hardware description to the FPGA.

[0019] In the above method for implementing real-time simulation on an FPGA using fixed-point arithmetic, obtaining the hardware description by passing the equation semantic encoding feature vector through a hardware description generator based on an adversarial generative network includes: optimizing the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector; and passing the optimized equation semantic encoding feature vector through the hardware description generator based on the adversarial generative network to obtain the hardware description.

[0020] This application provides a method for implementing real-time simulation on an FPGA using fixed-point arithmetic. The method involves standardizing the differential equations of the simulated system to obtain standardized differential equations; discretizing the standardized differential equations to obtain standardized difference equations; converting the standardized difference equations into corresponding hardware descriptions based on fixed-point arithmetic; and finally, synthesizing the hardware descriptions and deploying them on the FPGA. This method enables the simulation of systems with different numerical scales to be converted to a unified numerical scale through standardization, thereby allowing simulation calculations to be performed on the FPGA based on fixed-point arithmetic. This significantly reduces the cost of real-time simulation and improves simulation frequency and accuracy. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0022] Figure 1 This is a flowchart of a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in one embodiment of this application.

[0023] Figure 2 This is a flowchart of a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in another embodiment of this application.

[0024] Figure 3 This is a flowchart of a sub-step of step 130 in a method for implementing real-time simulation on an FPGA using fixed-point arithmetic provided in another embodiment of this application.

[0025] Figure 4 This is a block diagram of a system for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in another embodiment of this application.

[0026] Figure 5 This is a block diagram illustrating an electronic device for an exemplary embodiment of this application.

[0027] Figure 6 This is an application scenario diagram of a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in another embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of this application are used to explain this application, but are not intended to limit this application.

[0029] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0030] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0031] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0032] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0033] It is understandable that in real-time simulation systems, high-speed (step size less than 1µs) real-time simulation is typically implemented on Field Programmable Gate Arrays (FPGAs). To maintain versatility for simulations at different numerical scales, existing solutions usually use floating-point arithmetic for numerical solutions. However, implementing floating-point arithmetic on an FPGA consumes a large amount of hardware resources, significantly increasing system costs and slowing down computation speed. On the other hand, using fixed-point arithmetic for numerical solutions can greatly save hardware resources and speed up computation. However, the range of numerical values ​​that can be represented using fixed-point arithmetic is limited, making it difficult to adapt to simulation requirements at different numerical scales.

[0034] To address the aforementioned issues, this application provides a method for implementing real-time simulation on an FPGA using fixed-point arithmetic. The method involves standardizing the differential equations of the simulated system to obtain standardized differential equations; discretizing the standardized differential equations to obtain standardized difference equations; converting the standardized difference equations into corresponding hardware descriptions based on fixed-point arithmetic; and finally, synthesizing the hardware descriptions and deploying them on the FPGA. This method enables the simulation of systems with different numerical scales to be converted to a unified numerical scale through standardization, thereby allowing simulation calculations to be performed on the FPGA based on fixed-point arithmetic. This significantly reduces the cost of real-time simulation and improves simulation frequency and accuracy.

[0035] In one embodiment of this application, a method for implementing real-time simulation on an FPGA using fixed-point arithmetic is provided, comprising: standardizing the differential equations of the system to be simulated; discretizing the standardized differential equations to form standardized difference equations; converting the standardized difference equations into corresponding hardware descriptions based on fixed-point arithmetic; and deploying the hardware descriptions on the FPGA for operation.

[0036] according to Figure 1 As shown, in the design phase (a), the differential equations of the simulated system are first established. In the synchronously rotating dq coordinate system, the differential equations of the salient-pole permanent magnet synchronous motor are:

[0037]

[0038] Among them, i d and i q Let μ be the stator current in the dq coordinate system. d and μ q Let ω be the stator voltage in the dq coordinate system, and ω be the rotor electromagnetic angular velocity. Let t be the permanent magnet flux linkage, R and L be the stator resistance and stator inductance, respectively, and t be time.

[0039] Then, the differential equation is normalized to a per-unit. The normalization of the differential equation can be achieved by the following steps: selecting basic values ​​for the quantities (including variables and constants) in the differential equation, dividing the quantities by the corresponding basic values ​​to obtain the corresponding per-unit values, and writing the normalized differential equation in the form of per-unit values.

[0040] Specifically, select the base value as defined in Table 1, divide the quantity by the corresponding base value to obtain the per-unit value, where the base value is represented by the subscript base and the per-unit value is represented by the subscript pu.

[0041] Table 1: Base values ​​and per-unit values ​​of variables and parameters in the differential equations of salient-pole permanent magnet synchronous motors

[0042]

[0043]

[0044] Based on the per-unit values ​​defined in the table above, write the per-unitized differential equation to complete the per-unitization of the differential equation:

[0045]

[0046] Then, the per-unit differential equation is discretized to form a per-unit difference equation. The discretization can be performed using numerical computation methods including Euler's method, trapezoidal method, explicit and implicit Runge-Kutta methods, and Bausymmetric algorithms.

[0047] In one specific embodiment of this application, the forward Euler method is used, and h is selected. pu Discretize (2) by setting the step size to obtain the per-unit difference equation:

[0048]

[0049] in,

[0050]

[0051] Then, based on fixed-point arithmetic, the standardized difference equations are transformed into corresponding hardware descriptions, which can be implemented through different hardware description languages ​​and high-level languages, including but not limited to VHDL, Verilog, and High-Level Synthesis (HLS).

[0052] In a specific embodiment of this application, the quantities in (3) are represented by fixed-point numbers, and the operations between the quantities in (3) are represented by fixed-point arithmetic operations. The quantities and operations are described using a hardware description language.

[0053] Finally, the hardware description is synthesized and deployed on the FPGA to complete the (a) design phase.

[0054] In the (b) operational phase, u d and u q For the input signal, ω, R and L are parameters, i d and i q This is the output signal. (The last part, "u", appears to be a typo and can be left as is.) d u q ,ω, R and L are divided by the corresponding base values ​​in Table 1 to achieve per-unit scaling. After obtaining the corresponding per-unit values, they are input into the FPGA to complete the calculation corresponding to (3) using fixed-point arithmetic, and the per-unit value i of the output signal is obtained. dpu and i qpu . will i dpu i dpu and i qpu Multiplying by the corresponding base value in Table 1 achieves de-perimetric reduction, yielding the output signal i. d and i q When deployed on an FPGA, the input signals and parameters are normalized before being fed into the FPGA for computation, and the computation results are denormalized before generating the output signal.

[0055] In one specific embodiment of this application, the standardization of the input signals and parameters can be achieved by dividing the input signals and parameters by the corresponding base value, and the destandardization of the output signal can be achieved by multiplying by the corresponding base value. In another specific embodiment of this application, the standardization of the input signals and parameters can also be achieved by multiplying the input signals and parameters by the reciprocal of the corresponding base value. In yet another embodiment of this application, the standardization of the input signals and parameters, and the destandardization of the output signal, can be implemented on an FPGA, or on other computing units outside the FPGA (such as a CPU).

[0056] It should be understood that the above-described method of using fixed-point arithmetic to implement real-time simulation on FPGA can be applied in electronic systems, electrical systems, mechanical systems, hydraulic systems, pneumatic systems, and control systems.

[0057] The scheme disclosed in this application transforms the simulated system with different numerical scales to a unified numerical scale through per-unit scaling, and then implements simulation calculations on an FPGA based on fixed-point arithmetic. Compared with traditional floating-point arithmetic schemes, this scheme can significantly reduce the cost of real-time simulation and improve simulation frequency and accuracy.

[0058] Furthermore, in another embodiment of this application, a method for implementing real-time simulation on an FPGA using fixed-point arithmetic is provided. Figure 2 This is a flowchart illustrating a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, as provided in another embodiment of this application. Figure 2As shown in the embodiments of this application, a method for implementing real-time simulation on an FPGA using fixed-point arithmetic includes: 110, standardizing the differential equations of the simulated system to obtain standardized differential equations; 120, discretizing the standardized differential equations to obtain standardized difference equations; 130, converting the standardized difference equations into corresponding hardware descriptions based on fixed-point arithmetic; and 140, synthesizing the hardware descriptions and deploying them on the FPGA for operation. The discretization process can be any one of the following: Euler method, trapezoidal method, explicit and implicit Runge-Kutta method, and Bausch's algorithm.

[0059] This real-time simulation method can transform the simulated system with different numerical scales to a unified numerical scale through per-unit scaling, and then realize simulation calculations on FPGA based on fixed-point arithmetic. Compared with traditional computing schemes, this scheme can significantly reduce the cost of real-time simulation and improve the simulation frequency and accuracy.

[0060] As can be understood, an FPGA is a programmable logic device. By converting an algorithm or logic function description into a hardware description, specific functions can be implemented on the FPGA. Therefore, it is necessary to convert the per-unit difference equations into a hardware description to implement the simulation algorithm as a hardware circuit, thereby enabling real-time simulation on the FPGA. However, implementing floating-point operations on an FPGA requires a large amount of hardware resources, including multipliers and adders, while fixed-point operations can be implemented through simple shift and addition operations, greatly saving hardware resources. Based on this, converting the per-unit difference equations into corresponding hardware descriptions based on fixed-point operations is crucial. This can improve the system's hardware resource utilization, computation speed, achieve high-speed real-time simulation, and reduce system costs.

[0061] Figure 3 This is a flowchart of a sub-step in step 130 of a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in another embodiment of this application. (See flowchart for example.) Figure 3 As shown in Figure 130, the transformation of the per-unit difference equation into a corresponding hardware description based on fixed-point arithmetic includes: 131, uploading the per-unit difference equation to a cloud server; 132, on the cloud server, performing variable-granularity-based equation description segmentation on the per-unit difference equation to obtain a sequence of equation variables; 133, passing the sequence of equation variables through a variable embedding encoder to obtain a sequence of equation variable embedding encoding vectors; 134, performing semantic encoding on the sequence of equation variable embedding encoding vectors to obtain equation semantic encoding features; 135, generating the hardware description based on the equation semantic encoding features, and returning the hardware description to the FPGA.

[0062] Specifically, in the technical solution of this application, in the process of converting the per-unit difference equation into a corresponding hardware description, firstly, the per-unit difference equation is uploaded to a cloud server. Next, considering that there are many variables in the per-unit difference equation, and the different granularities and correlations of these variables determine the implementation and operation of the hardware, in order to convert the equation into a hardware description and thus implement hardware functions on the FPGA, in the technical solution of this application, the per-unit difference equation needs to be segmented on the cloud server based on variable granularity to obtain a sequence of equation variables. It should be understood that the equation segmentation method can decompose the per-unit difference equation into multiple variables to achieve parallel processing of different variables in the equation, while capturing the semantic relationships between variables. This allows for the generation of a more accurate hardware description based on the semantic relationships between equation variables, improving computational efficiency and accelerating processing speed.

[0063] Then, considering the interrelationships among the equation variables in the sequence, in order to extract important features and correlations between variables, the technical solution of this application uses a variable embedding encoder to obtain a sequence of equation variable embedding encoding vectors. It should be understood that the variable embedding encoder can learn the nonlinear relationships and complex patterns between equation variables and map different variable embeddings into a common space, thereby better extracting valuable feature information and improving the accuracy and robustness of subsequent hardware description generation and simulation. Simultaneously, the variable embedding encoder can provide interpretability of the variable relationships in the embedding space. By analyzing the equation variable embedding encoding vectors, the similarities and differences between different variables can be understood, which helps in the analysis and interpretation of simulation results.

[0064] Furthermore, since there are semantic association features based on the equations among the embedded encoding features of different equation variables after embedding encoding, in order to extract the semantic information and logical relationships implied between different variables in the equations and further improve the accuracy and interpretability of hardware description generation and simulation, in the technical solution of this application, the sequence of the embedded encoding vectors of the equation variables is passed through a semantic encoder based on a converter structure to obtain the equation semantic encoding feature vector. It should be understood that the converter structure has a powerful long-range dependency modeling capability, which can capture the dependencies between different equation variables across long distances. Through long-range dependency modeling, the overall structure and meaning of the equations can be better understood. Moreover, the attention mechanism in the converter structure can automatically learn the importance between equation variables and focus on the variables most relevant to the current task, thereby improving the efficiency and accuracy of semantic encoding.

[0065] In one specific embodiment of this application, semantic encoding of the sequence of equation variable embedding encoding vectors to obtain equation semantic encoding features includes: passing the sequence of equation variable embedding encoding vectors through a semantic encoder based on a converter structure to obtain equation semantic encoding feature vectors as the equation semantic encoding features.

[0066] Further, passing the sequence of equation variable embedded encoding vectors through a semantic encoder based on a converter structure to obtain equation semantic encoding feature vectors as the equation semantic encoding features includes: passing the sequence of equation variable embedded encoding vectors through the semantic encoder based on a converter structure to obtain multiple equation variable feature vectors; and concatenating the multiple equation variable feature vectors to obtain the equation semantic encoding feature vectors.

[0067] Subsequently, the semantically encoded feature vector of the equation is passed through a hardware description generator based on an adversarial generative network to obtain the hardware description. In other words, the hardware description generator based on the adversarial generative network can efficiently generate hardware descriptions that meet specific performance and resource constraints based on the long-range semantic association features of the per-unit difference equation, and return the hardware descriptions to the FPGA. This enables the efficient generation of customized hardware on the FPGA based on fixed-point computation, while shortening development time and improving simulation quality.

[0068] In one specific embodiment of this application, generating the hardware description based on the equation semantic encoding features and returning the hardware description to the FPGA includes: passing the equation semantic encoding feature vector through a hardware description generator based on an adversarial generative network to obtain the hardware description; and returning the hardware description to the FPGA.

[0069] Further, the hardware description is obtained by passing the equation semantic encoding feature vector through a hardware description generator based on an adversarial generative network, including: optimizing the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector; and passing the optimized equation semantic encoding feature vector through the hardware description generator based on the adversarial generative network to obtain the hardware description.

[0070] In the above technical solution, the sequence of equation variable embedding encoding vectors expresses the embedded semantic encoding representation of the equation variables. Thus, after passing the sequence of equation variable embedding encoding vectors through a semantic encoder based on a converter structure, context association can be further performed based on the embedding encoding representation context between variables, thereby obtaining an equation semantic encoding feature vector used to express the global semantics of the per-unit difference equation. However, considering the differences in the variable-granularity encoded semantic representations of each equation variable, although context association improves the distribution correlation between local semantic distributions, explicit distribution differences still exist between local semantic distributions. This leads to the discreteness of the local feature distribution of the equation semantic encoding feature vector obtained by aggregating the global semantic association representation corresponding to the sequence of equation variable embedding encoding vectors. Consequently, the convergence and iteration consistency of the equation semantic encoding feature vector through the hardware description generator based on adversarial generative networks to the probability mapping in the text semantic space domain of the hardware description is poor, reducing the quality of the generated results.

[0071] Based on this, this application optimizes the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector, including: a first eigenvalue v for the equation semantic encoding feature vector. i Second eigenvalue v j The relative probability value is obtained by calculating the absolute value of the difference and dividing it by the sum of absolute values, where the correction makes the relative probability value greater than zero and less than one. A first product is calculated of the first feature value multiplied by the relative probability value, and a second product is calculated of the second feature value multiplied by the absolute value of the difference between the relative probability value and one. A first quotient of the first feature value divided by the absolute value of the difference between the relative probability value and one and a second quotient of the second feature value divided by the relative probability value are also calculated. The first product and the second product are added together, and the difference between the first quotient and the second quotient is further subtracted to obtain the result relative to the first feature value v. i Second eigenvalue v j The corresponding eigenvalues ​​m of the optimization matrix i,j ; and, multiply the optimization matrix by the equation semantic encoding feature vector to obtain the optimized equation semantic encoding feature vector.

[0072] Specifically, it is expressed as:

[0073]

[0074] m i,j ∈M,v i ∈V,v j(j≠i) ∈V

[0075]

[0076] Where V represents the semantic encoding feature vector of the equation, v i and v j p represents the first and second eigenvalues ​​of the semantic encoding feature vector of the equation, respectively. i,j m represents the relative probability value. i,j Indicates the relationship with the first eigenvalue v i Second eigenvalue v j The corresponding eigenvalues ​​of the optimization matrix, M represents the first eigenvalue v. i Second eigenvalue v j The corresponding optimization matrix, V' represents matrix multiplication, and V′ represents the semantic encoding feature vector of the optimized equation.

[0077] Wherein, the first eigenvalue v i Second eigenvalue v j The corresponding relative probability value p i,j Represented as:

[0078]

[0079] Among them, v i and v j Let p represent the first and second eigenvalues ​​of the semantically encoded feature vector of the equation, respectively, where ε represents a predetermined hyperparameter. i,j This represents a relative probability value.

[0080] Here, regarding the region-boundary integral relationship of the high-dimensional feature manifold of the semantically encoded feature vector of the equation, the probability distribution of the entire feature set of the semantically encoded feature vector of the equation is defined as the manifold constraint boundary. This approximates the simply connected region representation of the high-dimensional manifold of the feature set of the semantically encoded feature vector of the equation, composed of eigenvalue pairs. This avoids ambiguity in mapping the diverse feature representations of the semantically encoded feature vector of the equation to the local manifold representations in the high-dimensional feature generative regression convergence space, improves the consistency of execution iteration of each local feature distribution in the mapping task, improves the convergence effect of feature generative regression, and enhances the text quality of the obtained hardware description. In this way, the simulated system with different numerical scales can be transformed to a unified numerical scale through permutation, and then simulation calculations can be implemented on FPGA based on fixed-point arithmetic. In this way, customized hardware can be generated efficiently, while shortening development time and improving simulation quality.

[0081] In summary, the method for implementing real-time simulation on an FPGA using fixed-point arithmetic based on the embodiments of this application has been clarified. It transforms the standardized difference equation into a corresponding hardware description based on fixed-point arithmetic, which can improve the hardware resource utilization and computing speed of the system, realize high-speed real-time simulation, and reduce the cost of the system.

[0082] In one embodiment of this application, Figure 4 This is a block diagram of a system for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in another embodiment of this application. Figure 4 As shown, a system 200 for real-time simulation on an FPGA using fixed-point arithmetic according to an embodiment of this application includes: a per-unit processing module 210, used to perform per-unit processing on the differential equations of the simulated system to obtain per-unit differential equations; a discretization processing module 220, used to discretize the per-unit differential equations to obtain per-unit difference equations; a fixed-point arithmetic module 230, used to convert the per-unit difference equations into corresponding hardware descriptions based on fixed-point arithmetic; and an FPGA running module 240, used to synthesize the hardware descriptions and deploy them on the FPGA for running.

[0083] Here, those skilled in the art will understand that the specific functions and operations of each unit and module in the system for implementing real-time simulation on an FPGA using fixed-point arithmetic have been referenced above. Figures 1 to 3 The method of implementing real-time simulation on FPGA using fixed-point arithmetic has been described in detail, and therefore, its repeated description will be omitted.

[0084] As described above, the system 200 for implementing real-time simulation on an FPGA using fixed-point arithmetic according to embodiments of this application can be implemented in various terminal devices, such as servers for implementing real-time simulation on an FPGA using fixed-point arithmetic. In one example, the system 200 for implementing real-time simulation on an FPGA using fixed-point arithmetic according to embodiments of this application can be integrated into a terminal device as a software module and / or a hardware module. For example, the system 200 for implementing real-time simulation on an FPGA using fixed-point arithmetic can be a software module in the operating system of the terminal device, or it can be an application developed for the terminal device; of course, the system 200 for implementing real-time simulation on an FPGA using fixed-point arithmetic can also be one of many hardware modules of the terminal device.

[0085] Alternatively, in another example, the system 200 that implements real-time simulation on the FPGA using fixed-point arithmetic can also be a separate device from the terminal device, and the system 200 that implements real-time simulation on the FPGA using fixed-point arithmetic can be connected to the terminal device via wired and / or wireless networks and transmit interactive information in accordance with an agreed data format.

[0086] The following is for reference. Figure 5This diagram illustrates a structural schematic of an electronic device 600 suitable for implementing embodiments of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0087] like Figure 5 As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of electronic device 600. Processing device 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0088] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0089] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a storage device 608, or installed from a ROM 602. When the computer program is executed by the processing device 601, it performs the functions defined in the methods of embodiments of this disclosure.

[0090] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0091] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol, such as HTTP (Hypertext Transfer Protocol), and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0092] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0093] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0095] The modules described in the embodiments of this disclosure can be implemented in software or hardware. The name of a module does not necessarily limit the module itself; for example, a test parameter acquisition module can also be described as "a module for acquiring device test parameters corresponding to a target device".

[0096] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0097] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0098] Figure 6 This is an application scenario diagram illustrating a method for implementing real-time simulation on an FPGA using fixed-point arithmetic, provided in another embodiment of this application. For example... Figure 6 As shown, in this application scenario, firstly, the standardized difference equation (e.g., as...) is... Figure 6 As shown in C), the equation is uploaded to a cloud server; then, the obtained standardized difference equation is input to a server deployed with a real-time simulation algorithm implemented on an FPGA using fixed-point arithmetic (e.g., such as...). Figure 6 In the S shown, the server is capable of processing the per-unit difference equation based on a real-time simulation algorithm implemented on the FPGA using fixed-point arithmetic to generate the hardware description and return the hardware description to the FPGA.

[0099] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for implementing real-time simulation on an FPGA using fixed-point arithmetic, characterized in that, The method comprises: normalizing differential equations of a system to be simulated to obtain normalized differential equations; discretizing the normalized differential equations to obtain normalized difference equations; translating the normalized difference equations into corresponding hardware descriptions based on fixed-point operations; and synthesizing the hardware descriptions and deploying them on an FPGA for running. The translation of the normalized difference equations into corresponding hardware descriptions based on fixed-point operations comprises: uploading the normalized difference equations to a cloud server; performing variable-granularity equation description segmentation on the normalized difference equations on the cloud server to obtain a sequence of equation variables; embedding the sequence of equation variables to obtain a sequence of equation variable embedding encoding vectors; performing semantic coding on the sequence of equation variable embedding encoding vectors to obtain equation semantic coding features, which comprises: passing the sequence of equation variable embedding encoding vectors through a semantic encoder based on a transformer structure to obtain an equation semantic coding feature vector as the equation semantic coding features; generating the hardware descriptions based on the equation semantic coding features and returning the hardware descriptions to the FPGA; wherein the optimization of the equation semantic coding feature vector to obtain an optimized equation semantic coding feature vector comprises: calculating a relative probability value by dividing the absolute value of the difference between a first feature value and a second feature value of the equation semantic coding feature vector by the sum of the absolute values and then modifying it, wherein the modification makes the relative probability value greater than zero and less than one; calculating a first product of the first feature value multiplied by the relative probability value, a second product of the second feature value multiplied by the absolute value of the difference between the relative probability value and one, a first quotient of the first feature value divided by the absolute value of the difference between the relative probability value and one, and a second quotient of the second feature value divided by the relative probability value; adding the first product and the second product, and further subtracting the difference between the first quotient and the second quotient to obtain the corresponding feature values of the optimized matrix corresponding to the first feature value and the second feature value; and multiplying the optimized matrix by the equation semantic coding feature vector to obtain the optimized equation semantic coding feature vector. The normalization of the differential equations of the system to be simulated to obtain the normalized differential equations comprises:

2. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 1, characterized in that, selecting base values for variables and constants in the differential equations; dividing the variables and constants by the corresponding base values to obtain corresponding normalized values; and replacing the variables and constants in the differential equations with the corresponding normalized values to obtain the normalized differential equations. The discretization processing is any one of Euler method, trapezoidal method, explicit and implicit Runge-Kutta method, and symplectic algorithm.

3. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 2, characterized in that, The passing of the sequence of equation variable embedding encoding vectors through the semantic encoder based on the transformer structure to obtain the equation semantic coding feature vector as the equation semantic coding features comprises:

4. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 3, characterized in that, passing the sequence of equation variable embedding encoding vectors through the semantic encoder based on the transformer structure to obtain a plurality of equation variable feature vectors; and ​ concatenate the plurality of equation variable feature vectors to obtain the equation semantic encoding feature vector.

5. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 4, characterized in that, generating the hardware description based on the equation semantic encoding feature, and returning the hardware description to the FPGA, comprising: generating the hardware description based on the equation semantic encoding feature vector through a hardware description generator based on a generative adversarial network to obtain the hardware description; returning the hardware description to the FPGA.

6. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 5, characterized in that, generating the hardware description based on the equation semantic encoding feature vector through a hardware description generator based on a generative adversarial network, comprising: optimizing the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector; generating the hardware description based on the optimized equation semantic encoding feature vector through the hardware description generator based on the generative adversarial network.

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