Memristor array circuit simulation method and device, computer equipment and storage medium

Abstract

The invention relates to a memristor array circuit simulation method and device, computer equipment and a storage medium. The method comprises the following steps: decomposing a single network layer input of a convolutional neural network based on a memristor array circuit into a plurality of binary input vectors, and allocating a simulation task; the simulation task is executed in parallel based on a distributed mode and multiple processes, weight bits are mapped to multiple device conductance of the memristor array in the simulation task, input bits are mapped into multiple voltage signals, and a circuit netlist of each memristor array circuit is written; analyzing the circuit netlist, operating simulation, and calculating an output current based on the Kirchhoff's law according to the voltage value and the device conductivity value; the current output by each memristor array circuit simulation task is converted into a digital signal, shifting, adding and combining are carried out to obtain an integer number, then the integer number is inversely quantized into a floating-point number, a bias item is added, and after quantization is carried out again, network layer output is obtained.

Description

Technical Field

[0001] The present application relates to the technical field of code snippet adaptation, and in particular to a memristor array circuit simulation method, apparatus, computer equipment and storage medium. Background Art

[0002] Memristor is a nonlinear resistor with memory function, whose resistance value can change with the amount of charge flowing through it and maintain this changed state after power is off. Memristor cross array, referred to as memristor array, is a memristor unit integration process, in which the memristor unit is located at the intersection of mutually perpendicular word lines and bit lines. The so-called 1T1R (one-transistor-one-resistor) refers to a structure in which a transistor is connected in series with a memristor or a resistive switching unit. Transistors are used to enable the memristor unit to avoid crosstalk caused by leakage current problems. In the traditional 1T1R array, the wire connecting the gates of transistors in the same row is the word line, and the wire connecting the memristor units in the same column is the bit line. To perform multiplication and accumulation operations based on the traditional 1T1R array, an input signal needs to be applied to the word line to control the switching state of the transistor, and a fixed read voltage needs to be applied to the bit line. This method is suitable for binary signals. The bit lines in the traditional 1T1R array are rotated to be perpendicular to the source lines to obtain a pseudo cross array structure. The word lines of this architecture connect the memristor units in the same row, and the bit lines connect the transistor gates in the same column. There are two ways to apply input signals to perform multiplication and accumulation operations based on the pseudo cross array, corresponding to two structures: Bitline-signal 1T1R and Gate-signal 1T1R. Bitline-signal 1T1R applies input signals to the word lines and applies transistor turn-on voltages to each bit line to turn on all transistors; Gate-signal 1T1R applies a fixed read voltage to each word line and applies input signals to the bit line to control the switching state of the transistor. It is similar to the traditional 1T1R array and is suitable for binary signals. 1R is a cross array structure without transistors. The cross unit in the 2T2R (two-transistor-two-resistor) array structure consists of two transistors and two memristors.

[0003] The main calculation of Convolutional Neural Network (CNN) is Matrix Vector Multiplication (MVM), and the basic operation of MVM is Multiply Accumulate (MAC) operation. The multiply-accumulate method based on memristor array is that, assuming that the convolution kernel weight is mapped to the memristor conductance by column, the voltage pulse is applied by row. According to Kirchhoff's law, the current collected at the end of the column is the result of the multiplication and accumulation of the input (voltage) and the weight (conductance).

[0004] Array parasitic resistance. In actual memristor crossbar arrays, there are wire resistance, input / output resistance, and transistor resistance. These parasitic resistances can cause signal attenuation, thus affecting the results of multiplication and accumulation operations.

[0005] In terms of computing architecture, traditional in-memory computing architecture follows the same paradigm as digital circuits and is not fault-tolerant. In digital circuit design, each number is represented by multiple bits. During multiplication, each bit in the multiplier is multiplied by each bit in the multiplicand to obtain many partial products. Therefore, the multiplier circuit has a set of shifters and adders to add the partial products. Traditional in-memory computing architecture inherits and extends this approach to the array, forming the so-called bit slicing method. In this method, the memristor is restricted to a finite predetermined state space (usually binary), and the weight matrix and input vector are decomposed into multiple bit planes. On these bit planes, MVM is performed to obtain partial products. Subsequently, these partial products are quantized and combined by using digital circuits such as analog-to-digital converters (ADCs), shifters, and adders to produce the complete MVM result.

[0006] Among the open source crossbar array simulators, there are PytorX, MLP+NeuroSim V3.0, and CrossSim. PytorX equates the transistors of the Bitline-signal 1T1R array structure to on-resistance, uses a simplified improved node analysis method to establish circuit equations, and solves linear equations based on GPU. Although this simulator does not call Spice simulation, its principle of establishing circuit equations is the same as Spice. In MLP+NeuroSim V3.0, the transistors in the Bitline-signal 1T1R structure are equivalent to on-resistances, and the simulation method for wire resistance is that it considers a path for voltage transmission, which goes from the input end through the bit line to the target memristor, then passes through the transistor, and finally reaches the output end through the source line, that is, the direct path through the memristor, and the memristor current = read voltage / (wire resistance of the path + transistor on-resistance). In CrossSim, three 1T1R circuit array structures are approximated and analyzed, and based on the approximate array structure, approximate calculation and iterative solution methods are used for simulation. The array parasitic resistance simulation methods of both MLP+NeuroSim and CrossSim simulators are approximate calculations, with low accuracy and low credibility. In addition, it is difficult to add new array structures for both, and the simulation code logic needs to be modified, which has poor scalability. In PytorX, the transistors of the Bitline-signal 1T1R array structure are also equivalent to on-resistance, and the simplified improved node analysis method is used to establish the circuit equation, and the linear equation is solved based on the GPU. Similarly, the simulator has the problem of difficulty in adding new array structures, and for some array structures (such as Gate-signal 1T1R), even small-scale array simulation is very time-consuming. Summary of the invention

[0007] Based on this, it is necessary to provide a memristor array circuit simulation method, device, computer equipment and storage medium to address the above technical problems.

[0008] A memristor array circuit simulation method, the method comprising:

[0009] Decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0010] Based on distributed, multi-process parallel execution of the simulation task, in the simulation task, the weight bits are mapped to multiple device conductances of the memristor array, the input bits are mapped to multiple voltage signals, and a circuit netlist of each memristor array circuit is compiled;

[0011] The circuit netlist is parsed and a simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0012] The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized into a floating point number and a bias term is added. The network layer output is obtained after quantization again.

[0013] In one embodiment, the memristor array circuit includes: traditional 1T1R, Gate-signal 1T1R, Bitline-signal 1T1R, 1R and 2T2R. Only by writing a circuit netlist, circuit simulation of various array structures can be supported. The following method takes traditional 1T1R as an example for explanation.

[0014] In one embodiment, the method further includes: modeling the conduction state of transistors in the memristor array circuit, and modifying the circuit netlist according to the modeled memristor array circuit.

[0015] In one embodiment, it further includes: for each row of word lines, the gates of each transistor in the row are connected, the unit resistance of each section on the word line is R_wl_wire, the word line driving signal source Vgate is a DC voltage source, and the signal enters the array through the input resistor Rload_1;

[0016] For each column of bit lines, the memristors R of the column are connected, the unit resistance of each section on the bit line is R_bl_wire, the bit line driving signal source Vread is a DC voltage source, and the signal enters the array through the input resistor Rload_2;

[0017] The source line of each column connects the sources of the transistors in the column, and the unit resistance of each section of the source line is R_sl_wire. The current passing through each memristor is collected from the source line and flows through the output resistor Rload_3.

[0018] In one of the embodiments, the method further includes: when the input signal is 1, the cross unit Rcell is equivalent to a combination of a memristor and a transistor on-resistance;

[0019] When the input signal is 0, the cross cell Rcell is equivalent to a combination of a memristor and a transistor disconnect resistor;

[0020] Applying a read voltage using the bit line, maintaining the bit line structure;

[0021] Use the source line to sink the current and output the current through the output resistor.

[0022] In one embodiment, it also includes: allocating each input vector to a corresponding memristor array circuit simulation task, performing multi-node distributed computing based on a message passing interface, and using multiple processes in each node to run the Ngspice simulation task in parallel.

[0023] In one of the embodiments, it also includes: in each memristor array, calling Ngspice API through the FFI interface to parse the circuit netlist and perform circuit simulation to obtain the sum of the column currents of each part; using regular expressions to process the Ngspice simulation callback results, extracting the sum of the column currents output by each memristor array circuit simulation task, and quantizing the current into a digital signal.

[0024] A memristor array circuit simulation device, the device comprising:

[0025] The task decomposition module decomposes the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assigns simulation tasks;

[0026] A netlist writing module is used to execute the simulation task in parallel based on distributed and multi-process, map the weight bits to multiple device conductances of the memristor array in the simulation task, map the input bits to multiple voltage signals, and write a circuit netlist for each memristor array circuit;

[0027] A simulation output module, which parses the circuit netlist and runs a simulation, and calculates the output current based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0028] The output processing module is used to convert the current output by each memristor array circuit simulation task into a digital signal, shift, add and combine it to obtain an integer, then dequantize the integer into a floating point number and add a bias term, and quantize it again to obtain the network layer output.

[0029] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0030] Decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0031] Based on distributed, multi-process parallel execution of the simulation task, in the simulation task, the weight bits are mapped to multiple device conductances of the memristor array, the input bits are mapped to multiple voltage signals, and a circuit netlist of each memristor array circuit is compiled;

[0032] The circuit netlist is parsed and a simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0033] The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized into a floating point number and a bias term is added. The network layer output is obtained after quantization again.

[0034] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0035] Decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0036] Based on distributed, multi-process parallel execution of the simulation task, in the simulation task, the weight bits are mapped to multiple device conductances of the memristor array, the input bits are mapped to multiple voltage signals, and a circuit netlist of each memristor array circuit is compiled;

[0037] The circuit netlist is parsed and a simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0038] The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized into a floating point number and a bias term is added. The network layer output is obtained after quantization again.

[0039] The above-mentioned memristor array circuit simulation method, device, computer equipment and storage medium first decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors, assign simulation tasks to each input vector, and improve the simulation efficiency based on distributed, multi-process parallel processing tasks; secondly, in the simulation task, the weight bit is mapped to the multiple device conductances of the memristor array, and the input bit is mapped to multiple voltage signals, and the circuit netlist of each memristor array circuit is compiled. For different memristor array architectures, only the circuit netlist needs to be changed, and there is no need to modify the simulation framework; then the circuit netlist is parsed and the simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage value and the device conductance value; finally, the current output by each memristor array circuit simulation task is converted into a digital signal, shifted, added and combined to obtain an integer, the integer is dequantized into a floating point number and a bias term is added, and the network layer output is obtained after quantization again. The method of the present invention can significantly improve the efficiency of memristor array circuit simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1is a schematic flow chart of a memristor array circuit simulation method in one embodiment;

[0041] Figure 2 A schematic diagram of a simulation framework of a memristor array circuit in one embodiment;

[0042] Figure 3 A schematic diagram of a 1T1R equivalent circuit in which a transistor is added in one embodiment;

[0043] Figure 4 is a schematic diagram of a 1T1R equivalent circuit without adding a transistor in an embodiment;

[0044] Figure 5 is a structural block diagram of a memristor array circuit simulation device in one embodiment;

[0045] Figure 6 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] The simulation program of the present invention can adopt multi-node distributed computing based on MPI communication to divide the test data set equally into each computing node, thereby speeding up the test speed without using a GPU.

[0048] In one embodiment, if Figure 1 As shown, a circuit simulation method based on a memristor array is provided, comprising:

[0049] Step 102, decomposing a single network layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors, and assigning simulation tasks.

[0050] In this step, the main process asynchronously creates multiple processes according to CPU resources to handle simulation tasks of multiple binary input vectors, and each binary input vector corresponds to each task.

[0051] Step 104, based on distributed, multi-process parallel execution of the simulation task, in the simulation task, the weight bits are mapped to multiple device conductances of the memristor array, the input bits are mapped to multiple voltage signals, and a circuit netlist of each memristor array circuit is compiled.

[0052] Step 106, parsing the circuit netlist and running a simulation, calculating the output current based on the voltage signal and the device conductance value and Kirchhoff's law.

[0053] Step 108, convert the current output by each memristor array circuit simulation task into a digital signal, shift, add and combine to obtain an integer, then dequantize the integer into a floating point number and add a bias term, and quantize again to obtain the network layer output.

[0054] The above-mentioned memristor array circuit simulation method first decomposes the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors, assigns simulation tasks to each input vector, and improves the simulation efficiency based on distributed, multi-process parallel processing tasks; secondly, in the simulation task, the weight bit is mapped to the multiple device conductances of the memristor array, and the input bit is mapped to multiple voltage signals, and the circuit netlist of each memristor array circuit is compiled. For different memristor array architectures, only the circuit netlist needs to be changed, and there is no need to modify the simulation framework; then the circuit netlist is parsed and the simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage value and the device conductance value; finally, the current output by each memristor array circuit simulation task is converted into a digital signal, shifted, added and combined to obtain an integer, the integer is dequantized into a floating point number and a bias term is added, and the network layer output is obtained after quantization again. The method of the present invention can significantly improve the efficiency of memristor array circuit simulation.

[0055] The framework of this method is Figure 2 As shown, first, for the calculation of a certain network layer, the main process asynchronously creates multiple processes according to the CPU resources to handle the simulation tasks of multiple input vectors, and determines whether all task processing is completed. If not, for each task, a single array simulation is performed in turn. Whether all arrays are simulated, if not, a circuit netlist is written to determine whether word lines and transistors are added. If so, the BSIMBULK107 transistor model, word line resistance and input signal are added. If not, the approximate resistance of the transistor being turned on or off is added to the unit resistance according to the input signal, and the simulation is defined to only save the current data of the output resistance. The Shared Ngspice API is called based on the FFI interface to run the simulation, and the simulation output data is matched and processed using regular expressions until all array simulations are completed, and the output data of all arrays are combined. The results of all tasks are processed and combined to obtain the current output of the network layer, and the output is converted, dequantized, biased and requantized to obtain the output of a certain network layer, and the calculation of the network layer is completed.

[0056] Specifically, the main process asynchronously creates multiple processes based on CPU resources to handle simulation tasks of multiple binary input vectors. Each input vector corresponds to each task. Each input vector has multiple arrays. In each task, a single array is simulated in turn. First, according to the two structures obtained by adding transistors in the above analysis, Ngspice circuit netlists are written respectively. In the netlist, it is defined that the simulation only saves the current data of the output resistor; then Python is used to call the Shared Ngspice API based on the FFI interface to run the simulation, and the simulated data is matched and processed using regular expressions. At this point, the multiplication and accumulation operation simulation of a single array is completed. Each task completes the operation simulation of all arrays under the input vector and combines the output data of all arrays. The main process blocks to obtain the results of each task, processes and combines to obtain the original output current data of the array operation of the network layer, performs analog-to-digital conversion on the original output current to obtain an integer, dequantizes the integer to a floating point number, adds a bias, and then quantizes to obtain the output of the network layer.

[0057] In one embodiment, the memristor array circuit includes: traditional 1T1R, Gate-signal 1T1R, Bitline-signal 1T1R, 1R and 2T2R. Only by writing a circuit netlist, circuit simulation of various array structures can be supported. The following method takes the traditional 1T1R as an example for explanation.

[0058] In one embodiment, the conduction states of transistors in the memristor array circuit are modeled, and the circuit netlist is modified according to the modeled memristor array circuit.

[0059] Specifically, take the traditional 1T1R as an example. Figure 3 As shown, the word line (WL) of each row connects the gates of each transistor in the row, and the unit resistance of each section on the word line is R_wl_wire. The word line driving signal source Vgate is a DC voltage source, and the signal enters the array through the input resistor Rload_1. The bit line (BL) of each column connects the memristors R of the column, and the unit resistance of each section on the bit line is R_bl_wire. The bit line driving signal source Vread is a DC voltage source, and the signal enters the array through the input resistor Rload_2. The source line (SL) of each column connects the sources of each transistor in the column, and the unit resistance of each section on the source line is R_sl_wire. The current passing through each memristor is collected from the source line and flows through the output resistor Rload_3 to enter the analog-to-digital converter. The analog-to-digital conversion here is processed in the program, so the output resistor Rload_3 is grounded.

[0060] In another embodiment, in order to improve the simulation speed, transistors may not be added, but approximation processing may be performed, as shown in FIG. Figure 4 As shown, when the input signal is 1, the cross unit Rcell is equivalent to a combination of a memristor and a transistor on-resistance; when the input signal is 0, the cross unit Rcell is equivalent to a combination of a memristor and a transistor off-resistance; a read voltage is applied using the bit line to maintain the bit line structure; a source line is used to collect current and output the current through an output resistor.

[0061] Specifically, the program is based on the input data bit. If it is 1 (0), the cross cell Rcell resistance = memristor resistance + transistor on (off) resistance. The same thing as the structure with added transistors is that the bit line applies the read voltage and the source line collects the current. The difference is that this structure does not require the addition of transistors and word lines, and the number of circuit nodes is reduced by two times. In addition, each set of inputs in this structure causes a change in the cross cell resistance, while the structure with added transistors is that the cross cell resistance remains unchanged and the input changes. The method of approximating without adding transistors increases the simulation speed, but it will affect the accuracy of the simulation, but the impact is small.

[0062] In one embodiment, each input vector is assigned to a corresponding memristor array circuit simulation task, multi-node distributed computing is performed based on a message passing interface, and Ngspice simulation tasks are run in parallel using multiple processes in each node.

[0063] In one of the embodiments, in each memristor array, the Ngspice API is called through the FFI interface to parse the circuit netlist and perform circuit simulation to obtain the sum of the currents of each column; the Ngspice simulation callback result is processed using a regular expression to extract the sum of the currents of each column output by each memristor array circuit simulation task, and the current is quantized and converted into a digital signal.

[0064] In one embodiment, Figure 5 As shown, a memristor array circuit simulation device is provided, including: a task decomposition module 502, a netlist writing module 504, a simulation output module 506 and an output processing module 508, wherein:

[0065] A task decomposition module 502 is used to decompose a single network layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks;

[0066] A netlist writing module 504 is used to execute the simulation task in parallel based on a distributed and multi-process manner, map the weight bits to multiple device conductances of the memristor array in the simulation task, map the input bits to multiple voltage signals, and write a circuit netlist for each memristor array circuit;

[0067] A simulation output module 506 parses the circuit netlist and runs a simulation, and calculates the output current based on Kirchhoff's law according to the voltage signal and the device conductance value;

[0068] The output processing module 508 is used to convert the current output by each memristor array circuit simulation task into a digital signal, perform shifting, addition and combination to obtain an integer, then dequantize the integer into a floating point number and add a bias term, and quantize again to obtain the network layer output.

[0069] In one embodiment, the memristor array circuit includes: traditional 1T1R, Gate-signal 1T1R, Bitline-signal 1T1R, 1R and 2T2R. Only by writing a circuit netlist, circuit simulation of various array structures can be supported. The following method takes traditional 1T1R as an example for explanation.

[0070] In one embodiment, the netlist writing module 504 is further used to model the conduction state of transistors in the memristor array circuit, and modify the circuit netlist according to the modeled memristor array circuit.

[0071] In one embodiment, the netlist writing module 504 is also used to connect the gates of each transistor in each row of word lines, the unit resistance of each section on the word line is R_wl_wire, the word line driving signal source Vgate is a DC voltage source, and the signal enters the array through the input resistor Rload_1; connect the memristors R in each column of bit lines, the unit resistance of each section on the bit line is R_bl_wire, the bit line driving signal source Vread is a DC voltage source, and the signal enters the array through the input resistor Rload_2; connect the sources of each transistor in the column of source lines, the unit resistance of each section on the source line is R_sl_wire, and the current passing through each memristor is collected from the source line and flows through the output resistor Rload_3.

[0072] In one of the embodiments, the netlist writing module 504 is also used to, when the input signal is 1, make the cross cell Rcell equivalent to a combination of a memristor and a transistor on-resistance; when the input signal is 0, make the cross cell Rcell equivalent to a combination of a memristor and a transistor off-resistance; use the bit line to apply a read voltage to maintain the bit line structure; use the source line to collect current and output the current through the output resistor.

[0073] In one embodiment, the task decomposition module 502 is further used to assign each input vector to a corresponding memristor array circuit simulation task, perform multi-node distributed computing based on a message passing interface, and use multiple processes in each node to run Ngspice simulation tasks in parallel.

[0074] In one embodiment, the simulation output module 506 is also used to call the Ngspice API through the FFI interface to parse the circuit netlist and perform circuit simulation in each memristor array to obtain the sum of the column currents of each part; the output processing module is also used to use regular expressions to process the Ngspice simulation callback results, extract the sum of the column currents output by each memristor array circuit simulation task, and quantize the currents and convert them into digital signals.

[0075] For the specific definition of the memristor array circuit simulation device, please refer to the definition of the memristor array circuit simulation method above, which will not be repeated here. Each module in the above-mentioned memristor array circuit simulation device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0076] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a memristor array circuit simulation method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0077] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0078] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in the above embodiment when executing the computer program.

[0079] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in the above embodiment are implemented.

[0080] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0081] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A memristor array circuit simulation method, characterized in that: The method comprises: Decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks; Based on distributed, multi-process parallel execution of the simulation task, in the simulation task, the weight bits are mapped to multiple device conductances of the memristor array, the input bits are mapped to multiple voltage signals, and a circuit netlist of each memristor array circuit is compiled; The circuit netlist is parsed and a simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage signal and the device conductance value; The current output by each memristor array circuit simulation task is converted into a digital signal, which is then shifted, added, and combined to obtain an integer. The integer is then dequantized into a floating point number and a bias term is added. The network layer output is obtained after quantization again.

2. The method according to claim 1, characterized in that The memristor array circuit includes: traditional 1T1R, Gate-signal 1T1R, Bitline-signal 1T1R, 1R and 2T2R. Only by writing a circuit netlist, circuit simulation of various array structures can be supported. The following method takes traditional 1T1R as an example for explanation.

3. The method according to claim 1, characterized in that The method further comprises: The conduction states of transistors in the memristor array circuit are modeled, and the circuit netlist is modified according to the modeled memristor array circuit.

4. The method according to claim 3, characterized in that The step of modeling the conduction state of transistors in the memristor array circuit comprises: For each row of word lines, the gates of the transistors in the row are connected. The unit resistance of each section on the word line is R_wl_wire. The word line driving signal source Vgate is a DC voltage source. The signal enters the array through the input resistor Rload_1. For each column of bit lines, the memristors R of the column are connected, the unit resistance of each section on the bit line is R_bl_wire, the bit line driving signal source Vread is a DC voltage source, and the signal enters the array through the input resistor Rload_2; The source line of each column connects the sources of the transistors in the column, and the unit resistance of each section of the source line is R_sl_wire. The current passing through each memristor is collected from the source line and flows through the output resistor Rload_3.

5. The method according to claim 3, characterized in that: The step of modeling the conduction state of transistors in the memristor array circuit comprises: When the input signal is 1, the cross cell Rcell is equivalent to a combination of a memristor and a transistor on-resistance; When the input signal is 0, the cross cell Rcell is equivalent to a combination of a memristor and a transistor disconnect resistor; Applying a read voltage using the bit line, maintaining the bit line structure; Use the source line to sink the current and output the current through the output resistor.

6. The method according to claim 1, characterized in that Decompose the single-layer input of a convolutional neural network based on a memristor array circuit into multiple binary input vectors and assign simulation tasks, including: Each input vector is assigned to the corresponding memristor array circuit simulation task, and multi-node distributed computing is performed based on the message passing interface. Multiple processes are used in each node to run the Ngspice simulation task in parallel.

7. The method according to claim 6, characterized in that The circuit netlist is parsed and a simulation is run, and the output current is calculated based on Kirchhoff's law according to the voltage signal and the device conductance value, including: In each memristor array, the Ngspice API is called through the FFI interface to parse the circuit netlist and perform circuit simulation to obtain the sum of the column currents of each part; The step of converting the current output by each memristor array circuit simulation task into a digital signal comprises: Regular expressions are used to process the Ngspice simulation callback results, extract the sum of the currents of each column output by each memristor array circuit simulation task, and quantize the currents into digital signals.

8. A memristor array circuit simulation device, characterized in that: The device comprises: A task decomposition module, used to decompose the single network layer input of the convolutional neural network based on the memristor array circuit into multiple binary input vectors and assign simulation tasks; A netlist writing module is used to execute the simulation task in parallel based on distributed and multi-process, map the weight bits to multiple device conductances of the memristor array in the simulation task, map the input bits to multiple voltage signals, and write a circuit netlist for each memristor array circuit; A simulation output module, which parses the circuit netlist and runs a simulation, and calculates the output current based on Kirchhoff's law according to the voltage signal and the device conductance value; The output processing module is used to convert the current output by each memristor array circuit simulation task into a digital signal, shift, add and combine it to obtain an integer, then dequantize the integer into a floating point number and add a bias term, and quantize it again to obtain the network layer output.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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