Simulation technology method for researching power semiconductor module parallel chip layout current sharing performance

Abstract

The invention relates to a simulation technology method for researching the current sharing property of the parallel chip layout of a power semiconductor module. The method comprises the following steps: 1) analyzing a circuit topology structure of an IGBT power module; 2) building a module internal circuit structure diagram; 3) establishing a three-dimensional model of the IGBT power module through SolidWorks engineering software, checking a simulation result and processing the simulation result; and 4) the result is added to an ideal circuit diagram to generate a circuit diagram capable of reflecting the real situation of the power module, and the current difference situation of the parallel chips can be specifically analyzed by calculating the current flowing through each chip. And 5) analyzing the current sharing difference of the parallel chips under the worst working condition. Compared with a complex and time-consuming module current-sharing experimental test and traditional circuit simulation needing a high-precision Spice device model, the method can more clearly and efficiently judge the current sharing of the layout of the parallel chips of the power modules, and provides a guidance thought for the current-sharing packaging design of the power modules.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor module packaging design, and provides a three-dimensional simulation analysis method for whether high-power and multi-chip parallel power IGBT modules can work normally and stably with current sharing, and specifically relates to a method for studying the simulation technology of the current sharing of parallel chip layout of power semiconductor modules. Background Art

[0002] In high-power engineering applications, ordinary power devices cannot meet the power requirements because the voltage and current are very high during operation. For this working condition, the current level of a single chip can be increased, or a method of connecting multiple chips with small current levels in parallel can be adopted. Due to the difficulty and high manufacturing cost of chips with large and high current levels, power module manufacturers often use the method of connecting multiple chips in parallel to increase the current level of the power module. However, there will be differences in the electrical performance parameters of chips of the same batch model, and parasitic parameters will be introduced in the power module packaging design process. These will affect the shunt capacity of the parallel chips to a certain extent, resulting in uneven current distribution of the parallel chips, and then causing some chips to have excessive electrical and thermal stress, overshoot of the shutdown voltage, and in severe cases, damage to the device and module failure, which greatly reduces the reliability and service life of the power module.

[0003] At present, the research on the current sharing of parallel chips in power modules is mainly divided into static current sharing and dynamic current sharing methods. From the perspective of circuit structure, it is divided into power circuit current sharing and drive control circuit current sharing. The static factors that affect the current sharing of multi-chip parallel operation of power modules mainly include loop impedance, on-resistance, on-state saturation voltage drop, threshold voltage, junction temperature, etc. The dynamic factors mainly include loop parasitic inductance, gate drive circuit, threshold voltage, on-state saturation voltage drop, junction temperature, etc. For these influencing factors, two research ideas are usually adopted: experimental testing and simulation analysis. Testing requires the construction of a test platform, adjustment and control of test conditions and parameters, and destructive testing of the module. The advantage is that it can truly reflect the working status of the chip, and the results are true and reliable. The disadvantage is that the actual operation is time-consuming and laborious. Circuit simulation requires building a test circuit in the circuit simulation software. It is necessary to add parasitic parameters related to the package and bus parasitic parameters and load parameters related to the actual working conditions into the circuit. In particular, when performing dynamic current sharing simulation, it is necessary to establish a high-precision chip Spice device model. The advantages are fast simulation analysis speed and high degree of visualization. The disadvantage is that the chip device model has a high accuracy requirement and cannot fully reflect the actual working status of the chip.

[0004] Therefore, a simulation method for studying the current sharing of parallel chip layout of power semiconductor modules is designed to overcome the above problems. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for studying the simulation technology of the current sharing of the parallel chip layout of the power semiconductor module. The present invention provides a simulation analysis method for judging whether the power module is working with current sharing, and provides a new research idea for the design of module current sharing.

[0006] The present invention is implemented by the following technical scheme: a method for studying the simulation technology of the current sharing of the parallel chip layout of the power semiconductor module, which is used to simulate and analyze the factors affecting the current sharing of the parallel chip of the power module, such as the loop impedance, loop inductance, and on-resistance, which have a greater impact on the current sharing of the parallel chip of the power module, and comprises the following steps:

[0007] 1) Analyze the circuit topology of IGBT power modules, such as half-bridge circuit and full-bridge circuit;

[0008] 2) Build a simple internal circuit diagram of the module;

[0009] 3) Use SolidWorks engineering software to build a 3D model of the IGBT power module, import the 3D model into 3D finite element simulation analysis software Ansys Q3D, and perform calculation and analysis to check the simulation results and perform post-processing of the simulation results;

[0010] 4) Add the results of the power module parasitic parameters after finite element simulation to the ideal circuit diagram to generate a circuit diagram that can reflect the actual situation of the power module. By analyzing the differences in parasitic parameters in the current paths of different chips, the current sharing of the power module package layout can be judged. By viewing the post-processed power module current density cloud map, the current sharing of parallel chips can be intuitively analyzed. By calculating the current flowing through each chip, the current difference of parallel chips can be specifically analyzed.

[0011] 5) By setting different on-resistances of the parallel chips, the current sharing differences of the parallel chips under the worst operating conditions are analyzed.

[0012] As a preferred embodiment: the specific steps of analyzing the half-bridge circuit in step 1) are: calculating the layout current sharing of the upper and lower tubes of the IGBT module with two chips connected in parallel through simulation analysis, and in order to simulate the distributed inductance of the half-bridge IGBT module, the materials inside the module are reasonably set, the bonding wires and power terminals and the upper and lower surface covering layers of the DBC are copper, and the IGBT chip needs to add new materials according to its characteristics, and the output characteristic curve of the module data manual is consulted, and the output characteristic curve at room temperature is used to achieve V CE(sat) The corresponding current value is used to calculate the typical value of the on-resistance of the IGBT chip according to Ohm's law, and then the conductivity of the IGBT chip material is calculated.

[0013] Preferably: the calculation and analysis of step 3) is specifically to check whether the internal chips, bonding wires, DBC, and power signal terminals of the model are in normal contact, analyze the flow path of the internal current of the module during operation, process the model, add and set the external voltage and current excitation source, set the simulation conditions and run the simulation, view the simulation results and perform post-processing of the simulation results.

[0014] Preferably, the current density cloud map in step 4) is a three-dimensional current density cloud map inside the module with a high degree of visualization.

[0015] The beneficial effects of the present invention are as follows:

[0016] The present invention uses Ansys Q3D three-dimensional finite element simulation of the power module's package parasitic parameters, draws an equivalent circuit diagram containing the package parasitic parameters, calculates the current flowing through each chip, and generates a highly visualized three-dimensional current density cloud map inside the module. Compared with the complex and time-consuming module current sharing experimental test and the traditional circuit simulation that requires a high-precision Spice device model, the present invention can more clearly and efficiently judge the current sharing of the power module parallel chip layout, and provide guidance for the power module current sharing package design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the external structure diagram of the IGBT module in the present invention;

[0018] Figure 2 This is the internal structure diagram of the IGBT module in the present invention;

[0019] Figure 3 This is a diagram of the internal circuit structure of the IGBT module in the present invention;

[0020] Figure 4 This is a current path diagram of the upper tube of the IGBT module in the present invention;

[0021] Figure 5 This is a current path diagram of the lower tube of the IGBT module in the present invention;

[0022] Figure 6 This is a cloud diagram of the tube current density of the IGBT module in the present invention;

[0023] Figure 7 The current density cloud diagram of the lower tube of the IGBT module in the present invention;

[0024] Figure 8 The IGBT module of the present invention includes an equivalent circuit diagram of parasitic parameters;

[0025] Fig. 9 This is a current path diagram of the upper tube of the three-parallel IGBT module of the present invention;

[0026] Fig.10This is the current path diagram of the lower tube of the three-parallel IGBT module of the present invention;

[0027] Fig.11 This is a cloud diagram of the tube current density of the three-parallel IGBT module of the present invention;

[0028] Fig.12 This is a cloud diagram of the current density of the lower tube of the three-parallel IGBT module of the present invention;

[0029] Fig.13 This is a cloud diagram of the upper tube current density of the three-parallel IGBT module in the worst working condition of the present invention;

[0030] Fig.14 This is a tube current density cloud diagram of the three-parallel IGBT module of the present invention under the worst operating condition. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to more clearly understand the objectives, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0032] In the description of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms such as "up", "down", "left", "right", "inside", "outside", "horizontal" and "vertical" is based on the orientation or position relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0033] The present invention will be described in detail below with reference to the accompanying drawings: Figure 1 As shown, a method for studying the simulation technology of the current sharing of the parallel chip layout of the power semiconductor module is used to simulate and analyze the factors affecting the current sharing of the parallel chip of the power module, such as the loop impedance, loop inductance, and on-resistance, which have a greater impact on the current sharing of the parallel chip of the power module, and includes the following steps:

[0034] 1) Analyze the circuit topology of IGBT power modules, such as half-bridge circuit and full-bridge circuit;

[0035] 2) Build a simple internal circuit diagram of the module;

[0036] 3) Use SolidWorks engineering software to build a 3D model of the IGBT power module, import the 3D model into the 3D finite element simulation analysis software Ansys Q3D, check whether the internal chip, bonding wire, DBC, and power signal terminal of the model are in normal contact, analyze the flow path of the internal current of the module during operation, process the model, add and set the external voltage and current excitation source, set the simulation conditions and run the simulation, view the simulation results and perform post-processing of the simulation results;

[0037] 4) Add the results of the power module parasitic parameters after finite element simulation to the ideal circuit diagram to generate a circuit diagram that can reflect the actual situation of the power module. By analyzing the differences in parasitic parameters in the current paths of different chips, the current sharing of the power module package layout can be judged. By viewing the post-processed power module current density cloud map, the current sharing of parallel chips can be intuitively analyzed. By calculating the current flowing through each chip, the current difference of parallel chips can be specifically analyzed.

[0038] 5) By setting different on-resistances of the parallel chips, the current sharing differences of the parallel chips under the worst operating conditions are analyzed.

[0039] As a preferred embodiment: the specific steps of analyzing the half-bridge circuit in step 1) are: calculating the layout current sharing of the upper and lower tubes of the IGBT module with two chips connected in parallel through simulation analysis, and in order to simulate the distributed inductance of the half-bridge IGBT module, the materials inside the module are reasonably set, the bonding wires and power terminals and the upper and lower surface covering layers of the DBC are copper, and the IGBT chip needs to add new materials according to its characteristics, and the output characteristic curve of the module data manual is consulted, and the output characteristic curve at room temperature is used to achieve V CE(sat) The current value corresponding to the time is calculated, and the typical value of the on-resistance of the IGBT chip is calculated according to Ohm's law, and then the conductivity of the IGBT chip material is calculated. The current density cloud map in step 4) is a three-dimensional current density cloud map inside the module with a high degree of visualization.

[0040] Example

[0041] Take StarPower's IGBT module GD500HTA75N8HT as an example. Figure 1 It is the external structure of the IGBT module. Figure 2 It is the internal structure of the IGBT module. Figure 2 It can be seen that the GD500HTA75N8HT module is a full-bridge circuit topology, and the internal layout of the three phases is exactly the same, so one of the phases is selected for simulation analysis. Figure 3 This is a simple equivalent circuit diagram of the left phase of the IGBT module. It can be seen from the figure that this is a half-bridge circuit structure. DC+, DC- and AC are power terminals, G, E, and C are signal terminals, T1_1 and T1_2 are two parallel IGBT chips on the upper tube, D1_1 and D1_2 are two parallel Diode chips on the upper tube, T2_1 and T2_2 are two parallel IGBT chips on the lower tube, and D2_1 and D2_2 are two parallel Diode chips on the lower tube.

[0042] This paper mainly calculates the layout current sharing of the upper and lower tubes of the IGBT module with two chips connected in parallel through simulation analysis. Figure 4It is the power loop current path when the upper tube of the IGBT module is working. The current flows from the DC+ terminal through the DBC to the lower surface of the upper tube IGBT chip, passes through the IGBT chip, bonding wire, and DBC and flows out from the AC terminal. Figure 5 It is the power loop current path when the lower tube of the IGBT module is working. The current flows from the AC terminal through the DBC to the lower surface of the lower tube IGBT chip, and then flows through the IGBT chip, bonding wire, and DBC from the DC-terminal. In order to simulate the distributed inductance of the half-bridge IGBT module, it is necessary to reasonably set the materials inside the module. The bonding wires, power terminals, and upper and lower surfaces of the DBC are covered with copper. The IGBT chip needs to add new materials according to its characteristics. The output characteristic curve of the module data manual is consulted, and the output characteristic curve at room temperature is used to achieve V CE(sat) The corresponding current value is calculated according to Ohm's law, and the typical value of the on-resistance of the IGBT chip is calculated, and then the conductivity of the IGBT chip material is calculated to be 172s / m. Figure 4 It can be seen that the upper surface of the DC+ terminal needs to be set as the surface where the current flows in, and the upper surface of the AC terminal needs to be set as the surface where the current flows out, Figure 5 It can be seen that the upper surface of the AC terminal needs to be set as the surface where the current flows in, and the upper surface of the DC-terminal needs to be set as the surface where the current flows out, and the Sink. The rated current of the IGBT module is 500A, so the external excitation current source is set to 500A. The simulation frequency is generally set to 10Mhz. After the inspection is completed, run the simulation.

[0043] Figure 6 and Figure 7 This is the current density cloud map of the upper and lower tubes of the module obtained after post-processing of the simulation results. The current density cloud map can intuitively reflect the distribution of the current inside the module. From the figure, it can be seen that the current density distribution of the parallel chips of the upper and lower tubes of the IGBT module is relatively symmetrical, and the current sharing is good. The specific current value passing through the parallel chips can be calculated by integration, which can be achieved through the Fields calculator in Ansys Q3D. The calculation results are as follows:

[0044] Table 1 Current flowing through the parallel chips of the upper and lower tubes of the IGBT module

[0045]

[0046] Imbalance I Defined as:

[0047]

[0048] Among them I k is the current passing through each chip, It is the average value of the current passing through the parallel chips. From the calculation results in Table 1, it can be seen that the imbalance of the current of the two parallel chips on the upper tube is ±0.4%, and the imbalance of the current of the two parallel chips on the lower tube is ±0.4%. The current equalization of the parallel chips on the upper and lower tubes of the IGBT module is good.

[0049] Table 2 Distributed parasitic parameters of IGBT chips in parallel in the power circuit of the upper tube of the IGBT module

[0050]

[0051] Table 3 Distributed parasitic parameters of IGBT chips in parallel in the power circuit of the lower tube of the IGBT module

[0052]

[0053] Table 2 and Table 3 show the distributed parasitic inductance and parasitic resistance parameters of the parallel chips in the power loop of the upper and lower tubes of the IGBT. From the data in the table, it can be seen that the parasitic parameters of the upper and lower tube chips to the DC+ and DC- terminals are slightly different, and the parasitic parameters of the upper and lower tube chips to the AC terminal are slightly different. Figure 4 and Figure 5 It can be seen that the layout of the DC+ and DC- power terminals and the two parallel chips of the upper and lower tubes is relatively symmetrical, so the distribution of parasitic parameters is relatively balanced. The layout of the AC terminal and the two parallel chips of the upper and lower tubes is slightly less symmetrical, so the distribution of parasitic parameters is not very balanced.

[0054] Figure 8 It is the equivalent circuit diagram of the IGBT module including parasitic parameters, which includes the distributed parasitic inductance and parasitic resistance of the parallel IGBT and Diode chips, as well as the parasitic parameters of the control signal loop. From the figure, we can intuitively judge the difference in the parasitic parameters of the parallel chips in the current path. The parasitic resistance mainly affects the static current sharing of the parallel chips, and the parasitic inductance affects the dynamic current sharing of the parallel chips. From the figure, we can see that the parasitic parameters of the parallel chips in the power circuit are slightly different, while the parasitic parameters of the parallel chips in the control circuit are quite different. Figure 2 It can be seen that the distances between the control signal terminals G, E and C and the parallel chips are quite different, so the parasitic parameters are very different. The power circuit carries a large current, and the signal circuit carries a small current. The power circuit has a greater impact on the current sharing of the power module, so the overall current sharing of the IGBT module is relatively good.

[0055] Take StarPower's IGBT module GD820HTX75P6HB as an example to explore the current sharing of parallel chips in the worst case. Its circuit topology is full bridge, the rated voltage is 750V, the rated current is 820A, and the package type is P6 package. Fig. 9This is the internal circuit of one phase of the GD820HTX75P6HB module. The power terminals DC+ and DC- are overlapped to reduce the parasitic inductance of the power circuit. The module is a parallel connection of 3 chips. In the actual module packaging process, the parameters of chips of the same batch model will also be different. The on-state saturation voltage drop V CE(sat) The minimum, typical and maximum values ​​of the on-resistance of the parallel chips are calculated, and then the conductivity of the chip material is obtained. The conductivity of the IGBT chip material is calculated as follows: Minimum conductivity σ min is 399s / m, typical conductivity σ typ is 411s / m, the maximum conductivity σ max In order to analyze the current sharing of the parallel chips in the worst case, the conductivity of the materials of the three parallel chips is first set to the typical value of conductivity σ typ , the simulation analysis calculates the current value flowing through each chip, and then sets the conductivity of the chip material with the maximum current to σ max , set the conductivity of the chip material with the minimum current to σ min This can make the chip with large current have a larger current capacity, and the chip with small current have a smaller current capacity. Therefore, the current sharing of parallel chips in extreme cases can be simulated. If the current sharing in the worst case still meets the working conditions, then the module has good current sharing.

[0056] Fig. 9 and Fig.10 They are the upper tube current path of the three-parallel IGBT module and the lower tube current path of the three-parallel IGBT module. T1_1, T1_2 and T1_3 are the three parallel IGBT chips on the upper tube, and T2_1, T2_2 and T2_3 are the three parallel IGBT chips on the lower tube. According to the actual working conditions, the external current excitation is set to 510A and the simulation frequency is set to 10Mhz. Fig.11 and Fig.12 They are the cloud diagrams of the current density of the upper tube of the three-parallel IGBT module and the cloud diagram of the current density of the lower tube of the three-parallel IGBT module. Table 4 is the integral calculation value of the current flowing through the parallel chips of the upper tube and the lower tube of the three-parallel IGBT module. Fig.11 , Fig.12 It can be seen from Table 4 that the upper tube T1_3 chip has the largest current and the T1_2 chip has the smallest current, the lower tube T2_1 chip has the largest current and the T2_2 chip has the smallest current, and the imbalance of the upper and lower tube parallel chips is controlled within ±3%, meeting the working condition requirements.

[0057] Table 4 Current flowing through the parallel chips of the upper and lower tubes of the three-parallel IGBT module

[0058]

[0059] In order to simulate the worst-case current sharing of parallel chips, the conductivity of chip T1_3 is set to σ max , the conductivity of chip T1_2 is set to σ min , the conductivity of chip T2_1 is set to σ max , the conductivity of T2_2 chip is set to σ min , Fig.13 and Fig.14 They are the current density cloud diagrams of the upper tube and lower tube of the three-parallel IGBT module under the worst working condition. Table 5 is the integral calculation value of the current flowing through the parallel chips of the upper tube and lower tube of the three-parallel IGBT module under the worst working condition. Fig.13 , Fig.14 It can be seen from Table 5 that the current difference through the upper tube T1_3 chip and the T1_2 chip is larger, and the current difference through the lower tube T2_1 chip and the T2_2 chip is larger. The imbalance of the upper tube and the lower tube parallel chips is controlled within ±5%, which still meets the working condition requirements.

[0060] Table 5 Current flowing through the upper and lower parallel chips of the three-parallel IGBT module under the worst working condition

[0061]

[0062] in conclusion

[0063] In order to solve the problem of current sharing in parallel chip layout of power semiconductor module, this paper analyzes and calculates whether the parallel chips share current from the perspective of three-dimensional finite element simulation calculation. Taking the IGBT module with two chips in parallel as an example, the influence of loop impedance, on-resistance and loop inductance on the current sharing of parallel chip layout is studied through Ansys Q3D finite element simulation. Taking the IGBT module with three chips in parallel as an example, the current imbalance of parallel chips is simulated and analyzed to explore the current sharing of parallel chips under the worst working conditions. Through simulation analysis and calculation, this paper can judge the current sharing of parallel chips more clearly and intuitively, and provide guidance for the packaging design of power modules regarding the current sharing of parallel chip layout.

[0064] The specific embodiments described herein are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for studying the simulation technology of current sharing of parallel chip layout of power semiconductor module, which is used to simulate and analyze the factors affecting the current sharing of parallel chip of power module, such as loop impedance, loop inductance and on-resistance, which have a great influence on the current sharing of parallel chip of power module, and is characterized in that: The steps include: 1) Analyze the circuit topology of IGBT power modules, such as half-bridge circuit and full-bridge circuit; 2) Build a simple internal circuit diagram of the module; 3) Use SolidWorks engineering software to build a 3D model of the IGBT power module, import the 3D model into 3D finite element simulation analysis software Ansys Q3D, and perform calculation and analysis to check the simulation results and perform post-processing of the simulation results; 4) Add the results of the power module parasitic parameters simulated by finite element simulation to the ideal circuit diagram to generate a circuit diagram that can reflect the actual situation of the power module. By analyzing the differences in parasitic parameters in the current paths of different chips, the current uniformity of the power module package layout can be judged. By viewing the post-processed power module current density cloud map, the current uniformity of the parallel chips can be intuitively analyzed. By calculating the current flowing through each chip, the current difference of the parallel chips can be specifically analyzed. 5) By setting different on-resistances of the parallel chips, the current sharing differences of the parallel chips under the worst operating conditions are analyzed.

2. The method for simulating the current sharing of parallel chip layout of power semiconductor modules according to claim 1, characterized in that: The specific steps of analyzing the half-bridge circuit in step 1) are: calculating the layout current sharing of the upper and lower tubes of the IGBT module with two chips connected in parallel through simulation analysis, and reasonably setting the materials inside the module in order to simulate the distributed inductance of the half-bridge IGBT module. The bonding wires, power terminals and upper and lower surface covering layers of DBC are copper. New materials are added to the IGBT chip according to its characteristics. The output characteristic curve of the module data manual is consulted, and the output characteristic curve at room temperature is used to achieve V CE(sat) The corresponding current value is used to calculate the typical value of the on-resistance of the IGBT chip according to Ohm's law, and then the conductivity of the IGBT chip material is calculated.

3. The method for simulating the current sharing of parallel chip layout of power semiconductor modules according to claim 1, characterized in that: The calculation and analysis of step 3) is specifically to check whether the internal chips, bonding wires, DBC, and power signal terminals of the model are in normal contact, analyze the flow path of the internal current of the module during operation, process the model, add and set the external voltage and current excitation source, set the simulation conditions and run the simulation, view the simulation results and perform post-processing of the simulation results.

4. The method for simulating the current sharing of parallel chip layout of power semiconductor modules according to claim 1, characterized in that: The current density cloud map in step 4) is a three-dimensional current density cloud map inside the module with a high degree of visualization.

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