Power supply network wiring detection method and device, electronic equipment and storage medium

Abstract

The invention relates to a power supply network wiring detection method and device, electronic equipment and a storage medium, and belongs to the field of integrated circuits. The power supply network wiring detection method comprises the following steps: determining an overlapping region of adjacent metal layers in a network where a target power supply network in a chip is located according to a graphic data system file of the chip; detecting whether the through hole pattern in the overlapping region is a target through hole pattern or not to determine whether the adjacent metal layers are fully connected or not; wherein when the through hole pattern in the overlapping area is the target through hole pattern, it is determined that the adjacent metal layers are fully connected. According to the method, the whole chip is detected based on the graphic data system file of the chip, so that the detection is more comprehensive, and the missing detection is reduced; and meanwhile, whether the adjacent metal layers are fully connected or not is quickly determined by detecting whether the through hole pattern in the overlapping region of the adjacent metal layers in the target PG net (the power supply network is on line network) is the target through hole pattern or not, so that the detection efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuits, and specifically relates to a detection method, device, electronic device and storage medium for power network wiring. Background Art

[0002] The input process files in the physical implementation process will define some design rules. EDA (Electronic Design Automation) tools will avoid design violations by routing based on these rules. If the tool behavior and design rules do not match well, it may cause some power networks (Power and Ground, PG) to have weak or insufficient connections; or some human settings may cause some PG nets to have weak or insufficient connections; and some PG nets are special nets that have high requirements for the quality of the routing and usually require manual routing, which can easily cause leaks or insufficient connections. Therefore, in order to improve DFM (Design for Manufacturing, Design for Manufacturing Feasibility), ensuring the robustness or sufficiency of the connection relationship plays an important role in improving chip yield. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a method, device, electronic device and storage medium for detecting power network wiring, so as to comprehensively and quickly detect whether the connection between adjacent metal layers in the wire network where the power network is located is sufficient.

[0004] The embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a method for detecting power network wiring, comprising: determining, according to a graphic data system file of the chip, an overlapping area of ​​adjacent metal layers in a network where a target power network in the chip is located; detecting whether a through-hole pattern in the overlapping area is a target through-hole pattern to determine whether the adjacent metal layers are fully connected; wherein the target through-hole pattern is a through-hole pattern with the best power network connection performance corresponding to the overlapping area; when the through-hole pattern in the overlapping area is the target through-hole pattern, determining that the adjacent metal layers are fully connected.

[0006] In the above embodiment, the present application performs full-chip detection based on the chip's graphic data system file, which can make the detection more comprehensive and reduce missed detections; at the same time, by detecting whether the through-hole pattern in the overlapping area of ​​adjacent metal layers in the target PG net (the line network where the power network is located) is the target through-hole pattern, it is possible to quickly determine whether the adjacent metal layers are fully connected, which is beneficial to improving detection efficiency.

[0007] In combination with a possible implementation method of the first aspect, according to the graphics data system file of the chip, determining the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located, including: determining all metal layers of the line network where the target power network is located according to the graphics data system file of the chip; obtaining the overlapping area of ​​adjacent metal layers in all the metal layers.

[0008] In the above embodiment, all metal layers of the target power network are first found according to the graphic data system file, and then the overlapping area of ​​adjacent metal layers (upper and lower metal layers) is obtained from all the obtained metal layers, so that the required overlapping area can be quickly found.

[0009] In combination with a possible implementation method of the first aspect, determining the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located according to the graphics data system file of the chip, including: determining the overlapping area of ​​each adjacent metal layer in the chip according to the graphics data system file of the chip; and finding the overlapping area of ​​adjacent metal layers in the line network where the target power network is located from the overlapping areas of each adjacent metal layer.

[0010] In the above embodiment, the overlapping areas of all adjacent metal layers in the chip are first found according to the graphic data system file, and then the overlapping areas of adjacent metal layers in the line network where the target power network is located are screened out from all the overlapping areas, providing another solution for finding the required overlapping areas.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, detecting whether the through-hole pattern in the overlapping area is a target through-hole pattern includes: obtaining a target through-hole pattern corresponding to the overlapping area, wherein the target through-hole pattern is determined based on the voltage drop and electromigration performance of the circuit and the process characteristics requirements of the circuit design; comparing the through-hole pattern in the overlapping area with the target through-hole pattern corresponding to the overlapping area to obtain a comparison result; and determining whether the through-hole pattern in the overlapping area is the target through-hole pattern based on the comparison result.

[0012] In the above embodiment, by determining the target through-hole pattern corresponding to the overlapping area in advance, when subsequently detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern, it is only necessary to compare the through-hole pattern in the overlapping area with the target through-hole pattern corresponding to the overlapping area, so as to quickly determine whether the through-hole pattern in the overlapping area is the target through-hole pattern.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the number of overlapping areas is multiple, corresponding to multiple target through-hole styles; the through-hole styles in the overlapping areas are compared with the target through-hole styles corresponding to the overlapping areas, including: sorting the overlapping areas corresponding to the multiple target through-hole styles according to the size of the overlapping areas to obtain a first sorting result; sorting the multiple overlapping areas according to the size of the overlapping areas to obtain a second sorting result; comparing the through-hole styles in the same sorting position in the first sorting result and the second sorting result.

[0014] In the above embodiment, by sorting the overlapping area where the designed through-hole style is located and the overlapping area corresponding to the target through-hole style, when comparing the through-hole styles, only the through-hole styles in the area with the same sorting position need to be compared. In this way, the target through-hole style to be compared can be searched quickly, thereby improving the comparison efficiency.

[0015] In combination with a possible implementation method of the first aspect, detecting whether the through-hole pattern in the overlapping area is a target through-hole pattern includes: obtaining a blank area in the overlapping area that does not contain a through-hole; while meeting circuit design requirements, determining whether the blank area can additionally set at least one through-hole in the overlapping area to obtain a judgment result; and determining whether the through-hole pattern in the overlapping area is a target through-hole pattern based on the judgment result.

[0016] In the above embodiment, by obtaining the blank area in the overlapping area that does not contain a through hole, it is determined whether the blank area can be additionally provided with at least one through hole in the overlapping area while meeting the circuit design requirements, so that it can be quickly determined whether the through hole pattern in the overlapping area is the target through hole pattern. For example, if the judgment result indicates that the blank area can be provided with at least one through hole in the overlapping area, it is considered that the through hole pattern in the overlapping area is not the target through hole pattern. This solution does not require the target through hole pattern corresponding to the overlapping area to be determined in advance, and can be used as a supplementary solution for how to detect whether the through hole pattern in the overlapping area is the target through hole pattern.

[0017] In combination with a possible implementation manner of the embodiment of the first aspect, the method further includes: when adjacent metal layers are not sufficiently connected, marking the adjacent metal layers that are not sufficiently connected.

[0018] In the above embodiment, if adjacent metal layers are not sufficiently connected, the adjacent metal layers that are not sufficiently connected are marked, so that the adjacent metal layers that are not sufficiently connected can be quickly located according to the mark, thereby facilitating subsequent layout optimization.

[0019] In the second aspect, an embodiment of the present application also provides a detection device for power network wiring, including: an acquisition module and a detection module; the acquisition module is used to determine the overlapping area of ​​adjacent metal layers in the network where the target power network in the chip is located according to the graphic data system file of the chip; the detection module is used to detect whether the through-hole pattern in the overlapping area is the target through-hole pattern, so as to determine whether the adjacent metal layers are fully connected; wherein the target through-hole pattern is the through-hole pattern with the best power network connection performance corresponding to the overlapping area; when the through-hole pattern in the overlapping area is the target through-hole pattern, it is determined that the adjacent metal layers are fully connected.

[0020] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a memory and a processor, the processor being connected to the memory; the memory being used to store programs; the processor being used to call the programs stored in the memory to execute a method provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment.

[0021] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method provided in the embodiment of the first aspect and / or any possible implementation method in combination with the embodiment of the first aspect is executed.

[0022] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0024] Figure 1 A schematic flow chart of a method for detecting power network wiring provided in an embodiment of the present application is shown.

[0025] Figure 2 A schematic diagram showing a through hole in an overlapping area provided by an embodiment of the present application that is not a target through hole pattern is shown.

[0026] Figure 3a A schematic diagram of selecting a target through-hole pattern provided in an embodiment of the present application is shown.

[0027] Figure 3bA schematic diagram of another method for selecting a target through-hole pattern provided in an embodiment of the present application is shown.

[0028] Figure 4 A module schematic diagram of a power network wiring detection device provided in an embodiment of the present application is shown.

[0029] Figure 5 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0031] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0032] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0033] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0034] In view of the fact that existing methods for detecting whether the power network's lines (PG net) are sufficiently connected have problems such as low detection efficiency and possible omissions, an embodiment of the present application provides a power network wiring detection method to comprehensively and quickly detect whether the connection between adjacent metal layers in the power network's lines is sufficient, which plays an important role in improving chip performance and improving chip yield.

[0035] The detection method of power network wiring provided in the embodiment of the present application performs full chip detection based on the chip's Graphic Data System (GDS) file, which can make the detection more comprehensive, thereby reducing missed detections; at the same time, by detecting whether the through-hole pattern in the overlapping area of ​​adjacent metal layers in the PG net is the target through-hole pattern, it is quickly determined whether the adjacent metal layers are fully connected, which is conducive to improving the detection efficiency. Among them, the power network corresponding to the target through-hole pattern has the best connection performance, that is, the connection performance of the power network connected based on the target through-hole pattern is better than that of the power network connected based on other through-hole patterns.

[0036] The power network wiring detection method provided in the embodiment of the present application can detect the physical layout and connection quality of the power network, which can include checking whether the layout of the power line is reasonable, whether there is poor contact (whether the connection is sufficient), corrosion, breakage and other problems. The power network wiring detection method can use electronic design automation technology to evaluate the quality of the wiring. This method is important for ensuring the long-term stability of the power network and reducing the risk of failure. Figure 1 The power supply network wiring detection method provided in the embodiment of the present application is described.

[0037] S1: According to the graphic data system file of the chip, determine the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located.

[0038] When detecting the power network wiring in the chip, EDA tools can be used for detection. For example, the EDA tool can be used to read the GDS file of the chip, and based on the GDS file, the overlapping area of ​​adjacent metal layers in the wiring network where the target power network in the chip is located is determined.

[0039] In some possible implementations, the design rule file may be directly called by the EDA tool to read the GDS file and perform subsequent processing. In this implementation, the user does not need to manually select the GDS file to be read.

[0040] Among them, the GDS file of the chip contains detailed information such as the chip's geometry, hierarchy, circuit elements and connections. Based on the GDS file, the overlapping area of ​​adjacent metal layers in the network where the target power network in the chip is located can be quickly and comprehensively determined.

[0041] It is understandable that there are usually multiple power nets (PG) in the chip, corresponding to different voltage domains, and the target power net is one of the multiple power nets, which can be manually specified by the user. The user can select the PG to be detected in the EDA tool. For example, assuming that the PG nets in the chip include PG netA, PG netB, and PG netC, the user can specify PG netA as the target PG net to be detected.

[0042] In one possible implementation, the implementation process of S1 may include: determining all metal layers of the line network where the target power network is located according to the GDS file of the chip, and obtaining the overlapping area of ​​adjacent metal layers in all metal layers. In this implementation, all metal layers of the line network where the target power network is located are first found, and then the overlapping area of ​​adjacent metal layers (upper and lower metal layers) is obtained from all the obtained metal layers.

[0043] In another possible implementation, the implementation process of S1 may include: determining the overlapping areas of each adjacent metal layer in the chip according to the GDS file of the chip, and finding the overlapping areas of adjacent metal layers in the line network where the target power network is located from the overlapping areas of each adjacent metal layer. In this implementation, the overlapping areas of all adjacent metal layers in the chip are first found, and then the overlapping areas of adjacent metal layers in the line network where the target power network is located are screened out from all the overlapping areas.

[0044] When finding the overlapping area of ​​adjacent metal layers in the wire mesh where the target power network is located from the overlapping areas of each adjacent metal layer, it can be determined whether the adjacent metal layers with overlapping areas are the same wire mesh where the target power network is located. If so, the overlapping area of ​​the adjacent metal layers is the overlapping area of ​​the adjacent metal layers in the wire mesh where the target power network is located.

[0045] When determining the overlapping area of ​​adjacent metal layers, graphic operations can be used, for example, through AND and OR operations, to obtain the overlapping area of ​​the upper and lower layers (i.e., the overlapping area) and the through-hole pattern in the area. For example, the overlapping area of ​​the upper and lower layers can be obtained through AND operations, and then the through-hole pattern in the area can be obtained by performing OR operations on the area.

[0046] S2: Detecting whether the through-hole pattern in the overlapping area is a target through-hole pattern to determine whether the adjacent metal layers are sufficiently connected.

[0047] After determining the overlapping area of ​​adjacent metal layers in the network where the target power network in the chip is located, by detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern, it is possible to quickly determine whether the adjacent metal layers are fully connected, wherein when the through-hole pattern in the overlapping area is the target through-hole pattern, it is determined that the adjacent metal layers are fully connected, and conversely, when the through-hole pattern in the overlapping area is not the target through-hole pattern, it is determined that the adjacent metal layers are not fully connected.

[0048] The via pattern refers to the arrangement pattern of at least one via used for electrical connection between different metal layers in a chip, which may include the shape, quantity and layout pattern of each via. In the embodiment of the present application, if the via pattern in the overlapping area of ​​adjacent metal layers is the target via pattern, the adjacent metal layers are considered to be fully connected, otherwise, they are considered to be not fully connected.

[0049] Among them, the vias in the overlapping area are conductive holes that connect different circuit layers. In the overlapping area, the shape and layout of the vias need to be carefully designed to ensure the reliability and performance of the circuit. For example, the diameter, position and distribution of the vias will affect the signal integrity and power integrity of the circuit. Since the target via pattern is the via pattern with the best power network connection performance corresponding to the overlapping area. Therefore, if the via pattern in the overlapping area is the target via pattern, the reliability and performance of the circuit can be better.

[0050] In one possible implementation, the process of detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern may include: determining whether the overlapping area contains a through-hole pattern; if the overlapping area does not contain a through-hole pattern, determining that the through-hole pattern in the overlapping area is not the target through-hole pattern; if the overlapping area contains a through-hole pattern, then detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern.

[0051] Among them, the through-hole style in the overlap area is usually not the target through-hole style and can include the following two categories: Figure 2 The through holes in the overlapping area of ​​adjacent metal layers of power netA are taken as an example for explanation. Figure 2 Region 1 represents the overlapping region of the mth layer and the m-1th layer in powernetA, and region 2 represents the overlapping region of the mth layer and the m+1th layer in powernetA, where m is an integer greater than or equal to 2. Although region 1 contains vias, the number or density of vias is insufficient, so the via pattern is not the target via pattern, resulting in a weak connection between the metal layers. Region 2 does not contain vias, resulting in the metal layers not being connected and not being the target via pattern.

[0052] In one possible implementation, the process of detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern may include: obtaining the target through-hole pattern corresponding to the overlapping area, comparing the through-hole pattern in the overlapping area with the target through-hole pattern corresponding to the overlapping area, obtaining a comparison result, and determining whether the through-hole pattern in the overlapping area is the target through-hole pattern according to the comparison result. In this implementation, by determining the target through-hole pattern corresponding to the overlapping area in advance, when subsequently detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern, it is only necessary to compare the through-hole pattern in the overlapping area with the target through-hole pattern corresponding to the overlapping area, so as to quickly determine whether the through-hole pattern in the overlapping area is the target through-hole pattern. For example, if the comparison result indicates that the through-hole pattern in the overlapping area is the same as the target through-hole pattern corresponding to the overlapping area, then the through-hole pattern in the overlapping area is considered to be the target through-hole pattern, otherwise, it is not the target through-hole pattern.

[0053] The target through-hole pattern is the through-hole pattern with the best power network connection performance corresponding to the overlapping area. The through-hole pattern with the best power network connection performance can be selected in advance from a plurality of through-hole pattern combinations corresponding to the overlapping area as the target through-hole pattern.

[0054] In one implementation, the target via pattern can be determined based on the voltage drop (IR Drop, where I is current and R is resistance) and electromigration performance (EM) of the circuit and the process characteristics requirements of the circuit design (which may include the size of the overlapping area of ​​different metal layers, the shape of the vias in the overlapping area, the distance between the vias and the edge of the overlapping area, etc.). In order to enhance the robustness of the power network connection, improve DFM reliability and chip yield, multiple via patterns can be designed for the same overlapping area in advance based on IREM performance (i.e., the voltage drop and electromigration performance of the circuit) and process characteristics requirements. The shape, quantity and / or layout of the vias in different via patterns can be different; then, multiple via patterns corresponding to the same overlapping area are simulated, and the target via pattern is determined from the combination of multiple via patterns corresponding to the overlapping area.

[0055] When determining the target through-hole style from the multiple through-hole style combinations corresponding to the overlapping area, the through-hole style with the best power network connection performance can be selected from the multiple through-hole style combinations corresponding to the overlapping area. For example, the through-hole style with low resistance, high current carrying capacity and highest space utilization can be selected as the target through-hole style. In another embodiment, the through-hole style with the largest contact area between two adjacent layers can be selected from the multiple through-hole style combinations as the target through-hole style. Among them, the through-hole style with the largest contact area corresponds to a smaller resistance, a higher current carrying capacity and a higher space utilization.

[0056] In the same manner as above, target through-hole patterns corresponding to overlapping areas of different sizes can be obtained, for example, target through-hole pattern 1 corresponding to overlapping area 1, target through-hole pattern 2 corresponding to overlapping area 2, target through-hole pattern 3 corresponding to overlapping area 3, and target through-hole pattern 4 corresponding to overlapping area 4. The sizes of overlapping area 1, overlapping area 2, overlapping area 3, and overlapping area 4 are different, and overlapping areas of different sizes correspond to different target through-hole patterns.

[0057] In order to better illustrate the above process of determining the target through-hole pattern from a combination of multiple through-hole patterns, Figure 3a , Figure 3b To explain, Figure 3a The overlapping area shown is the overlapping area of ​​the mth layer and the m-1th layer of metal, which is recorded as overlapping area 1; Figure 3b The overlapping area shown is the overlapping area of ​​the mth layer and the m+1th layer of metal, which is recorded as overlapping area 2. The sizes of these two overlapping areas are different, and the corresponding through-hole styles are also different. Figure 3a = Overlap area 1 has 2 through hole styles, Figure 3b There are three through-hole patterns in the overlapping area 2, and based on the above selection criteria for the target through-hole pattern, it can be seen that the through-hole pattern with the largest contact area between two adjacent layers is selected as the target through-hole pattern. Therefore, based on this selection criterion, Figure 3a The two through-hole styles of the mth and m-1th metal layers are selected. Figure 3a The through-hole pattern on the left side of the example shown is the target through-hole pattern. Similarly, for Figure 3b The three through-hole styles of the mth and m+1th metal layers are selected. Figure 3b The via pattern on the left in the example shown is the target via pattern.

[0058] It should be noted that when designing a chip, the higher the metal layer in the chip (the closer to the top layer), the larger the minimum width of the overlapping area with the adjacent metal layer. That is, the minimum width of the overlapping area between the mth layer and the m+1th layer is greater than or equal to the minimum width of the overlapping area between the mth layer and the m-1th layer.

[0059] It is understandable that, since the metal layer of the line network where the target power network is located can have multiple overlapping areas of adjacent metal layers, correspondingly, there will be multiple target via patterns, and one overlapping area corresponds to one target via pattern. When comparing the via pattern in the overlapping area (i.e., the designed via pattern) with the target via pattern corresponding to the overlapping area, it is necessary to compare the designed via pattern with the target via pattern in the overlapping area of ​​the same size, otherwise it is meaningless.

[0060] In order to speed up the comparison, in one possible implementation, when comparing the through-hole pattern in the overlapping area with the target through-hole pattern corresponding to the overlapping area, the process may include: sorting the overlapping areas corresponding to multiple target through-hole patterns according to the size of the overlapping area to obtain a first sorting result, sorting the multiple overlapping areas according to the size of the overlapping area to obtain a second sorting result, and comparing the through-hole patterns at the same sorting position in the first sorting result and the second sorting result. When comparing the through-hole patterns at the same sorting position in the first sorting result and the second sorting result, the number, shape, and layout of through-holes in the design through-hole pattern (the through-hole pattern in the overlapping area) and the target through-hole pattern may be compared. If the number, shape, and layout of through-holes are the same, the design through-hole pattern is considered to be the target through-hole pattern.

[0061] For example, the overlapping areas can be sorted from large to small according to the rule of overlapping area size, the overlapping areas corresponding to the target through-hole pattern can be sorted from large to small according to width, and the overlapping areas where the design through-hole pattern is located can be sorted from large to small according to width, and the through-hole patterns in the areas with the same sorting positions can be compared. The areas with the same sorting positions indicate that the width of the area where the design through-hole pattern is located is the same as the width of the area where the target through-hole pattern is located, so that the target through-hole pattern to be compared can be quickly searched.

[0062] When comparing the through-hole pattern in the same overlapping area with the corresponding target through-hole pattern, the through-hole pattern can be compared using, but not limited to, the XOR (exclusive OR) method. If the through-hole pattern in the overlapping area is different from the corresponding target through-hole pattern, it can be marked. Because the output of the XOR operation depends on whether the two input bits are different. If the two input bits are different, the output is 1; if the two input bits are the same, the output is 0. In the embodiment of the present application, only the design through-hole pattern with an output of 1 can be focused on, where 1 indicates that it is not the target through-hole pattern.

[0063] The principle of comparing the through-hole pattern (designed through-hole pattern) in the overlapping area with the target through-hole pattern corresponding to the overlapping area can be shown in Table 1.

[0064] Table 1

[0065]

[0066] The “ / ” in Table 1 means no comparison. Only the two areas marked with 1 need to be compared. If the design through-hole pattern is the same as the target through-hole pattern, mark 1 / 0. If the design through-hole pattern is different from the target through-hole pattern, mark 1 / 1 and report the position.

[0067] In another possible implementation, the process of detecting whether the through-hole pattern in the overlapping area is the target through-hole pattern may include: obtaining a blank area in the overlapping area that does not contain a through-hole, and determining whether the blank area can additionally set at least one through-hole in the overlapping area while meeting the circuit design requirements, obtaining a judgment result, and determining whether the through-hole pattern in the overlapping area is the target through-hole pattern according to the judgment result. In this implementation, it is not necessary to determine the target through-hole pattern corresponding to the overlapping area in advance, but by obtaining a blank area in the overlapping area that does not contain a through-hole, and determining whether the blank area can additionally set at least one through-hole in the overlapping area while meeting the circuit design requirements, if the judgment result indicates that the blank area can set at least one through-hole in the overlapping area, it is considered that the through-hole pattern in the overlapping area is not the target through-hole pattern, otherwise, it is the target through-hole pattern.

[0068] When determining whether additional through holes can be set in the blank area, the circuit design requirements need to be met, and the through hole style to be set needs to be the same as the through hole style already in the overlapping area, for example, the shape and size of the through hole need to be the same as the through hole style already in the overlapping area. In one embodiment, the circuit design requirements include the process characteristic requirements of the circuit design mentioned above, that is, the through holes to be set need to meet the process characteristic requirements of the circuit design mentioned above.

[0069] In a possible implementation manner, the power network wiring detection method may further include: when adjacent metal layers are not sufficiently connected, marking the adjacent metal layers that are not sufficiently connected to facilitate subsequent layout optimization thereof.

[0070] The detection method provided by the present application can comprehensively and quickly detect whether adjacent metal layers in the line network (PG net) where the power network is located are fully connected, which plays an important role in improving the performance of the chip and improving the yield rate of the chip. The detection method of the power network wiring provided in the embodiment of the present application can be applied to the chip design process and can be used as a supplement to PV (Physical Verification) verification.

[0071] The present application also provides a power network wiring detection device 100, such as Figure 4 As shown, the power network wiring detection device 100 includes: an acquisition module 110 and a detection module 120 .

[0072] The acquisition module 110 is used to determine the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located according to the graphic data system file of the chip.

[0073] The detection module 120 is used to detect whether the through-hole pattern in the overlapping area is the target through-hole pattern to determine whether the adjacent metal layers are fully connected; wherein, when the through-hole pattern in the overlapping area is the target through-hole pattern, it is determined that the adjacent metal layers are fully connected.

[0074] The acquisition module 110 is used to determine all metal layers of the line network where the target power network is located according to the graphic data system file of the chip; and obtain the overlapping area of ​​adjacent metal layers in all the metal layers.

[0075] The acquisition module 110 is used to determine the overlapping areas of each adjacent metal layer in the chip according to the graphic data system file of the chip; and find the overlapping areas of adjacent metal layers in the line network where the target power network is located from the overlapping areas of each adjacent metal layer.

[0076] The number of overlapping areas is multiple, corresponding to multiple target through-hole styles. The detection module 120 is used to sort the overlapping areas corresponding to the multiple target through-hole styles according to the size of the overlapping areas to obtain a first sorting result; sort the multiple overlapping areas according to the size of the overlapping areas to obtain a second sorting result; and compare the through-hole styles in the same sorting position in the first sorting result and the second sorting result.

[0077] The detection module 120 is used to obtain a blank area in the overlapping area that does not contain a through hole; under the condition that the circuit design requirements are met, determine whether the blank area can be additionally provided with at least one through hole in the overlapping area to obtain a determination result; and determine whether the through hole pattern in the overlapping area is a target through hole pattern based on the determination result.

[0078] The power network wiring detection device 100 further includes: a marking module, which is used to mark the adjacent metal layers that are not fully connected when the adjacent metal layers are not fully connected.

[0079] The power network wiring detection device 100 provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0080] like Figure 5 As shown, Figure 5 The electronic device 200 provided in the embodiment of the present application is shown in the structural block diagram. The electronic device 200 comprises: a transceiver 210, a memory 220, a communication bus 230 and a processor 240.

[0081] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, such as storing Figure 4 The software function module shown in is the detection device 100 for power network wiring. The detection device 100 for power network wiring includes at least one software function module that can be stored in the memory 220 in the form of software or firmware or solidified in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the executable module stored in the memory 220, such as the software function module or computer program included in the detection device 100 for power network wiring. For example, the processor 240 is used to execute the above-mentioned detection method for power network wiring.

[0082] Among them, the memory 220 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0083] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processor (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0084] The electronic device 200 mentioned above includes but is not limited to a tablet computer, a computer, a server, etc.

[0085] An embodiment of the present application also provides a non-volatile computer-readable storage medium (hereinafter referred to as storage medium), on which a computer program is stored. When the computer program is run by a computer such as the above-mentioned electronic device 200, the power network wiring detection method shown above is executed.

[0086] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0087] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0088] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0089] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a computer-readable storage medium, including several instructions for enabling a computer device (which can be a personal computer, a laptop, a server, or an electronic device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for detecting power network wiring, characterized in that: include: Determine the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located according to the graphic data system file of the chip; Detecting whether the via pattern in the overlapping area is a target via pattern to determine whether the adjacent metal layers are sufficiently connected; The target through-hole pattern is a through-hole pattern with the best power network connection performance corresponding to the overlapping area; when the through-hole pattern in the overlapping area is the target through-hole pattern, it is determined that the adjacent metal layers are fully connected.

2. The method according to claim 1, characterized in that According to the chip's graphic data system file, determine the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located, including: Determine all metal layers of the line network where the target power network is located according to the graphic data system file of the chip; Obtain overlapping areas of adjacent metal layers in all the metal layers.

3. The method according to claim 1, characterized in that According to the chip's graphic data system file, determine the overlapping area of ​​adjacent metal layers in the line network where the target power network in the chip is located, including: Determining overlapping areas of adjacent metal layers in the chip according to a graphic data system file of the chip; From the overlapping regions of each adjacent metal layer, the overlapping regions of adjacent metal layers in the line network where the target power network is located are found.

4. The method according to claim 1, characterized in that Detecting whether the through-hole pattern in the overlapping area is a target through-hole pattern includes: Obtaining a target through-hole pattern corresponding to the overlapping area, wherein the target through-hole pattern is determined according to the voltage drop and electromigration performance of the circuit and the process characteristic requirements of the circuit design; Comparing the through-hole pattern in the overlapping area with the target through-hole pattern corresponding to the overlapping area to obtain a comparison result; Determine whether the through-hole pattern in the overlapping area is a target through-hole pattern according to the comparison result.

5. The method according to claim 4, characterized in that The number of the overlapping regions is multiple and corresponds to multiple target through-hole patterns; comparing the through-hole patterns in the overlapping regions with the target through-hole patterns corresponding to the overlapping regions, including: Sorting the overlapping areas corresponding to the multiple target through-hole patterns according to the size of the overlapping areas to obtain a first sorting result; Sorting the multiple overlapping areas according to the size of the overlapping areas to obtain a second sorting result; The through-hole patterns at the same sorting position in the first sorting result and the second sorting result are compared.

6. The method according to claim 1, characterized in that Detecting whether the through-hole pattern in the overlapping area is a target through-hole pattern includes: Acquire a blank area in the overlapping area that does not contain a through hole; Under the condition that the circuit design requirements are met, determining whether the blank area can be additionally provided with at least one through hole in the overlapping area, and obtaining a determination result; It is determined whether the through-hole pattern in the overlapping area is a target through-hole pattern according to the judgment result.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: When the adjacent metal layers are not sufficiently connected, the adjacent metal layers that are not sufficiently connected are marked.

8. A detection device for power network wiring, characterized in that: include: An acquisition module, used for determining, according to a graphic data system file of the chip, an overlapping area of ​​adjacent metal layers in a line network where a target power network in the chip is located; A detection module, used to detect whether the through-hole pattern in the overlapping area is a target through-hole pattern, so as to determine whether the adjacent metal layers are sufficiently connected; The target through-hole pattern is a through-hole pattern with the best power network connection performance corresponding to the overlapping area; when the through-hole pattern in the overlapping area is the target through-hole pattern, it is determined that the adjacent metal layers are fully connected.

9. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is used to call the program stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is executed.

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