Optimization design method and device for chip simulation verification

Abstract

The invention provides an optimization design method and device for chip simulation verification, and the method comprises the steps: generating a candidate solution according to a current solution when a target chip is subjected to simulation verification, carrying out the simulated annealing calculation according to a preset algorithm cost function, the current solution and the candidate solution, judging whether to replace the current solution with the candidate solution or not, and carrying out the simulation verification of the target chip. Iterative calculation is carried out until an end condition is met, and an optimal constraint solution of the target chip is obtained; selecting at least one assertion in a preset assertion group, executing simulation according to the at least one assertion and the optimal constraint solution, and collecting coverage rate data of the external module; under the condition that it is determined that the collected coverage rate data does not reach the standard, the initial solution is adjusted according to the collected coverage rate data so as to optimize the obtained optimal constraint solution; at least one assertion selected in the assertion group is adjusted, simulation is executed again according to the at least one assertion after adjustment and the optimized optimal constraint solution, and coverage rate data of the external module after adjustment are collected until the coverage rate data reach the standard.

Description

Technical Field

[0001] The present invention relates to the technical field of chip simulation verification, and in particular to an optimization design method and device for chip simulation verification. Background Art

[0002] With the rapid development of semiconductor technology, the complexity and scale of chip design continue to increase, and the requirements for chip design verification are also increasing.

[0003] Before the actual manufacture of chips, designers need to use simulation tools and technologies to evaluate the performance and reliability of chips to ensure that the design meets the expected functions and performance indicators. Chip simulation verification is a key link in the chip design process, which involves the use of computer software, models and algorithms to simulate and analyze the accuracy and stability of chip circuit design.

[0004] Traditional chip simulation verification methods mainly rely on manually writing test cases or using automated tools to generate test data. These methods are effective when facing small-scale and simple chip designs, but as the design scale and complexity increase, these methods face the following challenges: It becomes extremely difficult to construct test cases that fully cover all possible execution paths, especially in complex control flows or data flows. Summary of the invention

[0005] The present invention provides an optimized design method and device for chip simulation verification, which is used to solve the defect that it is difficult to achieve comprehensive coverage of complex design paths and data flows in the prior art, resulting in possible blind spots in verification.

[0006] The present invention provides an optimization design method for chip simulation verification, comprising: In the process of simulating and verifying the target chip, a candidate solution is generated according to the current solution, and a simulated annealing calculation is performed according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, and the calculation is iterated until the end condition is met to obtain the optimal constraint solution of the target chip; Selecting at least one assertion in a preset assertion group, performing simulation according to the selected at least one assertion and the optimal constraint solution, and collecting coverage data of the external module; wherein the assertion has a corresponding binding relationship with the external module; When it is determined that the collected coverage data does not meet the standard, the initial solution is adjusted according to the collected coverage data to optimize the obtained optimal constraint solution; wherein the initial solution is the starting point for simulation verification of the target chip; At least one assertion selected from the assertion group is adjusted, simulation is re-executed according to the adjusted at least one assertion and the optimized optimal constraint solution, and coverage data of the adjusted external module is collected until the coverage data meets the standard.

[0007] According to an optimization design method for chip simulation verification provided by the present invention, a candidate solution is generated according to a current solution, and simulated annealing calculation is performed according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, and iterative calculation is performed until the end condition is met to obtain the optimal constraint solution of the target chip, which specifically includes: Based on the preset algorithm cost function and the current solution, calculating a function value corresponding to the current solution; Enable macro commands or call random built-in functions to randomly generate candidate solutions within the range of the current solution; Based on the preset algorithm cost function and the candidate solution, calculating a function value corresponding to the candidate solution; Compare the function value corresponding to the current solution and the function value corresponding to the candidate solution, and if the function value corresponding to the candidate solution is smaller than the function value corresponding to the current solution, replace the current solution with the candidate solution; If the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution, the reception probability corresponding to the candidate solution is calculated according to the function value corresponding to the candidate solution and the function value corresponding to the current solution, and a random number between 0 and 1 is generated. If the random number is less than the reception probability, the current solution is replaced by the candidate solution; if the random number is greater than or equal to the reception probability, the current solution is retained; Continue to iteratively execute the step of randomly generating candidate solutions within the range of the current solution until the end condition is met, and use the current solution obtained as the optimal constraint solution of the target chip, wherein the end condition includes: reaching a specified number of iterations, the current solution has not changed for multiple consecutive times, and the current solution reaches a set solution threshold.

[0008] According to an optimization design method for chip simulation verification provided by the present invention, the algorithm cost function is used to calculate the algorithm cost according to the code coverage rate achieved by the amount of data generated by the current solution, and the code coverage rate includes register flip coverage rate, digital design modeling code branch condition coverage rate, state machine state coverage rate and design modeling code line coverage rate; Based on the preset algorithm cost function and the current solution, the function value corresponding to the current solution is calculated, specifically including: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the amount of data generated by the current solution; calculating according to the hardware design path score covered by the current solution and the code coverage rate achieved by the amount of data generated by the current solution to obtain the function value corresponding to the current solution.

[0009] According to an optimization design method for chip simulation verification provided by the present invention, the reception probability corresponding to the candidate solution is calculated according to the function value corresponding to the candidate solution and the function value corresponding to the current solution, specifically including: determining the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; calculating according to the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter, to obtain the reception probability corresponding to the candidate solution.

[0010] According to an optimization design method for chip simulation verification provided by the present invention, simulation is performed according to the selected at least one assertion and the optimal constraint solution, and coverage data of the external module is collected, which specifically includes: performing simulation according to the selected at least one assertion and the optimal constraint solution, and collecting assertion results of the external module corresponding to the at least one assertion; wherein the assertions include external interface assertions, internal module assertions, bus assertions, memory assertions and fan-in resource assertions, and the external modules include chip modeling external signal modules, internal function modules, bus modules, memory modules and combinational logic modules; obtaining coverage data of the external modules according to the assertion results; wherein the coverage data includes at least one of code coverage, assertion coverage, scenario coverage and path coverage.

[0011] According to an optimization design method for chip simulation verification provided by the present invention, simulation is re-executed according to at least one adjusted assertion and the optimized optimal constraint solution, and coverage data of the adjusted external module is collected, which specifically includes: increasing the number of random simulations and random seeds, and re-executing simulation according to at least one adjusted assertion and the optimized optimal constraint solution, and collecting coverage data of the external module corresponding to the at least one adjusted assertion.

[0012] The present invention also provides an optimization design device for chip simulation verification, comprising: A simulated annealing calculation module is used to generate a candidate solution according to the current solution during the simulation verification of the target chip, and perform simulated annealing calculation according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterate the calculation until the end condition is met, and obtain the optimal constraint solution of the target chip; A coverage data collection module, used to select at least one assertion in a preset assertion group, perform simulation according to the selected at least one assertion and the optimal constraint solution, and collect coverage data of an external module; wherein the assertion has a corresponding binding relationship with the external module; An initial solution adjustment module, used to adjust the initial solution according to the collected coverage data to optimize the obtained optimal constraint solution when it is determined that the collected coverage data does not meet the standard; wherein the initial solution is the starting point for simulation verification of the target chip; The coverage data adjustment module is used to adjust at least one assertion selected in the assertion group, re-execute the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the standard.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, an optimization design method for chip simulation verification as described above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the optimization design method for chip simulation verification as described in any one of the above.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the optimized design method for chip simulation verification as described above is implemented.

[0016] The chip simulation and verification optimization design method and device provided by the present invention adopt a simulated annealing algorithm to automatically obtain the optimal constraint solution of the target chip, perform simulation according to at least one assertion and the optimal constraint solution, collect coverage data of external modules, and collect the coverage data of external modules through selected assertions. When it is determined that the collected coverage data does not meet the standard, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect the coverage data until the coverage data meets the standard, thereby using the optimal constraint solution obtained by the simulated annealing algorithm to influence subsequent simulation results, ensuring that the collected coverage data can fully cover all possible execution paths in the chip simulation and verification process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of a simulation verification platform provided by an embodiment of the present invention.

[0019] Figure 2 This is one of the flow charts of the chip simulation verification optimization design method provided by the embodiment of the present invention.

[0020] Figure 3 This is the second flow chart of the chip simulation verification optimization design method provided in the embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of an external coverage collection module of a simulation verification platform according to an embodiment of the present invention.

[0022] Figure 5 It is a flowchart of a method for collecting external coverage provided by an embodiment of the present invention.

[0023] Figure 6 It is a schematic diagram of the structure of the chip simulation verification optimization design device provided by an embodiment of the present invention.

[0024] Figure 7 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In addition to the technical defects mentioned in the background technology, the traditional technical solution also has the following technical defects: 1) It is difficult to collect coverage data in real time, especially during hardware simulation. This requires capturing and recording coverage data without interfering with the normal operation of chip modeling. In addition, the amount of data collected in real time is very large, requiring efficient storage and processing mechanisms.

[0027] 2) How to accurately measure coverage is another difficulty. In addition to code coverage (such as line coverage, branch coverage, etc.), other types of coverage need to be considered, such as functional coverage, scenario coverage, etc. These metrics need to be carefully designed to ensure that they can accurately reflect the verification status of the design.

[0028] In order to overcome the technical defects in the prior art that it is difficult to achieve comprehensive coverage of complex design paths and data flows, resulting in possible blind spots in verification, the embodiments of the present invention automatically obtain the optimal constraint solution of the target chip through a simulated annealing algorithm, and then collect the coverage data of the external module through assertions. When it is determined that the collected coverage data does not meet the standards, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect the coverage data until the coverage data meets the standards, thereby ensuring comprehensive coverage of the design paths and data flows.

[0029] Combine the following Figure 1-Figure 5 The optimized design method of chip simulation verification according to an embodiment of the present invention is described.

[0030] The method of the embodiment of the present invention can use SystemVerilog to model the behavior of the simulation platform based on the simulated annealing algorithm, realize an efficient verification platform that can converge quickly and collect in real time, and use SystemVerilog language to design and implement it. Based on the discussion of the logic principle, this design proposes the implementation principle, and uses SystemVerilog language to implement the platform logic, verifying the feasibility of the solution.

[0031] Among them, SystemVerilog is a hardware description and verification language based on the Verilog language. SystemVerilog combines concepts from Verilog, VHDL, C++, as well as verification platform language and assertion language, which improves the design modeling capabilities at a higher level of abstraction. It is mainly positioned in the chip implementation and verification process, integrating features such as object-oriented programming, dynamic threads and inter-thread communication. As an industrial standard language, SystemVerilog comprehensively integrates RTL design, test platforms, assertions and coverage, providing strong support for system-level design and verification.

[0032] Simulated Annealing (SA) is a heuristic random search algorithm, which is inspired by the annealing process in physics, especially the annealing process of solid materials (such as metals). The simulated annealing algorithm solves the optimization problem by simulating the process of solids being heated to a sufficient temperature and then gradually cooled. During the operation of the algorithm, the simulated annealing algorithm starts from a higher initial temperature. As the temperature gradually decreases, the algorithm randomly searches for the global optimal solution of the objective function in the solution space. At each temperature level, the algorithm repeats the iterative process of "generating a new solution → calculating the objective function difference → accepting or discarding". If the objective function value of the new solution is better, the new solution is accepted; otherwise, whether to accept the new solution is determined based on a certain probability, which is usually related to the relative size of the current temperature and the objective function difference.

[0033] The general steps of the search process of the simulated annealing algorithm (taking the maximization problem as an example) can be shown by the following simple flowchart: (1) Randomly generate a solution A, and calculate the objective function value f(A) corresponding to solution A.

[0034] (2) Randomly generate a solution B near solution A, and calculate the objective function value f(B) corresponding to solution B.

[0035] (3) If f(B) > f(A), then assign solution B to solution A, and then repeat the above steps, with the idea of iterative loop.

[0036] (4) If f(B) ≤ f(A), then calculate the probability of accepting solution B as P t =e -|f(xj) –f(xi)*Ct , and then generate a random number r between [0, 1]. If r < p, replace solution A with solution B, and repeat the above steps; otherwise, return to step (2), generate a random number A near the original solution A, and then perform step (3), and repeat the iteration.

[0037] Conditions for stopping iteration: reaching the specified number of iterations, reaching the threshold of the solution, and the solution remaining unchanged for multiple consecutive times.

[0038] Chip front-end verification is an important part of the chip design process, which mainly focuses on verifying whether the chip design meets the predetermined specifications and requirements.

[0039] Coverage collection is an essential and important part of the verification work. Coverage refers to the degree of coverage of the design or implementation in the verification work, and it can evaluate the effectiveness of the verification work by quantifying the progress of the verification and ensuring the completeness of the verification. The purpose of coverage collection is to understand the progress of the verification work and whether all design requirements and function points are covered.

[0040] Figure 1 The following shows a schematic diagram of the simulation verification platform involved in the embodiments of the present invention.

[0041] Among them, DUT (Device Under Test): the device under test, which refers to the chip to be tested in this embodiment. After connecting the DUT to the simulation verification platform, the simulation verification is then started.

[0042] driver: Requests a sequence_item (transaction) from the sequencer, and drives the information in the packet to the DUT port according to the bus protocol regulations (through the interface).

[0043] Sequencer: Coordinates the management of sequence and driver requests. When the driver requests data and the sequence sends a sequence_item request, it sends the sequence_item generated by the sequence to the driver.

[0044] Sequence (not part of the verification platform): Creates randomized transactions through the task body in the sequence, generates incentive content, and sends it to the sequencer.

[0045] monitor: Receives data (including input and output) from the DUT and converts it into transaction-level sequence_item, sends the input data to the reference model to generate the expected results, and sends the output data to the scoreboard for comparison.

[0046] Reference model: Use high-level language to simulate the functions of the DUT and generate expected results for the scoreboard to use as a judgment standard.

[0047] Scoreboard: Receives data from the reference model and monitor, and compares them to determine whether the DUT functions correctly.

[0048] Agent: Encapsulates driver, sequencer, and monitor together to improve code reusability. Agent comes with an enumeration parameter is_active (UVM_ACTIVE and UVM_PASSIVE modes) to control instantiated components. Agent-in and Agent-out correspond to

[0049] env: Encapsulates the components on the verification platform and configures the communication ports between the components to achieve the reusability of the verification environment. When running different test cases, you only need to instantiate env in them.

[0050] Verification platform such as Figure 1 As shown, UVM verifies randomness by generally enabling the uvm-do macro command or directly calling the random built-in function assert.tr.randomize() when calling the sequence component, and at the same time applying random constraints to it to obtain candidate solutions.

[0051] Figure 2 This is one of the flow charts of the chip simulation verification optimization design method provided by the present invention, such as Figure 2As shown, the method includes the following: Step 201: During the simulation verification of the target chip, a candidate solution is generated based on the current solution, and a simulated annealing calculation is performed based on a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution. The calculation is iterated until the end condition is met to obtain the optimal constraint solution of the target chip.

[0052] The optimal constraint solution is the solution with the lowest algorithm cost, that is, the solution can cover the critical path, and using this constraint solution, a higher code coverage can be achieved.

[0053] At the beginning, an initial solution is randomly generated or selected based on experience as the starting point for simulation verification. Then the current solution is evaluated using the preset algorithm cost function and its corresponding function value is calculated. This function value will be used for subsequent comparison with the candidate solution.

[0054] In the solution space of the current solution, a new candidate solution is generated through random perturbations or specific strategies. The function value of the candidate solution is calculated using the same algorithm cost function.

[0055] Then the function value of the current solution is compared with the function value of the candidate solution to determine whether to replace the current solution with the candidate solution. The temperature parameter is reduced according to the cooling scheme to prepare for the next round of iteration.

[0056] Determine whether the end condition is met, such as reaching the maximum number of iterations, not accepting new solutions for multiple consecutive times, or the quality of the solution reaches a preset threshold. If the end condition is not met, continue to generate new candidate solutions and evaluate them. When the end condition is met, the current solution is output as the optimal constraint solution, which is the optimal or approximately optimal solution found in the simulated annealing process. The optimal constraint solution obtained is used in the subsequent simulation verification steps to guide the generation and simulation process of test vectors.

[0057] Step 202: Select at least one assertion in a preset assertion group, perform simulation according to the selected at least one assertion and the optimal constraint solution, and collect coverage data of the external module; wherein the assertion has a corresponding binding relationship with the external module.

[0058] Assertion is a verification mechanism used in software engineering, hardware verification, and system design to ensure that the behavior of a program or system under specific conditions is as expected. During the verification process, the coverage of assertions can be used as an indicator to evaluate the comprehensiveness of verification.

[0059] It should be noted that the assertion group includes multiple assertions, each of which has a binding relationship with the corresponding external module. The assertions include external interface assertions, internal module assertions, bus assertions, memory assertions, and fan-in resource assertions. The external modules include chip modeling external signal modules, internal function modules, bus modules, memory modules, and combinational logic modules.

[0060] In the preset assertion group, at least one assertion is selected according to the characteristics of the optimal constraint solution. These assertions will be used to guide the verification of specific functions or paths during the simulation process.

[0061] The simulation process is performed using the optimal constraint solution as the initial condition of the simulation. During the simulation, the selected assertions are applied to check whether the behavior of the target chip is as expected.

[0062] During simulation, the results of each assertion are collected. This includes whether the assertion is satisfied, violated, or cannot be determined. Based on the assertion results, coverage data is generated. This data may include code coverage (such as line coverage, branch coverage, etc.), assertion coverage, scenario coverage, and path coverage.

[0063] Analyze the collected coverage data to determine whether the verification goals have been achieved. If the coverage data does not meet the target, it is necessary to identify the areas that are not covered or not fully tested.

[0064] If you find that some critical paths or functional points are not covered, you may need to adjust or add assertions to allow for more comprehensive testing in subsequent simulations. After adjusting the assertions, re-execute the simulation and collect coverage data again to verify that the adjustments are effective.

[0065] Through step 202, it can be ensured that the simulation verification is not only based on the optimal constraint solution, but also can comprehensively test and verify the design of the target chip, thereby improving the quality and efficiency of verification. This process helps to identify and fix possible problems and ensure that the chip design meets all predetermined specifications and requirements before going into production.

[0066] Step 203: When it is determined that the collected coverage data does not meet the standard, the initial solution is adjusted according to the collected coverage data to optimize the obtained optimal constraint solution.

[0067] The initial solution is the starting point for simulation verification of the target chip.

[0068] Review the collected coverage data and identify areas that do not meet the target, including uncovered or insufficiently covered lines of code, branches, state machine states, etc. Based on the coverage data, determine the initial solution parameters that need to be adjusted to improve the coverage of the areas that do not meet the target. Decide on the adjustment strategy, which may include modifying simulation parameters, changing input stimuli, optimizing the weights of the algorithm cost function, etc.

[0069] Adjusting the initial solution according to the strategy may involve modifying the test vectors, adjusting the simulation environment settings, or changing the starting conditions of the algorithm.

[0070] If the adjustment affects the simulation model or test bench, update the corresponding components to reflect the new initial solution. Recalculate the algorithm cost function using the updated initial solution to ensure that the adjusted solution still meets the cost-effectiveness requirements. Feed the adjusted initial solution back to the simulated annealing algorithm and restart the algorithm iteration process. Based on the new initial solution, continue to perform iterative calculations of the simulated annealing algorithm to find a better constraint solution.

[0071] By implementing step 203, it can be ensured that the simulation verification process can not only discover potential insufficient coverage problems, but also find solutions that meet all verification standards through an iterative optimization algorithm.

[0072] Step 204: adjust at least one assertion selected in the assertion group, re-execute simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collect coverage data of the adjusted external module until the coverage data meets the standard.

[0073] Integrate the modified assertions into the simulation environment and ensure that all dependent components and bindings are updated.

[0074] To explore the solution space more comprehensively, you may need to increase the number of random simulations and change the random seed to generate more diverse test vectors. Re-execute the simulation process using the updated assertions and simulation environment.

[0075] After re-running the simulation, new coverage data is collected and analyzed to check whether the predetermined coverage standard has been achieved.

[0076] If the coverage data still does not fully meet the requirements, the process of step 204 is repeated to continue adjusting the assertion and simulation parameters.

[0077] Through an iterative process, optimize the assertion set to achieve more comprehensive coverage while reducing redundant or unnecessary assertions. While adjusting assertions, monitor the performance of the simulation to ensure that the addition of assertions does not negatively impact simulation efficiency.

[0078] By implementing step 204, it can be ensured that the simulation verification process can be adaptively adjusted to achieve the goal of comprehensive coverage, thereby improving the verification quality and reliability of the chip design.

[0079] The chip simulation and verification optimization design method provided by the embodiment of the present invention adopts a simulated annealing algorithm to automatically obtain the optimal constraint solution of the target chip, performs simulation according to at least one assertion and the optimal constraint solution, collects coverage data of external modules, and collects the coverage data of external modules through selected assertions. When it is determined that the collected coverage data does not meet the standard, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect the coverage data until the coverage data meets the standard, thereby using the optimal constraint solution obtained by the simulated annealing algorithm to influence subsequent simulation results, ensuring that the collected coverage data can fully cover all possible execution paths in the chip simulation and verification process.

[0080] See also Figure 3 In step 201, the simulated annealing algorithm is used to obtain the optimal constraint solution of the target chip, which specifically includes: 300. Initialization phase: Set various parameters, input various parameters for algorithm modeling, solution space of simulation constraints, initial value of design path, median coverage parameters of constraint solution space, initial test temperature, annealing coefficient, and initial solution.

[0081] 301. Based on the preset algorithm cost function and the current solution, calculate a function value corresponding to the current solution.

[0082] Among them, step 301 includes: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the amount of data generated by the current solution; calculating according to the hardware design path score covered by the current solution and the code coverage rate achieved by the amount of data generated by the current solution to obtain the function value corresponding to the current solution.

[0083] Among them, code coverage includes register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage; Register flip coverage: measures the coverage of register state changes during simulation.

[0084] Digital Design Modeling Code Branch Condition Coverage: Measures the coverage of different branch paths in simulation.

[0085] State machine state coverage: measures the coverage of each state of the state machine.

[0086] Design modeling code line coverage: measures whether each line of code in the code is executed.

[0087] Specifically, the calculation of code coverage is as follows: (1)

[0088] Among them, f(x) is the algorithm cost calculation, the lower the cost, the better the verification effect; c(x) is the score of the covered hardware design paths; is the code coverage achieved by the amount of data generated by the constraints, 0~ 3 is the weight of each coverage; is the register flip coverage; Digital design modeling code branch condition coverage, is the state coverage of the state machine, Design modeling code line coverage; Fixed parameter for cost calculation, configurable, default is 1.

[0089] Analyze the correlation between the amount of data generated by the current solution and various code coverage indicators to determine their impact on the algorithm cost. Combine the hardware design path score and code coverage, and use the algorithm cost function to calculate the function value of the current solution. Analyze the calculated function value to evaluate the pros and cons of the current solution. The lower the function value, the lower the algorithm cost of the current solution and the higher the coverage.

[0090] According to the evaluation results of the function value, adjust the algorithm parameters, such as simulation input, constraints, etc., to optimize the algorithm performance.

[0091] 302. Activate a macro command or call a random built-in function to randomly generate candidate solutions within the range of the current solution.

[0092] In this step, enable the uvm-do macro command or directly call the random built-in function assert.tr.randomize() to randomly generate candidate solutions within the range of the current solution.

[0093] The range of the current solution can be a preset range. For example, the goal of a task is to find the minimum value in a certain interval [0, 100], and the current solution is x=50. A fixed range can be set, such as ±5, so that candidate solutions will be randomly generated between 45 and 55.

[0094] 303. Based on the preset algorithm cost function and the candidate solution, calculate a function value corresponding to the candidate solution.

[0095] Among them, step 303 includes: obtaining the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the candidate solution; calculating according to the hardware design path score covered by the current solution and the code coverage rate achieved by the data volume generated by the candidate solution to obtain the function value corresponding to the candidate solution.

[0096] The calculation method of the candidate solution is the same as that of the current solution, and will not be described in detail here.

[0097] 304. Compare the function value corresponding to the current solution and the function value corresponding to the candidate solution.

[0098] 305. If the function value corresponding to the candidate solution is smaller than the function value corresponding to the current solution, replace the current solution with the candidate solution.

[0099] 306. If the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution, calculate the reception probability corresponding to the candidate solution based on the function value corresponding to the candidate solution and the function value corresponding to the current solution, and generate a random number between 0 and 1. If the random number is less than the reception probability, replace the current solution with the candidate solution; if the random number is greater than or equal to the reception probability, retain the current solution.

[0100] In step 306, the reception probability corresponding to the candidate solution is calculated according to the function value corresponding to the candidate solution and the function value corresponding to the current solution, which specifically includes: determining the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; calculating according to the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter to obtain the reception probability corresponding to the candidate solution.

[0101] Specifically, see the following formula (2):

[0102] (2)

[0103] in, is the last temperature parameter,

[0104] P is the probability of receiving; is the cooling factor, i.e., the decreasing coefficient, which is used to improve the search efficiency and reduce the algorithm time. It can be set to 0.95 or 0.99, and is designed according to the acceptable number of iterations of the simulation platform; T is the initial temperature, which can be set to 100; f(B) and f(A) are the function values ​​corresponding to the candidate solution and the current solution respectively.

[0105] 307 . Continue to iteratively execute the step of randomly generating candidate solutions within the range of the current solution until an end condition is met, and use the obtained current solution as the optimal constraint solution of the target chip.

[0106] The termination conditions include: reaching a specified number of iterations, the current solution not changing for multiple consecutive times, and the current solution reaching a set solution threshold.

[0107] Within the scope of the current solution, new candidate solutions are continuously generated using macro commands or random built-in functions. This step is the core of the algorithm to explore the solution space.

[0108] For each newly generated candidate solution, use the preset algorithm cost function to calculate its corresponding function value and compare it with the function value of the current solution. If the function value of the candidate solution is better than the current solution, accept the candidate solution as the new current solution; if the function value of the candidate solution is not better than the current solution, calculate the acceptance probability and generate a random number in the range of [0,1] to decide whether to accept the candidate solution based on the probability.

[0109] According to the cooling scheme, the current temperature parameter is updated. The temperature parameter usually decreases gradually with the increase of the number of iterations.

[0110] At the end of each iteration, check whether the end condition is met, and record the current solution, candidate solution, function value and temperature parameter of each iteration to analyze the convergence of the algorithm and the search efficiency.

[0111] Moreover, during the iteration process, the convergence of the algorithm is monitored to ensure that the algorithm can find the optimal or approximately optimal solution within a reasonable number of iterations.

[0112] Through the iterative process, the algorithm continuously explores the solution space, trying to jump out of the local optimal solution and find the global optimal solution.

[0113] Through steps 300-307, it is possible to ensure that the simulated annealing algorithm systematically explores the solution space in the process of finding the optimal constraint solution, while effectively balancing exploration and utilization, and ultimately achieving algorithm convergence and determination of the optimal solution. This process helps to improve the quality and efficiency of chip simulation verification and ensure that the design meets the expected functions and performance indicators.

[0114] Specifically, see Figure 4 , Figure 4 The figure shows a schematic diagram of the external coverage collection module of the simulation verification platform described in this embodiment. The coverage is collected in an assertion manner; the core is the assertion part and the internal module mapping part; the interface of the assertion group is linked to the internal mapping module group in a bind manner.

[0115] The assertions include external interface assertions, internal module assertions, bus assertions, memory assertions and fan-in resource assertions, and the external modules include chip modeling external signal modules, internal function modules, bus modules, memory modules and combinational logic modules.

[0116] Specifically, External Interface Assertions: These assertions are used to verify that the interface between the chip and the external system interacts correctly according to the predetermined protocol. If the chip has an SPI interface for data transmission, assertions can be set to check whether the SPI clock and data signals are synchronized.

[0117] Internal Module Assertions: Used to check whether the functions of various modules inside the chip are working properly, such as processing units, arithmetic logic units, etc. Set assertions for the multiplication module of a processor to ensure that all multiplication operations are completed within the expected time.

[0118] Bus Assertions: These assertions are used to verify that data transfer on the chip's internal buses is correct, including the address bus and the data bus. Assertions are set on the system bus to ensure that no bus conflicts or incorrect data transfers occur.

[0119] Memory Assertions: Used to ensure the correctness of memory read and write operations, including cache consistency and memory access permissions. Set assertions on the chip's on-chip memory to check whether the memory write and read operations conform to the expected data pattern.

[0120] Fan-in Resource Assertions: These assertions are used to verify the effect of multiple input signals on a single logic cell, ensuring that the logic cell can handle multiple inputs correctly. Setting assertions on a logic gate with multiple inputs ensures that the output meets the logic function under all possible input combinations.

[0121] Specifically, the design method workflow is as follows: First, through the modeling process and algorithm execution process described in the previous paragraph of this article, the algorithm calculates the optimal constraint solution of the target chip. Figure 4 The assertion group and bind link of the module shown are used to select the assertion, and then the simulation step is started. After the simulation is completed, the assertion results are collected, and the coverage data of each item is obtained through the EDA tool. Part of the coverage collection is fed back to the algorithm calculation step to change the initial value to achieve the purpose of optimizing the solution, and part of it is fed back to the assertion selection to update the modules in the assertion group and the modules in the mapping group for the uncovered modules. At the same time, it is determined whether the overall coverage meets the standard. If not, the random simulation times and random seeds are increased, and the simulation step is re-entered until the coverage meets the standard.

[0122] For the specific process, see Figure 5, wherein correspondingly, step 202 specifically includes: selecting at least one assertion in a preset assertion group, performing simulation according to the selected at least one assertion and the optimal constraint solution, collecting assertion results of the external module corresponding to the at least one assertion; and obtaining coverage data of the external module according to the assertion results.

[0123] The coverage data includes at least one of code coverage, assertion coverage, scenario coverage, and path coverage.

[0124] Step 204 specifically includes: increasing the number of random simulations and the random seed, and re-executing the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collecting coverage data of the external module corresponding to the adjusted at least one assertion.

[0125] The method of the embodiment of the present invention further achieves the following technical effects: 1) Using the simulated annealing algorithm, the random constraints of the verification platform are intelligently selected to cover the design paths and data flows, select the optimal path and data flow, reduce manpower and material resources consumption, and improve efficiency.

[0126] 2) Through the external coverage collection module, the coverage is collected in real time without interfering with the chip, and the collected data is stored in external storage.

[0127] 3) Code coverage in the prior art is measured by dedicated EDA tools, such as VCS, URG, etc. However, there are many types of coverage, such as functional coverage and scenario coverage. Due to the large differences between different chip projects, there is no unified EDA or method for measurement. The method of this embodiment uses the results of the simulated annealing algorithm and combines the principles of functional and scenario verification to perform coverage statistics.

[0128] The following is a description of an optimized design device for chip simulation verification provided by an embodiment of the present invention. The optimized design device for chip simulation verification described below and the optimized design method for chip simulation verification described above can be referenced to each other.

[0129] The embodiment of the present invention provides an optimized design device for chip simulation verification, see Figure 6 ,include: The simulated annealing calculation module 601 is used to generate a candidate solution according to the current solution during the simulation verification of the target chip, and perform simulated annealing calculation according to the preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterate the calculation until the end condition is met, and obtain the optimal constraint solution of the target chip; A coverage data collection module 602 is used to select at least one assertion in a preset assertion group, perform simulation according to the selected at least one assertion and the optimal constraint solution, and collect coverage data of an external module; wherein the assertion has a corresponding binding relationship with the external module; The initial solution adjustment module 603 is used to adjust the initial solution according to the collected coverage data to optimize the obtained optimal constraint solution when it is determined that the collected coverage data does not meet the standard; wherein the initial solution is the starting point for simulation verification of the target chip; The coverage data adjustment module 604 is used to adjust at least one assertion selected in the assertion group, re-execute the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the standard.

[0130] Optionally, the simulated annealing calculation module 601 is specifically used to: calculate the function value corresponding to the current solution based on the preset algorithm cost function and the current solution; enable macro commands or call random embedded functions to randomly generate candidate solutions within the range of the current solution; calculate the function value corresponding to the candidate solution based on the preset algorithm cost function and the candidate solution; compare the function value corresponding to the current solution with the function value corresponding to the candidate solution, if the function value corresponding to the candidate solution is less than the function value corresponding to the current solution, replace the current solution with the candidate solution; if the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution , calculate the reception probability corresponding to the candidate solution according to the function value corresponding to the candidate solution and the function value corresponding to the current solution, and generate a random number between 0 and 1, if the random number is less than the reception probability, replace the current solution with the candidate solution; if the random number is greater than or equal to the reception probability, retain the current solution; continue to iterate and execute the step of randomly generating candidate solutions within the range of the current solution until the end condition is met, and use the obtained current solution as the optimal constraint solution of the target chip, wherein the end condition includes: reaching a specified number of iterations, the current solution has not changed for multiple consecutive times, and the current solution reaches a set solution threshold.

[0131] Optionally, the algorithm cost function is used to calculate the algorithm cost according to the code coverage achieved by the amount of data generated by the current solution, the code coverage including register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage; The simulated annealing calculation module 601 is specifically used to: obtain the hardware design path score covered by the current solution and the code coverage rate achieved by the amount of data generated by the current solution; calculate according to the hardware design path score covered by the current solution and the code coverage rate achieved by the amount of data generated by the current solution to obtain the function value corresponding to the current solution.

[0132] Optionally, the simulated annealing calculation module 601 is specifically used to: determine the current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; calculate according to the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter to obtain the reception probability corresponding to the candidate solution.

[0133] Optionally, the coverage data collection module 602 is specifically used to: perform simulation according to the selected at least one assertion and the optimal constraint solution, and collect assertion results of the external module corresponding to the at least one assertion; wherein the assertions include external interface assertions, internal module assertions, bus assertions, memory assertions and fan-in resource assertions, and the external modules include chip modeling external signal modules, internal function modules, bus modules, memory modules and combinational logic modules; obtain coverage data of the external modules according to the assertion results; wherein the coverage data includes at least one of code coverage, assertion coverage, scenario coverage and path coverage.

[0134] Optionally, the coverage data adjustment module 604 is specifically used to: increase the number of random simulations and random seeds, re-execute the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collect coverage data of the external module corresponding to the adjusted at least one assertion.

[0135] The chip simulation and verification optimization design device provided by the embodiment of the present invention adopts a simulated annealing algorithm to automatically obtain the optimal constraint solution of the target chip, performs simulation according to at least one assertion and the optimal constraint solution, collects coverage data of external modules, and collects the coverage data of external modules through selected assertions. When it is determined that the collected coverage data does not meet the standard, the initial solution and the selected assertions are adjusted to re-execute the simulation to collect the coverage data until the coverage data meets the standard, thereby using the optimal constraint solution obtained by the simulated annealing algorithm to influence subsequent simulation results, ensuring that the collected coverage data can fully cover all possible execution paths in the chip simulation and verification process.

[0136] Figure 7 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 7As shown, the electronic device may include: a processor (processor) 710 , a communication interface (Communications Interface) 720 , a memory (memory) 730 and a communication bus 740 , wherein the processor 710 , the communication interface 720 , and the memory 730 communicate with each other through the communication bus 740 . The processor 710 can call the logic instructions in the memory 730 to execute the optimization design method for chip simulation verification, including: in the process of simulating and verifying the target chip, generating a candidate solution according to the current solution, and performing simulated annealing calculation according to the preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterating the calculation until the end condition is met, and obtaining the optimal constraint solution of the target chip; selecting at least one assertion in the preset assertion group, performing simulation according to the selected at least one assertion and the optimal constraint solution, and collecting coverage data of the external module; wherein the assertion has a corresponding binding relationship with the external module; when it is determined that the collected coverage data does not meet the standard, adjusting the initial solution according to the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected in the assertion group, re-executing the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collecting the adjusted coverage data of the external module until the coverage data meets the standard.

[0137] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0138] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the chip simulation verification optimization design method provided by the above methods, including: in the process of simulating and verifying the target chip, generating a candidate solution according to the current solution, and performing simulated annealing calculation according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterating the calculation until the end condition is met, and obtaining the optimal constraint solution of the target chip; selecting at least one assertion in a preset assertion group, performing simulation according to the selected at least one assertion and the optimal constraint solution, and collecting coverage data of an external module; wherein the assertion has a corresponding binding relationship with the external module; when it is determined that the collected coverage data does not meet the standard, adjusting the initial solution according to the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected in the assertion group, re-executing the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collecting the adjusted coverage data of the external module until the coverage data meets the standard.

[0139] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements an optimization design method for chip simulation verification provided by the above methods, including: in the process of simulating and verifying a target chip, generating a candidate solution according to a current solution, and performing simulated annealing calculation according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterating the calculation until an end condition is met, and obtaining an optimal constraint solution for the target chip; selecting at least one assertion in a preset assertion group, performing simulation according to the selected at least one assertion and the optimal constraint solution, and collecting coverage data of an external module; wherein the assertion has a corresponding binding relationship with the external module; when it is determined that the collected coverage data does not meet the standard, adjusting the initial solution according to the collected coverage data to optimize the obtained optimal constraint solution; adjusting at least one assertion selected in the assertion group, re-executing the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collecting the adjusted coverage data of the external module until the coverage data meets the standard.

[0140] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0141] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip simulation verification optimization design method, characterized in that: include: In the process of simulating and verifying the target chip, a candidate solution is generated according to the current solution, and a simulated annealing calculation is performed according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, and the calculation is iterated until the end condition is met to obtain the optimal constraint solution of the target chip; Selecting at least one assertion in a preset assertion group, performing simulation according to the selected at least one assertion and the optimal constraint solution, and collecting coverage data of the external module; wherein the assertion has a corresponding binding relationship with the external module; When it is determined that the collected coverage data does not meet the standard, the initial solution is adjusted according to the collected coverage data to optimize the obtained optimal constraint solution; wherein the initial solution is the starting point for simulation verification of the target chip; At least one assertion selected from the assertion group is adjusted, simulation is re-executed according to the adjusted at least one assertion and the optimized optimal constraint solution, and coverage data of the adjusted external module is collected until the coverage data meets the standard.

2. The chip simulation and verification optimization design method according to claim 1, characterized in that: Generate a candidate solution according to the current solution, and perform simulated annealing calculation according to the preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterate the calculation until the end condition is met, and obtain the optimal constraint solution of the target chip, specifically including: Based on the preset algorithm cost function and the current solution, calculating a function value corresponding to the current solution; Enable a macro command or call a random built-in function to randomly generate candidate solutions within the range of the current solution; Based on the preset algorithm cost function and the candidate solution, calculating a function value corresponding to the candidate solution; Compare the function value corresponding to the current solution and the function value corresponding to the candidate solution, and if the function value corresponding to the candidate solution is smaller than the function value corresponding to the current solution, replace the current solution with the candidate solution; If the function value corresponding to the candidate solution is greater than or equal to the function value corresponding to the current solution, the reception probability corresponding to the candidate solution is calculated according to the function value corresponding to the candidate solution and the function value corresponding to the current solution, and a random number between 0 and 1 is generated. If the random number is less than the reception probability, the current solution is replaced by the candidate solution; if the random number is greater than or equal to the reception probability, the current solution is retained; Continue to iteratively execute the step of randomly generating candidate solutions within the range of the current solution until the end condition is met, and use the current solution obtained as the optimal constraint solution of the target chip, wherein the end condition includes: reaching a specified number of iterations, the current solution has not changed for multiple consecutive times, and the current solution reaches a set solution threshold.

3. The chip simulation and verification optimization design method according to claim 2, characterized in that: The algorithm cost function is used to calculate the algorithm cost according to the code coverage achieved by the amount of data generated by the current solution, wherein the code coverage includes register flip coverage, digital design modeling code branch condition coverage, state machine state coverage, and design modeling code line coverage; Based on the preset algorithm cost function and the current solution, calculating a function value corresponding to the current solution specifically includes: Obtaining a hardware design path score covered by the current solution and a code coverage rate achieved by the amount of data generated by the current solution; The function value corresponding to the current solution is obtained by calculating the code coverage rate achieved by the hardware design path score covered by the current solution and the amount of data generated by the current solution.

4. The chip simulation and verification optimization design method according to claim 2, characterized in that: Calculating the reception probability corresponding to the candidate solution according to the function value corresponding to the candidate solution and the function value corresponding to the current solution specifically includes: Determine a current temperature parameter, wherein the current temperature parameter is obtained by multiplying the previous temperature parameter by a decreasing coefficient; The reception probability corresponding to the candidate solution is obtained by performing calculation based on the difference between the function value corresponding to the candidate solution and the function value corresponding to the current solution, and the current temperature parameter.

5. The chip simulation and verification optimization design method according to claim 1, characterized in that: Performing simulation according to the selected at least one assertion and the optimal constraint solution to collect coverage data of the external module specifically includes: Perform simulation according to the selected at least one assertion and the optimal constraint solution, and collect assertion results of the external module corresponding to the at least one assertion; wherein the assertion includes external interface assertions, internal module assertions, bus assertions, memory assertions, and fan-in resource assertions, and the external module includes a chip modeling external signal module, an internal function module, a bus module, a memory module, and a combinational logic module; The coverage data of the external module is obtained according to the assertion result; wherein the coverage data includes at least one of code coverage, assertion coverage, scenario coverage and path coverage.

6. The chip simulation and verification optimization design method according to claim 1, characterized in that: Re-executing simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collecting adjusted coverage data of the external module, specifically includes: The number of random simulations and the random seed are increased, and the simulation is re-executed according to the adjusted at least one assertion and the optimized optimal constraint solution, and the coverage data of the external module corresponding to the adjusted at least one assertion is collected.

7. An optimization design device for chip simulation verification, characterized in that: include: A simulated annealing calculation module is used to generate a candidate solution according to the current solution during the simulation verification of the target chip, and perform simulated annealing calculation according to a preset algorithm cost function, the current solution and the candidate solution to determine whether to replace the current solution with the candidate solution, iterate the calculation until the end condition is met, and obtain the optimal constraint solution of the target chip; A coverage data collection module, configured to select at least one assertion in a preset assertion group, perform simulation according to the selected at least one assertion and the optimal constraint solution, and collect coverage data of an external module; wherein the assertion has a corresponding binding relationship with the external module; An initial solution adjustment module, used to adjust the initial solution according to the collected coverage data to optimize the obtained optimal constraint solution when it is determined that the collected coverage data does not meet the standard; wherein the initial solution is the starting point for simulation verification of the target chip; The coverage data adjustment module is used to adjust at least one assertion selected in the assertion group, re-execute the simulation according to the adjusted at least one assertion and the optimized optimal constraint solution, and collect the adjusted coverage data of the external module until the coverage data meets the standard.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the optimized design method for chip simulation verification as claimed in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the optimized design method for chip simulation verification as claimed in any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the optimized design method for chip simulation verification as claimed in any one of claims 1 to 6 is implemented.

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