Method for optimizing reserve pool network performance based on full flash memory

Abstract

The invention relates to the technical field of reserve pool networks, in particular to a method for optimizing the performance of a reserve pool network based on a full flash memory, and the method comprises the steps: constructing an input layer, a mask layer, a reserve pool layer and an output layer of the reserve pool network through the flash memory; a programming erasure voltage is applied to a grid electrode of a storage pool layer flash memory, the programming erasure voltage enables a defect to be generated in the flash memory, the defect causes charge trapping / de-trapping, during charge trapping, the output current of the flash memory is reduced, and during charge de-trapping, the output current of the flash memory is increased to a value before the programming erasure voltage is applied. The short-term memory characteristics of the reservoir network are achieved using current manifestation during charge trapping / de-trapping. According to the invention, the flash memory is adopted to form the reserve pool network, and the accurate control of the device characteristics is realized through the pressurization processing of the flash memory device of the reserve pool layer, so that the calculation power consumption of the reserve pool network is effectively reduced, and the performance optimization of the calculation system is realized under the condition that the device unit does not need to be reconstructed.

Description

Technical Field

[0001] The present invention relates to the field of reserve pools, and in particular to a method for reducing reserve pool consolidation based on all-flash memory. Background Art

[0002] In recent years, reservoir computing, as an emerging computing paradigm that mimics the way the human brain processes information, has attracted widespread attention. Reservoir computing achieves parallel processing and distributed representation of information by constructing a reservoir network containing a large number of neurons to improve the intelligence and adaptability of computing systems. The idea behind reservoir computing is to simulate the reservoir in the brain and to achieve rapid processing and learning of complex information by introducing dynamic reservoir units with short-term memory characteristics into the network. Compared with traditional computing models, reservoir computing is more biologically inspired and can better cope with the challenges of real-time, nonlinear, and multimodal information processing.

[0003] However, traditional reserve pool computing solutions have certain problems in terms of power consumption and reliability. Most of the current reserve pool computing solutions use new types of memory, whose reliability and uniformity are difficult to meet actual application needs. In addition, the devices used for reserve pool computing have a long response time, and excessively long calculations will greatly increase device power consumption. Summary of the invention

[0004] In view of the defects of the prior art, the present invention provides a method for optimizing the network performance of a reserve pool based on all-flash memory, aiming to reduce the power consumption of the reserve pool computing system and avoid reconstruction of traditional flash memory device units.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a method for optimizing the network performance of a reserve pool based on all-flash memory, the method comprising: Use flash memory to build the input layer, mask layer, reservoir layer, and output layer of the reservoir network; A programming and erasing voltage is applied to the gate of the reserve pool layer flash memory. The programming and erasing voltage generates defects inside the flash memory. The defects cause charge capture / de-trapping. When charge is captured, the output current of the flash memory decreases. When charge is de-trapped, the output current of the flash memory increases to the value before the programming and erasing voltage is applied. The current performance during charge capture / de-trapping is used to realize the short-term memory characteristics of the reserve pool network.

[0006] Furthermore, the programming voltage is 8-10V for the gate and 4.2V for the source, and the duration is an integer multiple of 10us. The erasing voltage is -8V for the gate and 4.2V for the drain, and the duration is 100us to 1s. When the programming voltage is applied, charge de-trapping is achieved, and when the erasing voltage is applied, charge trapping is achieved.

[0007] Furthermore, the gate programming voltage is a plurality of 10V pulses with a duration of 10us, and the gate erasing voltage is a -10V pulse with a duration of 0.1s.

[0008] Furthermore, the time for charge trapping / de-trapping is called relaxation time, and controllable relaxation time is introduced by controlling the application time of programming and erasing voltages.

[0009] Furthermore, the longer the programming and erasing voltage is applied, the shorter the relaxation time is.

[0010] Furthermore, when the reservoir network is working, the time step of the input pulse is smaller than the relaxation time.

[0011] Furthermore, the output layer of the reserve pool linearly combines the reserve states of the reserve pool layers, and the weight of the combination is optimized by linear regression.

[0012] Furthermore, 55nm NOR flash memory cells are used to construct the input layer, mask layer, reservoir layer and output end of the reservoir network.

[0013] Furthermore, 55nm NOR flash memory cells are arranged in parallel.

[0014] The present invention has the following advantages: the present invention uses flash memory to form a reserve pool network, and realizes precise control of device characteristics by pressurizing the flash memory devices in the reserve pool layer, and utilizes the characteristics of defect capture / de-capture, thereby realizing the short-term memory characteristics required by the reserve pool network. This feature greatly reduces the duration of reserve calculations, and the architecture does not change relative to the original architecture of the flash memory unit. The reduced calculation time effectively reduces the computational power consumption of the reserve pool network constructed compared to other storage units, and at the same time achieves performance optimization of the computing system without the need for device unit reconstruction. At the same time, the controllable relaxation time and the multiplication and addition operations realized by flash memory further improve the flexibility and computing efficiency of the system. Since flash memory has a lower operating current than existing ferroelectric devices, it can greatly reduce the power consumption during the calculation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the network structure of the all-flash storage pool; Figure 2 It is a schematic diagram of the charge capture characteristics of the flash memory unit after pressurization in the present invention; Figure 3 It is the working pressurization mode of the reservoir layer in the present invention; Figure 4 It is a statistical diagram of the measured intra-device fluctuation and inter-device fluctuation in the present invention; Figure 5 It is the current response after applying different P / E cycle numbers and pulse times to the flash memory devices in the reserve pool; Figure 6 is the regulation capability and retention characteristics of the flash memory devices in the output layer; Figure 7 It is a schematic diagram of the reserve pool calculation process; Figure 8 It is a schematic diagram of the prediction results of the reserve pool network timing signal in the present invention. DETAILED DESCRIPTION

[0016] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0017] Example 1 This embodiment discloses a method for reducing power consumption of a storage pool based on all-flash memory, such as Figure 1 As shown, the method uses 55nm NOR flash memory cells to construct the input layer, mask layer, reservoir layer and output layer of the reservoir network. The 55nm NOR flash memory cells have the nonlinear delay feedback function of flash memory (obtained by pressurizing the flash memory), while the output layer is implemented by flash memory cells with high reliability (i.e., original flash memory cells that have not been pressurized), which requires fine threshold adjustment and long-term retention characteristics. This function is completed by the high reliability of the flash memory itself. The nonlinear characteristics of the flash memory cells in the reservoir layer enable the input signal to be mapped to a high-dimensional space, simplifying the data processing of the output layer. Due to the historical dependence and nonlinear dynamic characteristics of the flash memory cells in the reservoir layer, only the output layer needs to be trained, which can significantly reduce the training cost and time. In addition, the traditional flash memory NOR type parallel arrangement method is used to process the input signal and generate a dynamic output current response without modifying the original array connection of the NOR flash memory.

[0018] The nonlinear delay feedback function of the flash memory mentioned above is obtained by pressurizing the flash memory. The specific implementation process is as follows: A programming and erasing voltage is applied to the gate of the reserve pool layer flash memory, and the programming and erasing voltage is set to a level that can cause defects to be generated inside the flash memory and thus cause charge capture / de-capture. Figure 2As shown, applying a programming and erasing voltage generates defects inside the flash memory, and the defects cause charge capture / decapture. When the charge is captured, the output current of the flash memory decreases. When the charge is decaptured, the output current of the flash memory increases to the value before the programming and erasing voltage is applied. The current performance during charge capture / decapture is used to realize the short-term memory characteristics of the reserve pool network. The short-term memory characteristics of the reserve pool network are that if multiple pulses are applied in a short time interval, the state of the unit will change significantly (corresponding to the decrease in the output current of the flash memory unit). In a long time interval, the absence of an input signal will cause state decay, that is, the unit will return to the initial state before any pulse is applied (corresponding to the increase in the output current of the flash memory unit), which is consistent with the current performance brought about by the electron capture / decapture process. This method reduces the duration of the reserve calculation and the architecture does not change relative to the original architecture of the flash memory unit. The reduced calculation time effectively reduces the calculation power consumption of the reserve pool network constructed compared to other storage units, and at the same time achieves the performance optimization of the computing system without the need to reconstruct the device unit.

[0019] In this embodiment, the programming voltage is 8-10V for the gate, 4.2V for the source, and the duration is an integer multiple of 10us. The erasing voltage is -8V for the gate, 4.2V for the drain, and the duration is 100us to 1s. When the programming voltage is applied, charge de-trapping is achieved, and when the erasing voltage is applied, charge trapping is achieved. Specifically, the gate programming voltage is a plurality of 10V pulses with a duration of 10us, and the gate erasing voltage is a -10V pulse with a duration of 0.1s.

[0020] The time for charge capture / de-capture is called relaxation time, and controllable relaxation time is introduced by controlling the application time of the program erase voltage. Specifically, the longer the program erase voltage is applied, the shorter the relaxation time. This embodiment realizes the flexible application of the reservoir network at different time scales by introducing controllable relaxation time. This helps to adapt to various computing needs and improve the flexibility and applicability of the system.

[0021] When the reservoir network is working, the time step of the input pulse is smaller than the relaxation time.

[0022] In this embodiment, the output layer of the reserve pool linearly combines the reserve states of the reserve pool layers, and the weight of the combination is optimized by linear regression. That is, the output layer of the reserve pool network implements multiplication and addition operations through flash memory devices, providing accurate predictions and outputs for the computing system. This feature enhances the overall performance of the reserve pool network.

[0023] Figure 1The structure of the all-flash reservoir network is presented. A reservoir computing system consists of an input layer, a mask layer, a reservoir layer, and an output layer, each of which is constructed from 55nm NOR flash memory cells. The reservoir layer has a flash nonlinear delay feedback function (obtained by pressurizing the flash memory), while the output layer is implemented by flash memory cells with high reliability (i.e., original flash memory cells that have not been pressurized), which requires fine threshold adjustment and long-term retention characteristics, which are completed by the high reliability of the flash memory itself. The nonlinear characteristics of the flash memory cells in the reservoir layer enable the input signal to be mapped to a high-dimensional space, simplifying the data processing of the output layer. Due to the historical dependence and nonlinear dynamic characteristics of the reservoir layer, only the output layer needs to be trained, which can significantly reduce the training cost and time. In addition, a traditional flash NOR-type parallel arrangement is used to process the input signal and generate a dynamic output current response without modifying the original array connection of the NOR flash memory. Therefore, the optimization of the reservoir network structure and the simplified training process make the reservoir computing system considered to have potential prospects in efficient online training.

[0024] Figure 2 The principle of defect trapping characteristics caused by applying a program-erase voltage is demonstrated. After applying a program-erase voltage, the flash memory cell shows obvious nonlinear characteristics. The defects generated by hot electron injection and hot hole injection are mainly distributed on the interface of the tunnel layer, causing random telegraph noise and charge capture. As the number of traps increases, the experimental results show that charge capture dominates the current fluctuation. Specifically, when electrons are trapped by defects, the current decreases, and when electrons are de-trapped, the current increases.

[0025] like Figure 3 As shown, by applying negative pulse / positive pulse on the gate for charge de-trapping / trapping, the current fluctuation can be controlled, and the single pulse time is 0.1s and 10us. Figure 3 As an example only, the duration of 0.1S can be extended to a duration of 100us to 1s, and the gate voltage can also be changed in the range of 8 to 10V, -8 to -10. The dependence of the current response caused by charge trapping on the pulse sequence shows that the dynamic output depends on the current input as well as the history of the input signal.

[0026] To verify the stability of the system, the fluctuations within and between devices are as follows: Figure 4 As shown. The fluctuations within the device are very stable, which helps to reduce the error in the reservoir calculation system. The difference between devices should be kept as large as possible to enrich the reservoir calculation state. Since the nonlinear response is caused by the applied voltage, the relaxation time difference between devices can be adjusted by changing the pressure pulse time.

[0027] Figure 4The inter-device fluctuation and intra-device fluctuation under different states of the reservoir are shown. The horizontal axis is the different programming states, and the vertical axis is (a) current state and (b) fluctuation ratio. Figure 4 We can see that the flash memory devices after the pressurization operation meet the characteristics of large device-to-device fluctuation and small device-to-device fluctuation required for the devices in the reserve pool.

[0028] To study the device-to-device fluctuations in detail, Figure 5 The current response after different cycle numbers is shown. Figure 5 (a) The horizontal axis is the pulse time, and the vertical axis is the response current. Under the influence of different pressure application times, the response current of the flash memory is different. Figure 5 (b) The horizontal axis is the number of pulses applied at different pulse times, and the vertical axis is the response current. In addition, the accuracy of the reserve pool calculation system depends not only on the richness of the reserve state, but also on multiple time scales. Figure 5 (b) Demonstrates the ability to handle multiple time scales. The current response shows nonlinear characteristics across multiple time scales.

[0029] Figure 6 The test of the fine state adjustment capability and retention characteristics of the output layer flash memory cells is shown, demonstrating the good performance of the flash memory in the output layer. Figure 6 (a) The horizontal axis is the gate voltage and the vertical axis is the current. Figure 6 (b) shows that the current in the output layer of the unstressed flash memory remains stable during the stress time.

[0030] Figure 7 The schematic diagram of the reservoir computing system consisting of the input layer, mask layer, reservoir layer, and output layer is shown. All layers are built by flash cells. The input signal is fed in as a time series, and the mask processes it, converting it into an input pulse with an appropriate time step (less than the relaxation time). If multiple pulses are applied in a short time interval, the state of the cell will change significantly. Whereas the absence of input signals in a long time interval will cause the state to decay, i.e. the cell will return to its initial state before any pulses are applied. Therefore, the short-term memory and nonlinear properties of flash memory make the above-mentioned reserve computing possible. The output can be determined not only by the signal itself, but also by the sequence of the input signals. That is, the reservoir system has an advantage in solving time series tasks. Finally, after being processed in the output layer, the resulting vector can be represented as a linear combination of the reserve states, and the weights of its combination are optimized by linear regression, which can also be achieved by flash cells.

[0031] Figure 8The results of the proposed reservoir computing system processing timing signals are shown. The ideal values ​​and actual test values ​​are completely fitted, so the results show that the proposed system can fully predict the timing signals.

[0032] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A method for optimizing network performance of a storage pool based on all-flash memory, characterized in that: The method includes: Use flash memory to build the input layer, mask layer, reservoir layer, and output layer of the reservoir network; A programming and erasing voltage is applied to the gate of the reserve pool layer flash memory. The programming and erasing voltage generates defects inside the flash memory. The defects cause charge capture / de-trapping. When charge is captured, the output current of the flash memory decreases. When charge is de-trapped, the output current of the flash memory increases to the value before the programming and erasing voltage is applied. The current performance during charge capture / de-trapping is used to realize the short-term memory characteristics of the reserve pool network.

2. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 1, characterized in that: The programming voltage is 8V to 10V for the gate and 4.2V for the drain, and the duration is an integer multiple of 10us. The erasing voltage is -10V to -8V for the gate and 4.2V for the drain, and the duration is 100us to 1s. Charge de-trapping is achieved when the programming voltage is applied, and charge trapping is achieved when the erasing voltage is applied.

3. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 2, characterized in that: The gate programming voltage is multiple 10V pulses with a duration of 10us, and the gate erase voltage is a -10V pulse with a duration of 0.1s.

4. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 1, characterized in that: The time for charge trapping / de-trapping is called relaxation time, and controllable relaxation time can be introduced by controlling the application time of programming and erasing voltages.

5. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 4, characterized in that: The longer the programming and erasing voltage is applied, the shorter the relaxation time.

6. The method for optimizing the network performance of a storage pool based on all-flash memory according to claim 4, characterized in that: When the reservoir network is working, the time step of the input pulse is smaller than the relaxation time.

7. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 1, characterized in that: The output layer of the reserve pool linearly combines the reserve states of the reserve pool layers, and the weight of the combination is optimized through linear regression.

8. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 1, characterized in that: The input layer, mask layer, reservoir layer and output end of the reservoir network are constructed using 55nm NOR flash memory cells.

9. The method for optimizing network performance of a storage pool based on all-flash memory according to claim 8, characterized in that: 55nm NOR flash memory cells are arranged in parallel.

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