Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: transistors (M1) and (M2) that supply a voltage (Vp) and a voltage (Vn) to a first terminal, respectively; transistors (M3) and (M4) for supplying a power supply voltage and a ground voltage to a first terminal, respectively; a level shifter (LS1) that converts the signal EP and outputs a signal RGP; and a second level shifter (LS2) that converts the signal EN and outputs a signal RGN. When the voltage Vp is output from the first terminal, the power supply voltage is supplied from the transistor M3 to the first terminal according to the signal RGN, and then the voltage Vp is supplied from the transistor M1 to the first terminal according to the signal RGP. When a voltage Vn is output from a first terminal, a ground voltage is supplied from a transistor M4 to the first terminal in accordance with a signal RGP, and then the voltage Vn is supplied from a transistor M2 to the first terminal in accordance with a signal RGN.

Description

[0001] Cross-references of related applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-131410 (filing date: August 10, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] An embodiment of the present invention relates to a semiconductor device. Background Art

[0004] A semiconductor device including a high-frequency switch is known. Summary of the invention

[0005] A semiconductor device according to an embodiment includes: a first transistor supplied with a first voltage higher than a power supply voltage and supplying the first voltage to a first terminal; a second transistor supplied with a second voltage lower than a ground voltage and supplying the second voltage to the first terminal; a third transistor supplied with the power supply voltage and supplying the power supply voltage to the first terminal; a fourth transistor supplied with the ground voltage and supplying the ground voltage to the first terminal; a first level shifter, when a first signal is the power supply voltage, converting the power supply voltage to the first voltage and outputting a second signal; and a second level shifter, when a third signal is the ground voltage, converting the ground voltage to the second voltage and outputting a fourth signal. When the first voltage is output from the first terminal, the power supply voltage is supplied from the third transistor to the first terminal according to the fourth signal, and then the first voltage is supplied from the first transistor to the first terminal according to the second signal, and when the second voltage is output from the first terminal, the ground voltage is supplied from the fourth transistor to the first terminal according to the second signal, and then the second voltage is supplied from the second transistor to the first terminal according to the fourth signal.

[0006] Another semiconductor device of the embodiment comprises: a plurality of switch circuits; and a delay circuit for delaying a plurality of control signals corresponding to the plurality of switch circuits, wherein the plurality of switch circuits respectively comprise: a first transistor supplied with a first voltage higher than a power supply voltage and supplying the first voltage to a first end; a second transistor supplied with a second voltage lower than a ground voltage and supplying the second voltage to the first end; a third transistor supplied with the power supply voltage and supplying the power supply voltage to the first end; a fourth transistor supplied with the ground voltage and supplying the ground voltage to the first end; a first level shifter for converting the power supply voltage into the first voltage and outputting a second signal when a first signal is the power supply voltage; and a second level shifter for converting the ground voltage into the second voltage and outputting a fourth signal when a third signal is the ground voltage, and when the first voltage is output from the first end, the power supply voltage is supplied from the third transistor to the first end according to the fourth signal. A first terminal is provided, and then the first voltage is supplied from the first transistor to the first terminal according to the second signal. When the second voltage is output from the first terminal, the ground voltage is supplied from the fourth transistor to the first terminal according to the second signal. Then, the second voltage is supplied from the second transistor to the first terminal according to the fourth signal. The delay circuit comprises: a first circuit for generating a delay signal according to the plurality of control signals; and a plurality of logic circuits for generating the first signal and the third signal using each of the plurality of control signals and the delay signal. Each of the plurality of logic circuits outputs each of the plurality of control signals as a signal of one of the first signal and the third signal. Each of the plurality of logic circuits delays each of the plurality of control signals using the delay signal, and outputs each of the plurality of control signals after delay as a signal of the other of the first signal and the third signal.

[0007] According to the present embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram showing the configuration of a wireless device including the switch circuit according to the first embodiment.

[0009] Figure 2 : is a circuit diagram showing the configuration of a switch circuit according to the first embodiment.

[0010] Figure 3 1 is a timing chart showing the operation of the switch control circuit in the switch circuit of the first embodiment.

[0011] Figure 41 is a timing chart showing the operation of the switch control circuit in the switch circuit of the comparative example.

[0012] Figure 5 : is a circuit diagram showing the configuration of a switch circuit according to the second embodiment.

[0013] Figure 6 It is a circuit diagram showing a configuration of a switch circuit according to a modification of the second embodiment.

[0014] Figure 7 It is a circuit diagram showing the configuration of a switch circuit according to another modified example of the second embodiment.

[0015] Figure 8 : is a circuit diagram showing the configuration of a switch circuit according to a third embodiment.

[0016] Fig. 9 : is a circuit diagram showing the configuration of a switch circuit according to a fourth embodiment.

[0017] Fig.10 : is a circuit diagram showing the configuration of a delay circuit included in a plurality of switch circuits according to the fifth embodiment.

[0018] Fig.11 : is a circuit diagram showing the configuration of a delay circuit included in a plurality of switch circuits according to the sixth embodiment.

[0019] Fig.12 It is a timing chart showing the operation of the switch control circuit in the switch circuit according to the sixth embodiment.

[0020] Fig.13 : is a circuit diagram showing the configuration of a delay circuit included in a switch circuit according to a modification of the sixth embodiment.

[0021] Fig.14 : is a circuit diagram showing the configuration of a switch element in a delay circuit according to a modification of the sixth embodiment.

[0022] Fig.15 It is a circuit diagram showing the configuration of a switch circuit according to the seventh embodiment.

[0023] Fig.16 This is a circuit diagram showing a part of the operation of the on / off switching circuit in the switch circuit of the seventh embodiment.

[0024] Fig.17 It is a circuit diagram showing the configuration of a switch circuit according to an eighth embodiment.

[0025] Fig.18 This is a circuit diagram showing a part of the operation of the on / off switching circuit in the switch circuit according to the eighth embodiment.

[0026] Fig.19 : is a circuit diagram showing the configuration of a switch circuit according to a ninth embodiment.

[0027] Fig. 20 This is a circuit diagram showing a part of the operation of the on / off switching circuit in the switch circuit of the ninth embodiment.

[0028] Description of Reference Numerals

[0029] 1: switch circuit; 2: switch circuit; 3: switch circuit; 4: switch circuit; 5: signal processing circuit; 6: signal processing circuit; 7: control circuit; 8: power supply circuit; 10: switch control circuit; 11: on / off switching circuit; 11a: on / off switching circuit; 11b: on / off switching circuit; 11c: on / off switching circuit; 11d: on / off switching circuit; 11e: on / off switching circuit; 11f: on / off switching circuit; 12: delay circuit; 12a: delay circuit; 12b: delay circuit; 12c: delay circuit; 20: high frequency switch; 20a: high frequency switch; 20b: high frequency switch; 20c: high frequency switch; 20d: high frequency switch; 20e: high frequency switch; B1: buffer; B2: buffer; B3: buffer; B4: buffer; B5: buffer; B6: buffer; D1: diode; D2: diode; LS1: level shifter; LS2: level shifter; LS3: level shifter; M1: p-channel MOS field effect transistor; M2: n-channel MOS field effect transistor; M3: n-channel MOS field effect transistor; M4: p-channel MOS field effect transistor. DETAILED DESCRIPTION

[0030] The following describes the embodiments with reference to the drawings. In the following description, common reference symbols are added to the structural elements having the same function and structure. In addition, the embodiments shown below illustrate the device and method for concretizing the technical ideas of the embodiments, and do not specify the material, shape, structure and configuration of the components as the following embodiments.

[0031] Function blocks can be implemented as hardware, computer software, or a combination of both. Function blocks do not necessarily have to be distinguished as in the following examples. For example, a portion of the functions may also be performed by a function block different from the illustrated function block. Furthermore, the illustrated function block may also be divided into more refined function sub-blocks.

[0032] 1. First Implementation

[0033] Hereinafter, a semiconductor device according to a first embodiment will be described. The semiconductor device includes a switch circuit 1 .

[0034] 1.1 Structure of the First Embodiment

[0035] 1.1.1 Wireless Devices

[0036] Figure 1 This is a block diagram showing the structure of a wireless device WD including a switch circuit 1 according to the first embodiment. The wireless device WD is, for example, a smartphone, a feature phone, a portable terminal (e.g., a tablet terminal), a personal computer, a game device, a router, a base station, etc. The wireless device WD transmits and receives signals using communication standards such as LTE (registered trademark) (Long Term Evolution) and / or Wifi.

[0037] The wireless device WD includes, for example, an antenna ANT, switch circuits 1, 2, 3, and 4, signal processing circuits 5 and 6, a control circuit 7, and a power supply circuit 8. In the wireless device WD, for example, the switch circuits 1, 2, 3, and 4 and the power supply circuit 8 are mounted on a semiconductor substrate to form a semiconductor device (or semiconductor package, IC chip). Figure 1 2 shows an example in which the power supply circuit 8 is provided outside the switch circuits 1, 2, 3, and 4, but the power supply circuit 8 may be provided inside the switch circuit.

[0038] The antenna ANT receives high frequency signals from other devices (eg, base stations or other wireless devices). The antenna ANT can also transmit high frequency signals from the wireless device WD to other devices.

[0039] The control circuit 7 sends a control signal CNT (including CNT1, CNT2, CNT3, CNT4) to the switch circuits 1, 2, 3, and 4 and the signal processing circuits 5 and 6, for example. Whether the switch circuits 1, 2, 3, and 4 are in an on state or an off state is controlled by the control signal CNT sent from the control circuit 7. While a certain switch circuit is in an on state, the switch circuit can transmit a signal between the first end and the second end of the switch circuit. On the other hand, while a certain switch circuit is in an off state, the switch circuit does not transmit a signal between the first end and the second end of the switch circuit. The signal processing circuits 5 and 6 process signals based on the control signal CNT received from the control circuit 7.

[0040] A first end of the switch circuit 1 is connected to the antenna ANT, and a second end of the switch circuit 1 is connected to the signal processing circuit 5. The switch circuit 1 receives a control signal CNT1 from the control circuit 7. The switch circuit 1 transmits a high-frequency signal received via the antenna ANT to the signal processing circuit 5, for example, while being set to an on state based on the control signal CNT1.

[0041] The first end of the switch circuit 2 is connected to the signal path between the switch circuit 1 and the signal processing circuit 5. The second end of the switch circuit 2 is connected to a node to which the ground voltage GND is supplied (hereinafter referred to as the ground voltage GND node).

[0042] The switch circuit 2 receives a control signal CNT2 from the control circuit 7. The switch circuit 2 is set to an on state based on the control signal CNT2, for example, while the switch circuit 1 is set to an off state. While the switch circuit 2 is set to an on state, the potential of the signal path between the switch circuit 1 and the signal processing circuit 5 is set to a ground voltage.

[0043] The signal processing circuit 5 receives the high-frequency signal transmitted via the switch circuit 1 , and performs various processes on the high-frequency signal based on the control signal CNT3 received from the control circuit 7 .

[0044] A first end of the switch circuit 3 is connected to the antenna ANT, and a second end of the switch circuit 3 is connected to the signal processing circuit 6. The switch circuit 3 receives, for example, a control signal CNT2 from the control circuit 7. The switch circuit 3 transmits, for example, a high-frequency signal received via the antenna ANT to the signal processing circuit 6 while being set to an on state based on the control signal CNT2. The frequency band of the high-frequency signal transmitted by the switch circuit 3 is different from the frequency band of the high-frequency signal transmitted by the switch circuit 1, for example. The switch circuit 1 and the switch circuit 3 are selectively set to an on state under the control of the control circuit 7, for example.

[0045] The first end of the switch circuit 4 is connected to the signal path between the switch circuit 3 and the signal processing circuit 6. The second end of the switch circuit 4 is, for example, grounded. The switch circuit 4 receives, for example, a control signal CNT1 from the control circuit 7. The switch circuit 4 is, for example, in an on state based on the control signal CNT1 while the switch circuit 3 is in an off state. While the switch circuit 4 is in the on state, the potential of the signal path between the switch circuit 3 and the signal processing circuit 6 is set to the ground potential.

[0046] The signal processing circuit 6 receives the high-frequency signal transmitted via the switch circuit 3 , and performs various processes on the high-frequency signal based on the control signal CNT4 received from the control circuit 7 .

[0047] The power supply circuit 8 is provided in the semiconductor device including the switch circuit 1, and generates the high voltage Vp and the low voltage Vn using the power supply voltage VDD and the ground voltage GND supplied from the outside of the semiconductor device. In addition, as mentioned above, the power supply circuit 8 can be provided inside the switch circuit 1 or outside the switch circuit 1. The power supply circuit 8 includes, for example, a charge pump. The high voltage Vp is, for example, about 3V to 5V, and is set to 3.5V here. The low voltage Vn is, for example, -4V to -2V, and is set to -3.5V here.

[0048] In the above description, the switch circuits 1 and 3 are described as transmitting high-frequency signals received by the wireless device WD from other devices. The switch circuits 1 and 3 are not limited thereto. The switch circuits 1 and 3 may also be circuits transmitting high-frequency signals sent by the wireless device WD to other devices.

[0049] 1.1.2 Switching Circuit

[0050] Next, the switch circuit 1 according to the first embodiment will be described. Figure 2 : is a circuit diagram showing the configuration of a switch circuit according to the first embodiment.

[0051] The switch circuit 1 includes a switch control circuit 10 and a high-frequency switch 20. The switch control circuit 10 controls the high-frequency switch 20 to switch from an on state to an off state or from an off state to an on state. These switching from an on state to an off state and from an off state to an on state are also referred to as on / off switching.

[0052] The high frequency switch 20 is, for example, a switch for switching the path of the high frequency signal. The on state of the high frequency switch 20 is a state in which all the switching transistors connected between the first end and the second end are turned on and the first end and the second end are electrically connected. The off state of the high frequency switch 20 is a state in which one of the switching transistors is turned off and the first end and the second end are electrically disconnected. The details of the high frequency switch 20 will be described later.

[0053] Next, the switch control circuit 10 will be described. The switch control circuit 10 includes an on / off switching circuit 11 and a delay circuit 12 .

[0054] The on / off switching circuit 11 outputs a switch signal SWG for setting the high-frequency switch 20 to the on state or the off state from the terminal TSW. The on / off switching circuit 11 receives a control signal CNT from the control circuit 7. The on / off switching circuit 11 outputs a voltage Vp or a voltage Vn as the switch signal SWG based on the control signal CNT. When the voltage Vp is output as the switch signal SWG, the high-frequency switch 20 is set to the on state. On the other hand, when the voltage Vn is output as the switch signal SWG, the high-frequency switch 20 is set to the off state.

[0055] The delay circuit 12 generates a signal EN and a signal EP based on the control signal CNT. The signal EN is a signal whose rising time from the "L" level to the "H" level is the same as that of the control signal CNT, and whose falling time from the "H" level to the "L" level is delayed. The signal EP is a signal whose rising time from the "L" level to the "H" level is delayed with respect to the control signal CNT, and whose falling time from the "H" level to the "L" level is the same as that of the control signal CNT.

[0056] Next, the circuit configuration and the connection of circuit elements in the switch control circuit 10 will be described.

[0057] The on / off switching circuit 11 has p-channel MOS field effect transistors (hereinafter referred to as pMOS transistors) M1, M4, M5, M7, M9, M11, M13, M15, n-channel MOS field effect transistors (hereinafter referred to as nMOS transistors) M2, M3, M6, M8, M10, M12, M14, M16, buffers B1, B2, B3, B4 and diodes D1, D2.

[0058] The signal EP is input to the input terminal of the buffer B1. The output terminal of the buffer B1 is connected to the input terminal of the buffer B2. The output terminal of the buffer B2 is connected to the gates of the pMOS transistor M5 and the nMOS transistor M6.

[0059] The first power supply terminal of the buffer B1 is connected to a node to which the power supply voltage VDD is supplied (hereinafter referred to as the power supply voltage VDD node). The power supply voltage VDD is supplied from outside the semiconductor device to the power supply voltage VDD node. The second power supply terminal of the buffer B1 is connected to a ground voltage GND node. The ground voltage GND is supplied from outside the semiconductor device to the ground voltage GND node. When the signal EP is at an "H" level, the buffer B1 outputs the power supply voltage VDD as an "H" level, and when the signal EP is at an "L" level, the buffer B1 outputs the ground voltage GND as an "L" level.

[0060] The first power supply terminal of the buffer B2 is connected to a node to which the voltage Vp is supplied (hereinafter referred to as the voltage Vp node). The voltage Vp is supplied from the power supply circuit 8 to the voltage Vp node. The second power supply terminal of the buffer B2 is connected to the ground voltage GND node. When the output of the buffer B1 is the power supply voltage VDD, the buffer B2 outputs the voltage Vp as an "H" level, and when the output of the buffer B1 is the ground voltage GND, the buffer B2 outputs the ground voltage GND as an "L" level. The buffer B1 and the buffer B2 constitute a level shifter LS1.

[0061] The drains of the pMOS transistor M5 and the nMOS transistor M6 are connected to the gates of the pMOS transistor M7 and the nMOS transistor M8. The drains of the pMOS transistor M7 and the nMOS transistor M8 are connected to the source of the pMOS transistor M1 and the gate of the pMOS transistor M4. The signal RGP corresponding to the signal EP is output from the drains of the pMOS transistor M7 and the nMOS transistor M8.

[0062] The sources of the pMOS transistors M5 and M7 are connected to a voltage node Vp, and the sources of the nMOS transistors M6 and M8 are connected to a ground voltage node GND.

[0063] The drain of the pMOS transistor M1 is connected to the drain of the nMOS transistor M2 and the terminal TSW. The gates of the pMOS transistors M1 and M2 are connected to a ground voltage GND node.

[0064] The drain of the nMOS transistor M3 is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the power supply voltage VDD node. The drain of the pMOS transistor M4 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the ground voltage GND node. The sources of the nMOS transistor M3 and the pMOS transistor M4 are connected to the terminal TSW. In addition, the switching signal SWG is output from the terminal TSW.

[0065] The signal EN is input to the input terminal of the buffer B3. The output terminal of the buffer B3 is connected to the input terminal of the buffer B4. The output terminal of the buffer B4 is connected to the gates of the pMOS transistor M9 and the nMOS transistor M10.

[0066] The first power supply terminal of the buffer B3 is connected to the power supply voltage VDD node. The second power supply terminal of the buffer B3 is connected to the ground voltage GND node. When the signal EN is at an "H" level, the buffer B3 outputs the power supply voltage VDD as an "H" level, and when the signal EN is at an "L" level, the buffer B3 outputs the ground voltage GND as an "L" level.

[0067] The first power supply terminal of the buffer B4 is connected to the power supply voltage VDD node. The second power supply terminal of the buffer B4 is connected to a node to which the voltage Vn is supplied (hereinafter referred to as the voltage Vn node). The voltage Vn is supplied from the power supply circuit 8 to the voltage Vn node. When the output of the buffer B3 is the power supply voltage VDD, the buffer B4 outputs the power supply voltage VDD as an "H" level, and when the output of the buffer B3 is the ground voltage GND, the buffer B4 outputs the voltage Vn as an "L" level. The buffer B3 and the buffer B4 constitute a level shifter LS2.

[0068] The drains of the pMOS transistor M9 and the nMOS transistor M10 are connected to the gates of the pMOS transistor M11 and the nMOS transistor M12. The drains of the pMOS transistor M11 and the nMOS transistor M12 are connected to the source of the nMOS transistor M2. The sources of the pMOS transistors M9 and M11 are connected to the ground voltage GND node. The sources of the nMOS transistors M10 and M12 are connected to the voltage Vn node.

[0069] The output terminal of the buffer B4 is also connected to the gates of the pMOS transistor M13 and the nMOS transistor M14. The drains of the pMOS transistor M13 and the nMOS transistor M14 are connected to the gates of the pMOS transistor M15 and the nMOS transistor M16. The drains of the pMOS transistor M15 and the nMOS transistor M16 are connected to the gate of the nMOS transistor M3. The signal RGN corresponding to the signal EN is output from the drains of the pMOS transistor M15 and the nMOS transistor M16.

[0070] The sources of the pMOS transistors M13 and M15 are connected to the power supply voltage VDD node, and the sources of the nMOS transistors M14 and M16 are connected to the voltage Vn node.

[0071] The delay circuit 12 includes buffers B5 and B6 , a resistor element R, a capacitor element C, an AND circuit AD1 , and an OR circuit OR1 .

[0072] The control signal CNT is input to the input terminal of the buffer B5. The output terminal of the buffer B5 is connected to the first input terminal of the logic AND circuit AD1, the first input terminal of the logic OR circuit OR1, and the input terminal of the buffer B6. The first power supply terminal of the buffer B5 is connected to the power supply voltage VDD node. The second power supply terminal of the buffer B5 is connected to the ground voltage GND node. Similarly, the first power supply terminal of the buffer B6 is connected to the power supply voltage VDD node. The second power supply terminal of the buffer B6 is connected to the ground voltage GND node.

[0073] The output end of the buffer B6 is connected to one end of the resistor element R. The other end of the resistor element R is connected to the first electrode of the capacitor element C, the second input end of the logic AND circuit AD1, and the second input end of the logic OR circuit OR1. The second electrode of the capacitor element C is connected to the ground voltage GND node. Moreover, the signal EP is output from the output end of the logic AND circuit AD1, and the signal EN is output from the output end of the logic OR circuit OR1.

[0074] Next, use Figure 2 The circuit structure and connection of circuit elements in the high frequency switch 20 are described. Figure 2 In FIG. 1 , a first end and a second end of the high frequency switch 20 are shown as a terminal T1 and a terminal T2 , respectively.

[0075] The high frequency switch 20 includes nMOS transistors N1_1, N1_2, N1_3, ..., N1_(n-1), N1_n and resistors R1_1, R1_2, R1_3, ..., R1_(n-1), R1_n. In addition, n is an integer greater than 1. The number of transistors and resistors included in the high frequency switch 20 is arbitrary and may be one or more.

[0076] In addition, in the circuit symbols of each transistor, one end of the transistor is shown as a drain and the other end is a source, but the drain and the source can be swapped according to the relationship between the potentials of one end and the other end. The resistance values ​​of the resistor elements R1_1 to R1_n are, for example, substantially the same. The following describes the case where the resistance values ​​of these resistor elements R1_1 to R1_n are substantially the same.

[0077] The current paths of nMOS transistors N1_1, N1_2, N1_3, ..., N1_n are connected in series between terminal T1 and terminal T2. The details are as follows. The drain of nMOS transistor N1_1 is connected to terminal T1, and the drain of nMOS transistor N1_2 is connected to the source of nMOS transistor N1_1. The drain of nMOS transistor N1_3 is connected to the source of nMOS transistor N1_2, and the drain of nMOS transistor N1_4 is connected to the source of nMOS transistor N1_3. The connection relationship of nMOS transistors N1_4, N1_5, ..., N1_n is the same below, and the source of nMOS transistor N1_n is connected to terminal T2.

[0078] A resistor element R1_1 is connected between the gate (or control terminal) of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. A resistor element R1_2 is connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. A resistor element R1_3 is connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. The same is true for the resistor elements R1_4, R1_5, ..., R1_n. Furthermore, one end of the resistor element R1_n is connected to the gate of the nMOS transistor N1_n, and the terminal TSW is connected to the other end of the resistor element R1_n.

[0079] 1.2 Operation of the First Embodiment

[0080] Next, the operation of the switch circuit 1 according to the first embodiment will be described.

[0081] Figure 3 1 is a timing chart showing the operation of the switch control circuit 10 in the switch circuit 1 according to the first embodiment.

[0082] When the high frequency switch 20 is switched from the off state to the on state, the switching signal SWG output from the terminal TSW of the switch control circuit 10 is set from the voltage Vn to the voltage Vp. In addition, when the high frequency switch 20 is switched from the on state to the off state, the switching signal SWG output from the terminal TSW of the switch control circuit 10 is set from the voltage Vp to the voltage Vn.

[0083] In the present embodiment, when the high frequency switch 20 is switched from the off state to the on state, the power supply voltage VDD (for example, 1.2V) is supplied to the terminal TSW before the voltage Vp (for example, 3.5V) is supplied to the terminal TSW. Then, after the voltage of the terminal TSW rises to about the power supply voltage VDD, the voltage Vp is supplied to the terminal TSW. In this way, when the switching signal SWG is raised from the voltage Vn to the voltage Vp, the power supply voltage VDD is first supplied to the terminal TSW to raise the switching signal SWG from the voltage Vn to the power supply voltage VDD, and then the voltage Vp is supplied to the terminal TSW, thereby raising the switching signal SWG from the power supply voltage VDD to the voltage Vp. As a result, even when the driving force of the power supply circuit 8 that supplies the voltage Vp is insufficient, the voltage Vp is not reduced when the voltage Vp is supplied, and the switching signal SWG can be raised from the voltage Vn to the voltage Vp. This prevents the switching signal SWG from changing from voltage Vn to voltage Vp from changing slowly due to a drop in voltage Vp caused by insufficient driving force of power supply circuit 8. This shortens the time required for the switching signal SWG to change from voltage Vn to voltage Vp.

[0084] In addition, when the high-frequency switch 20 is switched from the on state to the off state, before the voltage Vn (for example, -3.5V) is supplied to the terminal TSW, the ground voltage GND (for example, 0V) is supplied to the terminal TSW. Then, after the voltage of the terminal TSW drops to about the ground voltage GND, the voltage Vn is supplied to the terminal TSW. In this way, when the switch signal SWG is dropped from the voltage Vp to the voltage Vn, the ground voltage GND is first supplied to the terminal TSW to drop the switch signal SWG from the voltage Vp to the ground voltage GND, and then the voltage Vn is supplied to the terminal TSW, thereby dropping the switch signal SWG from the ground voltage GND to the voltage Vn. Thus, even when the driving force of the power supply circuit 8 that supplies the voltage Vn is insufficient, the voltage Vn is not increased when the voltage Vn is supplied, and the switch signal SWG can be dropped from the voltage Vp to the voltage Vn. Thus, the transition of the switch signal SWG from the voltage Vp to the voltage Vn is prevented from being slowed down due to the increase of the voltage Vn generated when the driving force of the power supply circuit 8 is insufficient. Thus, the time required for the switching signal SWG to transition from the voltage Vp to the voltage Vn can be shortened.

[0085] The following describes in detail the operations of the high-frequency switch 20 (1) when it is switched from the off state to the on state and (2) when it is switched from the on state to the off state.

[0086] (1) When switching from the OFF state to the ON state

[0087] First, at time t0, a voltage Vn (e.g., -3.5V) is output from the terminal TSW of the switch control circuit 10 as a signal SWG. As a result, the high-frequency switch 20 is set to an off state. At this time, the control signal CNT input to the delay circuit 12 in the switch control circuit 10 is "L" (e.g., 0V), and the signals EP and EN are also "L". As a result, the transistor M2 is set to an on state, and the transistors M1, M3, and M4 are set to an off state.

[0088] Next, at time t1, the control signal CNT rises from "L" to "H" (for example, the power supply voltage VDD). Then, the signal EN rises from "L" to "H", and the signal EP remains "L". Therefore, the transistor M3 is set to the on state, and the transistors M1, M2, and M4 are set to the off state. As a result, the charge flows from the power supply voltage VDD node to the terminal TSW via the diode D1 and the transistor M3, and the terminal TSW is charged. As a result, Figure 3 As shown, the voltage of the signal SWG rises, and when it reaches a first voltage (eg, 0.7 V) at time t2a, the high-frequency switch 20 is switched from the off state to the on state.

[0089] Next, at time t2, signal EP rises from "L" to "H", and signal EN remains "H". Therefore, transistor M1 is set to the on state, and transistors M2, M3, and M4 are set to the off state. As a result, charge flows from the voltage Vp node to the terminal TSW via transistor M1, and the terminal TSW is further charged. As a result, Figure 3 As shown, the voltage of signal SWG further rises to voltage Vp, and high-frequency switch 20 is stably maintained in the on state.

[0090] (2) When switching from the on state to the off state

[0091] Afterwards, at time t3, the control signal CNT drops from "H" to "L". Then, the signal EP drops from "H" to "L", and the signal EN remains "H". Therefore, the transistor M4 is set to the on state, and the transistors M1, M2, and M3 are set to the off state. As a result, the charge of the terminal TSW is released to the ground voltage GND node via the transistor M4 and the diode D2, and the terminal TSW is discharged. As a result, Figure 3 As shown, the voltage of the signal SWG decreases, and when it reaches a second voltage at time t4a, the high-frequency switch 20 is switched from the on state to the off state.

[0092] Next, at time t4, signal EN drops from "H" to "L", and signal EP remains "L". Therefore, transistor M2 is set to the on state, and transistors M1, M3, and M4 are set to the off state. As a result, the charge at terminal TSW is released to the voltage Vn node via transistor M2, and terminal TSW is further discharged. As a result, Figure 3 As shown, the voltage of signal SWG further drops to voltage Vn, and high-frequency switch 20 is stably maintained in the off state.

[0093] As described above, when the high frequency switch 20 is set to the on state, the transistor M1 is set to be on, the transistor M2 is set to be off, and the voltage Vp is output from the terminal TSW of the switch control circuit 10 to the high frequency switch 20 as the switching signal SWG.

[0094] When the high-frequency switch 20 is switched from the off state to the on state, before the transistor M1 is set to be on and the transistor M2 is set to be off, the transistors M1 and M2 are set to be off and the transistor M3 is set to be on. During this period, the power supply voltage VDD is supplied from the power supply voltage VDD node to the terminal TSW. After that, the transistor M1 is set to be on and the transistors M2, M3 and M4 are set to be off. During this period, the voltage Vp is supplied from the voltage Vp node to the terminal TSW. As a result, the signal SWG changes from the voltage Vn to the voltage Vp at a high speed. As a result, the high-frequency switch 20 is switched from the off state to the on state at a high speed.

[0095] When the high frequency switch 20 is set to the off state, the transistor M2 is set to be on, the transistor M1 is set to be off, and the voltage Vn is output from the terminal TSW of the switch control circuit 10 to the high frequency switch 20 as the switching signal SWG.

[0096] When the high-frequency switch 20 is switched from the on state to the off state, before the transistor M2 is set to be on and the transistor M1 is set to be off, the transistors M1 and M2 are set to be off, and the transistor M4 is set to be on. During this period, a current is introduced from the terminal TSW to the ground voltage GND node. After that, the transistor M2 is set to be on, and the transistors M1, M3, and M4 are set to be off. During this period, a current is introduced from the terminal TSW to the voltage Vn node. As a result, the signal SWG changes from the voltage Vp to the voltage Vn at a high speed. As a result, the high-frequency switch 20 is switched from the on state to the off state at a high speed.

[0097] A diode D1 is provided between the drain of nMOS transistor M3 and the power supply voltage VDD node to prevent a reverse current from flowing from terminal TSW to the power supply voltage VDD node via the parasitic diode of nMOS transistor M3 when high frequency switch 20 is set to the on state, that is, when signal SWG is at voltage Vp.

[0098] Similarly, a diode D2 is provided between the drain of pMOS transistor M4 and the ground voltage GND node. Diode D2 prevents a reverse current from flowing from the ground voltage GND node to terminal TSW via the parasitic diode of pMOS transistor M4 when high frequency switch 20 is set to the off state, that is, when signal SWG is at voltage Vn.

[0099] 1.3 Effects of the First Implementation

[0100] According to the first embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0101] Below, use Figure 4 A switch circuit of a comparative example is described, and then the effects of the first embodiment are described.

[0102] Figure 4 1 is a timing chart showing the operation of the switch control circuit in the switch circuit of the comparative example.

[0103] In the comparative example, when the high frequency switch is switched from the off state to the on state, at time t11, the voltage Vp is supplied from the power supply circuit 8 to the terminal TSW. However, if the driving force of the power supply circuit 8 is insufficient, as shown in FIG. Figure 4 As shown in FIG. 1 , the voltage Vp supplied from the power supply circuit 8 drops significantly. Therefore, the rise of the signal SWG from the voltage Vn to the voltage Vp slows down. For example, at time t12, when the signal SWG rises to the first voltage, the high-frequency switch switches from the off state to the on state. Therefore, the switching of the high-frequency switch from the off state to the on state slows down.

[0104] When the high frequency switch is switched from the on state to the off state, at time t13, the voltage Vn is supplied from the power supply circuit 8 to the terminal TSW. That is, the current flows from the terminal TSW into the voltage Vn node. However, if the driving force of the power supply circuit 8 is insufficient, as shown in FIG. Figure 4 As shown in FIG. 1 , the voltage Vn supplied from the power supply circuit 8 rises significantly. Therefore, the drop of the signal SWG from the voltage Vp to the voltage Vn slows down. For example, at time t14, when the signal SWG drops to the second voltage, the high-frequency switch switches from the on state to the off state. Therefore, the switching of the high-frequency switch from the on state to the off state slows down.

[0105] On the other hand, in the first embodiment, when the high-frequency switch is switched from the off state to the on state or from the on state to the off state, the operation is as follows.

[0106] When the high-frequency switch 20 is switched from the off state to the on state, the power supply voltage VDD supplied from the outside of the semiconductor device is first supplied to the terminal TSW. Then, the voltage Vp output from the power supply circuit 8 in the semiconductor device is supplied to the terminal TSW. In this way, by switching the power supply voltage VDD and the voltage Vp to the terminal TSW in two stages, even if the driving force of the power supply circuit 8 that supplies the voltage Vp is insufficient, the voltage Vp is not reduced when the voltage Vp is supplied, and the switching signal SWG can be increased from the voltage Vn to the voltage Vp. As a result, the switching of the high-frequency switch 20 from the off state to the on state can be accelerated. That is, the switching time of the high-frequency switch 20 from the off state to the on state can be shortened.

[0107] In addition, when the high-frequency switch 20 is switched from the on state to the off state, the ground voltage GND supplied from the outside of the semiconductor device is first supplied to the terminal TSW. Thereafter, the voltage Vn output from the power supply circuit 8 in the semiconductor device is supplied to the terminal TSW. In this way, by switching the ground voltage GND and the voltage Vn to the terminal TSW in two stages, even when the driving force of the power supply circuit 8 supplying the voltage Vn is insufficient, the voltage Vn is not increased when the voltage Vn is supplied, and the switch signal SWG can be reduced from the voltage Vp to the voltage Vn. As a result, the switching of the high-frequency switch 20 from the on state to the off state can be accelerated. That is, the switching time of the high-frequency switch 20 from the on state to the off state can be shortened.

[0108] 2. Second Implementation

[0109] Next, a semiconductor device according to a second embodiment is described. In the second embodiment, a circuit including an nMOS transistor and a resistor element is added to the high frequency switch 20 according to the first embodiment. In addition, signals supplied to these nMOS transistors and resistor elements are prepared. In the second embodiment, descriptions of points similar to those of the switch circuit 1 according to the first embodiment in terms of structure, operation, and effects are omitted, and the description will be centered on the points of difference.

[0110] 2.1 Structure of the Second Embodiment

[0111] Figure 5 : is a circuit diagram showing the configuration of a switch circuit according to the second embodiment.

[0112] In the switch circuit 1 of the second embodiment, the on / off switching circuit 11 a and the high-frequency switch 20 a included in the switch control circuit 10 are different from those of the first embodiment.

[0113] The on / off switching circuit 11a includes a terminal TRN connected to the drains of the pMOS transistor M15 and the nMOS transistor M16. A signal RGN corresponding to the signal EN is output from the terminal TRN.

[0114] The high frequency switch 20a has Figure 2 In addition to the structure shown, the high-frequency switch 20 further includes, for example, nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), N2_n and resistor elements R2_1, R2_2, R2_3, ..., R2_(n-1), R2_n.

[0115] The high frequency switch 20a is provided with an nMOS transistor N2_1 capable of short-circuiting both ends of the resistor element R1_1. An nMOS transistor N2_2 capable of short-circuiting both ends of the resistor element R1_2 is provided. An nMOS transistor N2_3 capable of short-circuiting both ends of the resistor element R1_3 is provided. The same is true for the nMOS transistors N2_4, N2_5, ..., N2_(n-1), and N2_n. In addition, the resistor elements R2_1, R2_2, R2_3, ..., R2_(n-1), and R2_n are provided at the gates of the nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), and N2_n, respectively.

[0116] Next, the connection of the circuit elements in the high-frequency switch 20a will be described.

[0117] The drain and source of the nMOS transistor N2_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the drain of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_1, and the source of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_2. The drain and source of the nMOS transistor N2_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the drain of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_2, and the source of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_3. The drain and source of the nMOS transistor N2_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the drain of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_3, and the source of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_4. The same applies to the nMOS transistors N2_4, N2_5, ..., N2_(n-1). Furthermore, the drain of the nMOS transistor N2_n is connected to the gate of the nMOS transistor N1_n, and the source of the nMOS transistor N2_n is connected to the terminal TSW.

[0118] A resistor element R2_1 is connected between the gate of the nMOS transistor N2_1 and the gate of the nMOS transistor N2_2. A resistor element R2_2 is connected between the gate of the nMOS transistor N2_2 and the gate of the nMOS transistor N2_3. A resistor element R2_3 is connected between the gate of the nMOS transistor N2_3 and the gate of the nMOS transistor N2_4. The same is true for the resistor elements R2_4, R2_5, ..., R2_(n-1). Furthermore, one end of the resistor element R2_n is connected to the gate of the nMOS transistor N2_n, and the other end of the resistor element R2_n is connected to the terminal TRG.

[0119] 2.2 Operation of the Second Embodiment

[0120] When the high frequency switch 20a is switched from the off state to the on state, Figure 5 In the switch circuit 1 shown, signals SWG and RGN output from the on / off switching circuit 11 a are input to terminals TSW and TRN of the high-frequency switch 20 a , respectively.

[0121] In the high frequency switch 20a, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are turned on in sequence by the signal SWG input to the terminal TSW. In addition, the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1 are turned on in sequence by the signal RGN input to the terminal TRN. As a result, the resistor elements R1_n, R1_(n-1), R1_(n-2), ..., R1_1 are short-circuited by the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1, respectively, and the transition of the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 from off to on is accelerated. As a result, the switching of the high frequency switch 20a from the off state to the on state is accelerated.

[0122] 2.3 Effects of the Second Implementation

[0123] According to the second embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0124] Furthermore, in the second embodiment, in addition to the configuration of the first embodiment, nMOS transistors N2_1 to N2_n for short-circuiting both ends of the resistor elements R1_1 to R1_n in the high-frequency switch 20a and a signal RGN for controlling the on and off of these nMOS transistors N2_1 to N2_n are provided. Thus, the time until all the nMOS transistors N1_1 to N1_n in the high-frequency switch 20a are turned on can be shortened. As a result, the switching of the high-frequency switch 20a from the off state to the on state can be accelerated.

[0125] 2.4 Modification of the Second Embodiment

[0126] Next, a switch circuit 1 according to a modified example of the second embodiment will be described. Figure 6 It is a circuit diagram showing a configuration of a switch circuit according to a modification of the second embodiment.

[0127] In the switch circuit 1 of the modification, the high-frequency switch 20 b is different from the configuration of the second embodiment described above. Specifically, it is as follows.

[0128] The high frequency switch 20b has Figure 5 The high frequency switch 20 a shown in the figure has a structure in which the source and drain of each of the nMOS transistors N2_1 , N2_2 , N2_3 , . . . , N2_(n-1), and N2_n are reversed.

[0129] The source of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_1, and the drain of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_2. The source of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_2, and the drain of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_3. The source of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_3, and the drain of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_4. The same applies to the nMOS transistors N2_4, N2_5, ..., N2_(n-1). In addition, the source of the nMOS transistor N2_n is connected to the gate of the nMOS transistor N1_n, and the drain of the nMOS transistor N2_n is connected to the terminal TSW.

[0130] As described above, in the high-frequency switch 20b formed by swapping the sources and drains of the nMOS transistors N2_1, N2_2, N2_3, . . . , N2_(n-1), and N2_n with respect to the high-frequency switch 20a, the operation of the high-frequency switch 20b is also the same as that of the high-frequency switch 20a in the second embodiment.

[0131] 2.5 Other Modifications of the Second Embodiment

[0132] Next, a switch circuit 1 according to another modified example of the second embodiment will be described. Figure 7 It is a circuit diagram showing the configuration of a switch circuit according to another modified example of the second embodiment.

[0133] In the switch circuit 1 of another modified example, the high-frequency switch 20c has a configuration different from that of the second embodiment described above. Specifically, it is as follows.

[0134] The high frequency switch 20c has Figure 2 In addition to the structure of the high frequency switch 20 shown, for example, it also has nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), N2_n, N2_(n+1) and resistor elements R2_1, R2_2, R2_3, ..., R2_(n-1), R2_n, R2_(n+1), R2_(n+2).

[0135] The source of the nMOS transistor N2_(n+1) and one end of the resistor R2_(n+1) are connected to the terminal TSW, and the drain of the nMOS transistor N2_(n+1) is connected to the other end of the resistor R2_(n+1).

[0136] Between the first node and the gate of the nMOS transistor N1_1, the nMOS transistor N2_1 is connected in parallel with the resistor R1_1, wherein the drain of the nMOS transistor N2_(n+1) and the other end of the resistor R2_(n+1) are connected to the first node. Between the first node and the gate of the nMOS transistor N1_2, the nMOS transistor N2_2 is connected in parallel with the resistor R1_2. Between the first node and the gate of the nMOS transistor N1_3, the nMOS transistor N2_3 is connected in parallel with the resistor R1_3. Hereinafter, the nMOS transistor N2_4 is connected to the resistor R1_4, ..., the nMOS transistor N2_(n-1) is connected to the resistor R1_(n-1), and the nMOS transistor N2_n is connected to the resistor R1_n.

[0137] The gate of the nMOS transistor N2_1 is connected to the terminal TRN via the resistor elements R2_1 and R2_(n+2). The gate of the nMOS transistor N2_2 is connected to the terminal TRN via the resistor elements R2_2 and R2_(n+2). The gate of the nMOS transistor N2_3 is connected to the terminal TRN via the resistor elements R2_3 and R2_(n+2). In the following, similarly, the gate of the nMOS transistor N2_4 is connected to the terminal TRN via the resistor elements R2_4 and R2_(n+2), the gate of the nMOS transistor N2_(n-1) is connected to the terminal TRN via the resistor elements R2_(n-1) and R2_(n+2), and the gate of the nMOS transistor N2_n is connected to the terminal TRN via the resistor elements R2_n and R2_(n+2). Furthermore, the gate of the nMOS transistor N2_(n+1) is connected to the terminal TRN via the resistor element R2_(n+2).

[0138] As described above, when nMOS transistors and resistors are connected in parallel to the gates of nMOS transistors N1_1, N1_2, N1_3, ..., N1_(n-1), and N1_n, nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., and N2_1 are turned on by the signal RGN input to the terminal TRN. As a result, resistors R1_n, R1_(n-1), R1_(n-2), ..., and R1_1 are short-circuited by nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., and N2_1, respectively, and the transition of nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., and N1_1 from off to on is accelerated. As a result, the switching of the high-frequency switch 20c from the off state to the on state is accelerated.

[0139] 3. Third Implementation

[0140] Next, a semiconductor device according to a third embodiment is described. In the third embodiment, a circuit including a pMOS transistor and a resistor is added to the high frequency switch 20 according to the first embodiment. In addition, signals supplied to these pMOS transistors and resistors are prepared. In the third embodiment, descriptions of points similar to those of the switch circuit 1 according to the first embodiment in terms of structure, operation, and effects are omitted, and the description will be centered on the points of difference.

[0141] 3.1 Structure of the Third Embodiment

[0142] Figure 8 : is a circuit diagram showing the configuration of a switch circuit according to a third embodiment.

[0143] In the switch circuit 1 of the third embodiment, the on / off switching circuit 11 b and the high-frequency switch 20 d included in the switch control circuit 10 are different from those of the first embodiment.

[0144] The on / off switching circuit 11b includes a terminal TRP connected to the drains of the pMOS transistor M7 and the nMOS transistor M8. A signal RGP corresponding to the signal EP is output from the terminal TRP.

[0145] The high frequency switch 20d has Figure 2 In addition to the structure shown, the high-frequency switch 20 further includes, for example, pMOS transistors P1_1, P1_2, P1_3, ..., P1_(n-1), P1_n and resistor elements R2_1, R2_2, R2_3, ..., R2_(n-1), R2_n.

[0146] A pMOS transistor P1_1 capable of short-circuiting both ends of the resistor R1_1 is provided in the high-frequency switch 20d. A pMOS transistor P1_2 capable of short-circuiting both ends of the resistor R1_2 is provided. A pMOS transistor P1_3 capable of short-circuiting both ends of the resistor R1_3 is provided. The same applies to the pMOS transistors P1_4, P1_5, ..., P1_(n-1), and P1_n. Furthermore, resistor elements R2_1, R2_2, R2_3, ..., R2_(n-1), and R2_n are provided at the gates of the pMOS transistors P1_1, P1_2, P1_3, ..., P1_(n-1), and P1_n, respectively.

[0147] Next, the connection of the circuit elements in the high-frequency switch 20d will be described.

[0148] The source and drain of the pMOS transistor P1_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the source of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_1, and the drain of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_2. The source and drain of the pMOS transistor P1_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the source of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_2, and the drain of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_3. The source and drain of the pMOS transistor P1_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the gate of the nMOS transistor N1_3 is connected to the source of the pMOS transistor P1_3, and the gate of the nMOS transistor N1_4 is connected to the drain of the pMOS transistor P1_3. The same applies to the pMOS transistors P1_4, P1_5, ..., P1_(n-1). Furthermore, the gate of the nMOS transistor N1_n is connected to the source of the pMOS transistor P1_n, and the drain of the pMOS transistor P1_n is connected to the terminal TSW.

[0149] A resistor element R2_1 is connected between the gate of the pMOS transistor P1_1 and the gate of the pMOS transistor P1_2. A resistor element R2_2 is connected between the gate of the pMOS transistor P1_2 and the gate of the pMOS transistor P1_3. A resistor element R2_3 is connected between the gate of the pMOS transistor P1_3 and the gate of the pMOS transistor P1_4. The same is true for the resistor elements R2_4, R2_5, ..., R2_(n-1). Furthermore, one end of the resistor element R2_n is connected to the gate of the pMOS transistor P1_n, and the other end of the resistor element R2_n is connected to the terminal TRP.

[0150] 3.2 Operation of the Third Embodiment

[0151] When the high frequency switch 20d is switched from the on state to the off state, Figure 7 In the switch circuit 1 shown, signals SWG and RGP output from the on / off switching circuit 11b are input to terminals TSW and TRP of the high-frequency switch 20d.

[0152] In the high-frequency switch 20d, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are turned off in sequence by the signal SWG input to the terminal TSW. In addition, the pMOS transistors P1_n, P1_(n-1), P1_(n-2), ..., P1_1 are turned off in sequence by the signal RGP input to the terminal TRP. As a result, the transition of the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 from on to off is accelerated. As a result, the switching of the high-frequency switch 20d from the on state to the off state is accelerated.

[0153] 3.3 Effects of the Third Implementation

[0154] According to the third embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0155] Furthermore, in the third embodiment, in addition to the configuration of the first embodiment, pMOS transistors P1_1 to P1_n for electrically disconnecting both ends of the resistor elements R1_1 to R1_n in the high-frequency switch 20d and a signal RGP for controlling the on and off of these pMOS transistors P1_1 to P1_n are provided. Thus, the time until the pMOS transistors P1_1 to P1_n in the high-frequency switch 20d are turned off can be shortened. As a result, the switching of the high-frequency switch 20d from the on state to the off state can be accelerated.

[0156] 4. Fourth Implementation

[0157] Next, a semiconductor device according to a fourth embodiment is described. In the fourth embodiment, a circuit including an nMOS transistor and a resistor element and a circuit including a pMOS transistor and a resistor element are added to the high frequency switch 20 according to the first embodiment. In addition, signals supplied to the circuit including the nMOS transistor and the resistor element and the circuit including the pMOS transistor and the resistor element are prepared separately. In the fourth embodiment, descriptions of points similar to those of the structure, operation, and effects of the switch circuit 1 according to the first embodiment are omitted, and the description will be centered on the points of difference.

[0158] 4.1 Structure of the Fourth Embodiment

[0159] Fig. 9 : is a circuit diagram showing the configuration of a switch circuit according to a fourth embodiment.

[0160] In the switch circuit 1 of the fourth embodiment, the on / off switching circuit 11 c and the high-frequency switch 20 e included in the switch control circuit 10 are different from those of the first embodiment. Specifically, they are as follows.

[0161] The on / off switching circuit 11c includes a terminal TRN connected to the drains of the pMOS transistor M15 and the nMOS transistor M16. A signal RGN corresponding to the signal EN is output from the terminal TRN. The on / off switching circuit 11c also includes a terminal TRP connected to the drains of the pMOS transistor M7 and the nMOS transistor M8. A signal RGP corresponding to the signal EP is output from the terminal TRP.

[0162] The high frequency switch 20e has Figure 2 In addition to the structure shown, the high-frequency switch 20 further includes, for example, nMOS transistors N2_1, N2_2, N2_3, ..., N2_(n-1), N2_n and resistor elements R2_1, R2_2, R2_3, ..., R2_(n-1), R2_n.

[0163] The drain and source of the nMOS transistor N2_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the drain of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_1, and the source of the nMOS transistor N2_1 is connected to the gate of the nMOS transistor N1_2. The drain and source of the nMOS transistor N2_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the drain of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_2, and the source of the nMOS transistor N2_2 is connected to the gate of the nMOS transistor N1_3. The drain and source of the nMOS transistor N2_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the drain of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_3, and the source of the nMOS transistor N2_3 is connected to the gate of the nMOS transistor N1_4. The nMOS transistors N2_4, N2_5, ..., N2_(n-1) are connected in the same manner. Furthermore, the drain of the nMOS transistor N2_n is connected to the gate of the nMOS transistor N1_n, and the source of the nMOS transistor N2_n is connected to the terminal TSW.

[0164] A resistor element R2_1 is connected between the gate of the nMOS transistor N2_1 and the gate of the nMOS transistor N2_2. A resistor element R2_2 is connected between the gate of the nMOS transistor N2_2 and the gate of the nMOS transistor N2_3. A resistor element R2_3 is connected between the gate of the nMOS transistor N2_3 and the gate of the nMOS transistor N2_4. Hereinafter, resistor elements R2_4, R2_5, ..., R2_(n-1) are connected in the same manner. Furthermore, one end of the resistor element R2_n is connected to the gate of the nMOS transistor N2_n, and the other end of the resistor element R2_n is connected to the terminal TRN.

[0165] The high frequency switch 20e further includes, for example, pMOS transistors P1_1, P1_2, P1_3, . . . , P1_(n-1), P1_n, and resistor elements R3_1, R3_2, R3_3, . . . , R3_(n-1), R3_n.

[0166] The source and drain of the pMOS transistor P1_1 are connected between the gate of the nMOS transistor N1_1 and the gate of the nMOS transistor N1_2. That is, the source of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_1, and the drain of the pMOS transistor P1_1 is connected to the gate of the nMOS transistor N1_2. The source and drain of the pMOS transistor P1_2 are connected between the gate of the nMOS transistor N1_2 and the gate of the nMOS transistor N1_3. That is, the source of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_2, and the drain of the pMOS transistor P1_2 is connected to the gate of the nMOS transistor N1_3. The source and drain of the pMOS transistor P1_3 are connected between the gate of the nMOS transistor N1_3 and the gate of the nMOS transistor N1_4. That is, the source of the pMOS transistor P1_3 is connected to the gate of the nMOS transistor N1_3, and the drain of the pMOS transistor P1_3 is connected to the gate of the nMOS transistor N1_4. The pMOS transistors P1_4, P1_5, ..., P1_(n-1) are connected in the same manner. Furthermore, the source of the pMOS transistor P1_n is connected to the gate of the nMOS transistor N1_n, and the drain of the pMOS transistor P1_n is connected to the terminal TSW.

[0167] A resistor element R3_1 is connected between the gate of the pMOS transistor P1_1 and the gate of the pMOS transistor P1_2. A resistor element R3_2 is connected between the gate of the pMOS transistor P1_2 and the gate of the pMOS transistor P1_3. A resistor element R3_3 is connected between the gate of the pMOS transistor P1_3 and the gate of the pMOS transistor P1_4. Hereinafter, resistor elements R3_4, R3_5, ..., R3_(n-1) are connected in the same manner. Furthermore, one end of the resistor element R3_n is connected to the gate of the pMOS transistor P1_n, and the other end of the resistor element R3_n is connected to the terminal TRP.

[0168] 4.2 Operation of the Fourth Embodiment

[0169] When the high frequency switch 20e is switched from the off state to the on state, Fig. 9 In the switch circuit 1 shown, signals SWG and RGN output from the on / off switching circuit 11 c are input to terminals TSW and TRN of the high-frequency switch 20 e , respectively.

[0170] In the high frequency switch 20e, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are turned on in sequence by the signal SWG input to the terminal TSW. In addition, the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1 are turned on in sequence by the signal RGN input to the terminal TRN. As a result, the resistor elements R1_n, R1_(n-1), R1_(n-2), ..., R1_1 are short-circuited by the nMOS transistors N2_n, N2_(n-1), N2_(n-2), ..., N2_1, respectively, and the transition of the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 from off to on is accelerated. As a result, the switching of the high frequency switch 20e from the off state to the on state is accelerated.

[0171] On the other hand, when the high frequency switch 20e is switched from the on state to the off state, Fig. 9 In the switch circuit 1 shown, signals SWG and RGP output from the on / off switching circuit 11c are input to terminals TSW and TRP of the high-frequency switch 20e, respectively.

[0172] In the high-frequency switch 20e, the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 are turned off in sequence by the signal SWG input to the terminal TSW. In addition, the pMOS transistors P1_n, P1_(n-1), P1_(n-2), ..., P1_1 are turned off in sequence by the signal RGP input to the terminal TRP. As a result, the transition of the nMOS transistors N1_n, N1_(n-1), N1_(n-2), ..., N1_1 from on to off is accelerated. As a result, the switching of the high-frequency switch 20d from the on state to the off state is accelerated.

[0173] 4.3 Effects of the Fourth Implementation

[0174] According to the fourth embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0175] Furthermore, in addition to the configuration of the first embodiment, the fourth embodiment further includes nMOS transistors N2_1 to N2_n for short-circuiting both ends of the resistor elements R1_1 to R1_n in the high-frequency switch 20e, and a signal RGN for controlling the on and off of these nMOS transistors N2_1 to N2_n. This can shorten the time until all the nMOS transistors N1_1 to N1_n in the high-frequency switch 20e are turned on. As a result, the high-frequency switch 20e can be switched from the off state to the on state more quickly.

[0176] Furthermore, in addition to the configuration of the first embodiment, the fourth embodiment further includes pMOS transistors P1_1 to P1_n for electrically disconnecting both ends of the resistor elements R1_1 to R1_n in the high-frequency switch 20e, and a signal RGP for controlling the on and off of these pMOS transistors P1_1 to P1_n. This can shorten the time until the pMOS transistors P1_1 to P1_n in the high-frequency switch 20e are turned off. As a result, the high-frequency switch 20e can be switched from the on state to the off state more quickly.

[0177] 5. Fifth Implementation

[0178] Next, a semiconductor device according to a fifth embodiment is described. Figure 1In the wireless device WD shown in the figure, when the four switch circuits 1, 2, 3 and 4 are controlled by the control signals CNT1, 2, 3 and 4, four delay circuits 12 are required. However, since the delay circuit 12 includes the resistor element R and the capacitor element C, the occupied area of ​​the delay circuit may become large. Therefore, by using the delay circuit proposed in the fifth embodiment, the RC circuit is set as one to reduce the occupied area of ​​the delay circuit. In the fifth embodiment, the description of the same points as the structure, operation and effect of the switch circuit 1 of the first embodiment is omitted, and the description is centered on the different points.

[0179] 5.1 Structure of the Fifth Embodiment

[0180] Fig.10 : is a circuit diagram showing the configuration of a delay circuit included in a plurality of switch circuits according to the fifth embodiment.

[0181] In the plurality of switch circuits of the fifth embodiment, the delay circuit 12a included in the plurality of switch control circuits 10 is different from that in the first embodiment. The details are as follows.

[0182] The delay circuit 12a has multiple buffers B11, B12, B13 and B14, logic XOR circuits XO1, XO2, XO3, XO4 and XO5, D flip-flops DF1, DF2, DF3, DF4 and DF5, logic AND circuits AD1, AD2, AD3 and AD4, logic OR circuits OR1, OR2, OR3, OR4 and OR5, inverters IV1, IV2 and IV3, resistor elements R and capacitor elements C.

[0183] Next, the connection of the circuit elements in the delay circuit 12a will be described.

[0184] The control signals CNT1, 2, 3 and 4 are input to the first input terminals of the logical exclusive OR circuits XO1, XO2, XO3 and XO4, respectively. The control signals CNT1, 2, 3 and 4 are also input to the D input terminals of the D flip-flops DF1, DF2, DF3 and DF4, respectively. Furthermore, the control signals CNT1, 2, 3 and 4 are also input to the first input terminals of the logical AND circuits AD1, AD2, AD3 and AD4, respectively, and are input to the first input terminals of the logical OR circuits OR1, OR2, OR3 and OR4, respectively.

[0185] Control signals CNT1, 2, 3 and 4 are input to input terminals of buffers B11, B12, B13 and B14, respectively. Output terminals of buffers B11, B12, B13 and B14 are connected to second input terminals of XOR circuits XO1, XO2, XO3 and XO4, respectively.

[0186] The output terminals of the logical exclusive OR circuits XO1, XO2, XO3 and XO4 are connected to the four input terminals of the logical OR circuit OR5. The output terminal of the logical OR circuit OR5 is connected to the clock input terminal of the D flip-flop DF5. The Q inverting output terminal of the D flip-flop DF5 is connected to the D input terminal.

[0187] The Q output terminal of the D flip-flop DF5 is connected to the first input terminal of the logic XOR circuit XO5 via the inverter IV1, the resistor R, and the inverter IV2. The first electrode of the capacitor C is connected to the node between the resistor R and the inverter IV2, and the second electrode of the capacitor C is connected to the ground voltage GND node. The Q output terminal of the D flip-flop DF5 is also connected to the second input terminal of the logic XOR circuit XO5.

[0188] The output terminal of the logic XOR circuit XO5 is connected to the clock input terminal of the D flip-flops DF1, DF2, DF3 and DF4 via the inverter IV3. The Q output terminal of each of the D flip-flops DF1, DF2, DF3 and DF4 is connected to the second input terminal of the logic AND circuits AD1, AD2, AD3 and AD4, and is connected to the second input terminal of the logic OR circuits OR1, OR2, OR3 and OR4.

[0189] Furthermore, signals EP1 and EN1 are output from the output terminals of the AND circuit AD1 and the OR circuit OR1, respectively. Signals EP2 and EN2 are output from the output terminals of the AND circuit AD2 and the OR circuit OR2, respectively. Signals EP3 and EN3 are output from the output terminals of the AND circuit AD3 and the OR circuit OR3, respectively. Furthermore, signals EP4 and EN4 are output from the output terminals of the AND circuit AD4 and the OR circuit OR4, respectively.

[0190] 5.2 Operation of the Fifth Embodiment

[0191] use Fig.10 The operation of the delay circuit 12a in the fifth embodiment will be described.

[0192] The delay circuit 12a is input with control signals CNT1, CNT2, CNT3 and CNT4 which respectively control the switch circuits 1, 2, 3 and 4. For example, as the control signals CNT1 to CNT4, Fig.10The signal waveforms shown in (1a), (2a), (3a) and (4a) are input to buffers B11, B12, B13 and B14, respectively. Then, through the logic circuit and an RC circuit provided at the output stage of buffers B11 to B14, the signal waveforms shown in (1b), (2b), (3b) and (4b) are output from circuits AD1 and OR1, AD2 and OR2, AD3 and OR3, and AD4 and OR4, respectively, as signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4.

[0193] Then, the signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4 output from the delay circuit 12a are respectively input to the on / off switching circuits 11 in the switch circuits 1, 2, 3, and 4 to generate the signal SWG.

[0194] In addition, here, an example is shown in which buffers B11 to B14 each have a three-stage buffer, but if the signal delay required for the circuit operation of the subsequent stage can be generated, buffers B11 to B14 can also be a one-stage or two-stage buffer, or a four-stage or more buffer. Also, here, a delay circuit is shown that generates a signal delay using an RC circuit including a resistor R and a capacitor C, but if the delay required for signals EP1 to 4 and signals EN1 to 4 can be generated only with a multi-stage buffer, the delay circuit can be formed only with a multi-stage buffer without using an RC circuit. This is also the same for the delay circuit described later.

[0195] 5.3 Effects of the Fifth Implementation

[0196] According to the fifth embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0197] Furthermore, in the fifth embodiment, a plurality of delay circuits for controlling a plurality of switch circuits are formed by one RC circuit. Thus, it is possible to prevent an increase in the occupied area that would otherwise occur if a plurality of delay circuits were provided, and to reduce the occupied area of ​​the delay circuits. In addition, an example in which four delay circuits are formed by one RC circuit is shown here, but the invention is not limited thereto. It is also possible to form delay circuits other than four by one RC delay circuit.

[0198] 6. Sixth Implementation

[0199] Next, the semiconductor device of the sixth embodiment is described. There is a case where there are multiple switch circuits to which the power supply circuit (for example, a charge pump) 8 supplies the voltages Vp and Vn, and there are multiple switch circuits that are switched simultaneously. There is a case where the more switch circuits that are turned on or off simultaneously, the greater the change in the voltages Vp and Vn, and the longer the switching time between on and off. In the sixth embodiment, the delay time in the delay circuit is optimized according to the number of switching of the switch circuits, and the switching speed is increased at the number of switching of each switch circuit.

[0200] 6.1 Structure of the Sixth Embodiment

[0201] Fig.11 : is a circuit diagram showing the configuration of a delay circuit included in a plurality of switch circuits according to the sixth embodiment.

[0202] In the plurality of switch circuits of the sixth embodiment, the delay circuit 12 b included in the plurality of switch control circuits 10 is different from that in the first embodiment.

[0203] The delay circuit 12b has multiple buffers B11, B12, B13, B14, B15 and B16, logic XOR circuits XO1, XO2, XO3, XO4 and XO5, D flip-flops DF1, DF2, DF3, DF4, DF5, DF6, DF7, DF8 and DF9, logic AND circuits AD1, AD2, AD3 and AD4, logic OR circuits OR1, OR2, OR3, OR4 and OR5, inverters IV1, IV2 and IV3, variable resistance elements VR, capacitance elements C and counting circuit CO.

[0204] Next, the connection of the circuit elements in the delay circuit 12b will be described.

[0205] The control signals CNT1, 2, 3 and 4 are input to the first input terminals of the logical exclusive OR circuits XO1, XO2, XO3 and XO4, respectively. The control signals CNT1, 2, 3 and 4 are also input to the D input terminals of the D flip-flops DF1, DF2, DF3 and DF4, respectively. Furthermore, the control signals CNT1, 2, 3 and 4 are also input to the first input terminals of the logical AND circuits AD1, AD2, AD3 and AD4, respectively, and are input to the first input terminals of the logical OR circuits OR1, OR2, OR3 and OR4, respectively.

[0206] Control signals CNT1, 2, 3 and 4 are input to input terminals of buffers B11, B12, B13 and B14, respectively. Output terminals of buffers B11, B12, B13 and B14 are connected to second input terminals of XOR circuits XO1, XO2, XO3 and XO4, respectively.

[0207] The output terminals of the logical exclusive OR circuits XO1, XO2, XO3 and XO4 are respectively connected to the four input terminals of the logical OR circuit OR5. The output terminals of the logical exclusive OR circuits XO1, XO2, XO3 and XO4 are also respectively connected to the D input terminals of the D flip-flops DF5, DF6, DF7 and DF8. The Q output terminals of the D flip-flops DF5, DF6, DF7 and DF8 are respectively connected to the input terminals of the counting circuit CO. The output terminal of the counting circuit CO is input to the control terminal of the variable resistance element VR. The counting circuit CO counts the number of rises and falls of the signals CNT1, CNT2, CNT3 and CNT4 using the signal output from the Q output terminal of the D flip-flops DF5 to DF8, and outputs a signal corresponding to the count number to the control terminal. The variable resistance element VR makes the resistance value variable according to the signal input to the control terminal. In addition, the number of rises and falls is equivalent to the number of switching of the high-frequency switch.

[0208] The output terminal of the logic OR circuit OR5 is connected to the clock input terminal of the D flip-flop DF9 via buffers B15 and B16. The Q inverting output terminal of the D flip-flop DF5 is connected to the D input terminal. The node between the buffers B15 and B16 is connected to the clock input terminals of the D flip-flops DF5, DF6, DF7 and DF8, respectively.

[0209] The Q output terminal of the D flip-flop DF9 is connected to the first input terminal of the logic exclusive OR circuit XO5 via the inverter IV1, the variable resistance element VR, and the inverter IV2. The first electrode of the capacitor C is connected to the node between the variable resistance element VR and the inverter IV2, and the second electrode of the capacitor C is connected to the ground voltage GND node. The Q output terminal of the D flip-flop DF9 is connected to the second input terminal of the logic exclusive OR circuit XO5.

[0210] The output terminal of the logical exclusive OR circuit XO5 is input to the clock input terminal of the D flip-flops DF1, DF2, DF3 and DF4 via the inverter IV3. The Q output terminal of each of the D flip-flops DF1, DF2, DF3 and DF4 is connected to the second input terminal of the logical AND circuits AD1, AD2, AD3 and AD4, and is connected to the second input terminal of the logical OR circuits OR1, OR2, OR3 and OR4, respectively.

[0211] Furthermore, signals EP1 and EN1 are output from the output terminals of the AND circuit AD1 and the OR circuit OR1, respectively. Signals EP2 and EN2 are output from the output terminals of the AND circuit AD2 and the OR circuit OR2, respectively. Signals EP3 and EN3 are output from the output terminals of the AND circuit AD3 and the OR circuit OR3, respectively. Furthermore, signals EP4 and EN4 are output from the output terminals of the AND circuit AD4 and the OR circuit OR4, respectively.

[0212] 6.2 Operation of the Sixth Embodiment

[0213] use Fig.11 and Fig.12 The operation of the delay circuit 12b in the sixth embodiment will be described. Fig.12 1 is a timing chart showing the operation of the switch control circuit 10 in the switch circuit according to the sixth embodiment.

[0214] The delay circuit 12b is input with control signals CNT1, CNT2, CNT3 and CNT4 which respectively control the switch circuits 1, 2, 3 and 4. For example, as the control signals CNT1 to CNT4, Fig.11 The signal waveforms shown in (1c), (2c), (3c) and (4c) are input to the buffers B11, B12, B13 and B14, respectively. Then, through the logic circuit, the counting circuit CO and the RC circuit including the variable resistance element VR provided at the output stage of the buffers B11 to B14, the signal waveforms shown in (1d), (2d), (3d) and (4d) are output from the circuits AD1 and OR1, AD2 and OR2, AD3 and OR3 and AD4 and OR4, respectively, as the signals EP1 and EN1, EP2 and EN2, EP3 and EN3 and EP4 and EN4.

[0215] Then, the signals EP1 and EN1, EP2 and EN2, EP3 and EN3, and EP4 and EN4 output from the delay circuit 12b are input to the on / off switching circuits 11 in the switch circuits 1, 2, 3, and 4, respectively, to generate the signal SWG.

[0216] Here, if Fig.12 As shown, for example, when the control signal CNT1 rises from "L" to "H" at time t1, the signal EN1 rises from "L" to "H" at the same time t1. After that, at time t2b, the signal EP1 rises from "L" to "H". In addition, for example, at time t1, the control signal CNT2 still maintains "L", CNT3 drops from "H" to "L", and CNT4 still maintains "H". The period of time t1-t2b (that is, the transition period from the off state to the on state) changes according to the number of rises and the number of falls in the signals CNT1, CNT2, CNT3 and CNT4 combined. The number of rises and falls combined is equivalent to the number of switching of the high-frequency switch. The number of rises is also called the number of transitions from "L" to "H", and the number of falls is also called the number of transitions from "H" to "L".

[0217] In addition, here, the period of time t1-t2b (i.e., the transition period from the disconnected state to the connected state) is changed according to the sum of the number of increases and the number of decreases, but the transition period from the disconnected state to the connected state may be changed according to the number of increases, and the transition period from the connected state to the disconnected state may be changed according to the number of decreases.

[0218] In the delay circuit 12b, if the number of rising and falling is large, that is, the number of switching of the high-frequency switch is large, the resistance value of the variable resistance element VR becomes large, and the time period t1-t2b is set to be long. On the other hand, if the number of rising and falling is small, that is, the number of switching of the high-frequency switch is small, the resistance value of the variable resistance element VR becomes small, and the time period t1-t2b is set to be short. Thus, the switching time of the high-frequency switch can be set to an appropriate time, that is, the shortest.

[0219] 6.3 Effects of the Sixth Implementation

[0220] According to the sixth embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0221] Furthermore, in the sixth embodiment, when controlling a plurality of switch circuits, the delay time in the delay circuit can be minimized according to the number of on and off switching of the high frequency switches in the plurality of switch circuits. Thus, the on and off switching of the high frequency switches in the switch circuits can be accelerated.

[0222] 6.4 Modification of the Sixth Embodiment

[0223] Next, a switch circuit according to a modified example of the sixth embodiment will be described. Fig.13 : is a circuit diagram showing the configuration of a delay circuit included in a switch circuit according to a modification of the sixth embodiment.

[0224] In the plurality of switch circuits of the modification, the delay circuit 12 c included in the plurality of switch control circuits 10 is different from that in the sixth embodiment.

[0225] The delay circuit 12c has multiple buffers B11, B12, B13, B14, B15 and B16, logical exclusive OR circuits XO1, XO2, XO3, XO4 and XO5, D flip-flops DF1, DF2, DF3, DF4, DF5, DF6, DF7, DF8 and DF9, logical AND circuits AD1, AD2, AD3 and AD4, logical OR circuits OR1, OR2, OR3, OR4 and OR5, inverters IV1, IV2 and IV3, resistors R1, R2, R3 and R4, switch elements S1, S2, S3 and S4 and capacitor element C.

[0226] Next, the connection of the circuit elements in the delay circuit 12c will be described.

[0227] The Q inverting output terminals of the D flip-flops DF5 , DF6 , DF7 and DF8 are respectively connected to the control terminals of the switch elements S1 , S2 , S3 and S4 .

[0228] The output end of the inverter IV1 is connected to the input end of the inverter IV2 via four resistor elements R1, R2, R3 and R4 connected in series. One end of the switch element S1 is connected to one end of the resistor element R1, and the other end of the switch element S1 is connected to the other end of the resistor element R1. One end of the switch element S2 is connected to one end of the resistor element R2, and the other end of the switch element S2 is connected to the other end of the resistor element R2. One end of the switch element S3 is connected to one end of the resistor element R3, and the other end of the switch element S3 is connected to the other end of the resistor element R3. One end of the switch element S4 is connected to one end of the resistor element R4, and the other end of the switch element S4 is connected to the other end of the resistor element R4.

[0229] A first electrode of a capacitor C is connected to a node between the resistor R4 and the inverter IV2 , and a second electrode of the capacitor C is connected to a ground voltage GND node. Other connections are the same as those in the sixth embodiment.

[0230] Fig.14 Detailed circuit diagrams of the switch elements S1, S2, S3 and S4 are shown in FIG. The switch elements S1, S2, S3 and S4 each have an nMOS transistor N31, a pMOS transistor P31 and an inverter IV11. The signals output from the Q inverting output terminals of the D flip-flops DF5, DF6, DF7 and DF8 are input to the gate of the nMOS transistor N31 of the switch elements S1, S2, S3 and S4 and the input terminal of the inverter IV11. The output terminal of the inverter IV11 is connected to the gate of the pMOS transistor P31. The switch elements S1, S2, S3 and S4 are set to one of the connected state and the disconnected state according to the signals input to the control terminal, i.e., the gate of the nMOS transistor N31 and the inverter IV11.

[0231] In the delay circuit 12c, Fig.12 The period from time t1 to time t2b shown varies depending on the number of rising and falling edges of the signals CNT1, CNT2, CNT3, and CNT4.

[0232] If the number of rising and falling of signals CNT1, CNT2, CNT3 and CNT4 is large, that is, the number of switching of high-frequency switches is large, the number of switch elements S1 to S4 set to the cut-off state increases. Therefore, the resistance value of the circuit including switch elements S1 to S4 and resistor elements R1 to R4 increases. As a result, the period of time t1-t2b is set to be long.

[0233] In addition, if the number of rises and falls of the signals CNT1, CNT2, CNT3, and CNT4 is small, that is, the number of switching of the high-frequency switch is small, the number of switch elements set to the connection state among the switch elements S1 to S4 increases. Therefore, the resistance value of the circuit including the switch elements S1 to S4 and the resistor elements R1 to R4 becomes smaller. As a result, the period of time t1-t2b is set short. Through these controls, the switching time of the high-frequency switch can be set to an appropriate time, that is, the shortest.

[0234] 7. Seventh Implementation Method

[0235] Next, a semiconductor device according to a seventh embodiment is described. In the seventh embodiment, the pMOS transistor M4 and the diode D2 are deleted from the switch control circuit 10 of the first embodiment. In the seventh embodiment, description of the same points as the structure, operation, and effects of the switch circuit 1 of the first embodiment is omitted, and the description will be centered on the different points.

[0236] 7.1 Structure of the Seventh Embodiment

[0237] Fig.15 It is a circuit diagram showing the configuration of a switch circuit according to the seventh embodiment.

[0238] In the switch circuit 1 of the seventh embodiment, the configuration of the on / off switching circuit 11 d included in the switch control circuit 10 is different from that of the first embodiment.

[0239] The on / off switching circuit 11d is Figure 2 The on / off switching circuit 11 shown has a structure in which the pMOS transistor M4 and the diode D2 are deleted.

[0240] 7.2 Operations of the Seventh Implementation Method

[0241] Fig.16 11 is a circuit diagram showing a part of the operation of the on / off switching circuit 11 d in the switch circuit according to the seventh embodiment.

[0242] In the seventh embodiment, when the high frequency switch 20 is switched from the on state to the off state, or from the off state to the on state, the Figure 3 The signals shown are the same as the signals EP and EN.

[0243] exist Figure 2 In the on / off switching circuit 11 of the first embodiment shown in FIG. 1 , when the high frequency switch 20 is switched from the on state to the off state, as shown in FIG. Fig.16 As shown in (b), the charge of the voltage Vp (for example, 3.5 V) in the signal SWG flows to the ground voltage GND node (for example, 0 V) ​​through the pMOS transistor M4 and the diode D2.

[0244] In the on / off switching circuit 11d of the seventh embodiment, when the high frequency switch 20 is switched from the on state to the off state, during the period from time t3 to time t4, as shown in FIG. Fig.16 As shown in (a), the charge of the voltage Vp (for example, 3.5V) in the signal SWG flows to the node connected to the source of the pMOS transistor M1 through the parasitic diode PD1 present in the pMOS transistor M1. At this time, the node connected to the source of the pMOS transistor M1 is set to the ground voltage GND (for example, 0V). As a result, the signal SWG drops from the voltage Vp to the ground voltage GND. In addition, the period from time t3 to t4 is a period when the signal EP is "L" and the signal EN is "H".

[0245] The operation when the high-frequency switch 20 is switched from the off state to the on state is the same as that of the first embodiment.

[0246] 7.3 Effects of the Seventh Implementation Method

[0247] According to the seventh embodiment, it is possible to provide a semiconductor device capable of speeding up the switching between on and off of a high-frequency switch.

[0248] Furthermore, in the seventh embodiment, when the high-frequency switch 20 is switched from the on state to the off state, that is, when the signal SWG is switched from the voltage Vp to the voltage Vn, by setting the period in which the signal EP is set to "L" and the signal EN is set to "H" (the period from time t3 to time t4), the charge of the voltage Vp in the signal SWG can be discharged to the ground voltage GND via the parasitic diode PD1 present in the pMOS transistor M1 during this period.

[0249] Therefore, it is possible to Figure 2 The structure of the first embodiment shown above is obtained by removing the pMOS transistor M4 and the diode D2 to provide the structure of the seventh embodiment.

[0250] 8. Eighth Implementation

[0251] Next, a semiconductor device according to an eighth embodiment is described. In the eighth embodiment, the nMOS transistor M3, the diode D1, the pMOS transistor M4, and the diode D2 are deleted from the switch control circuit 10 of the first embodiment. In the eighth embodiment, description of the same points as those of the switch circuit 1 of the first embodiment in terms of structure, operation, and effect is omitted, and the description will be centered on the different points.

[0252] 8.1 Structure of the Eighth Embodiment

[0253] Fig.17 It is a circuit diagram showing the configuration of a switch circuit according to an eighth embodiment.

[0254] In the switch circuit 1 of the eighth embodiment, the configuration of the on / off switching circuit 11 e included in the switch control circuit 10 is different from that of the first embodiment.

[0255] The on / off switching circuit 11e is Figure 2 The configuration of the on / off switching circuit 11 shown is obtained by eliminating the nMOS transistor M3, the diode D1, the pMOS transistor M4, the diode D2, the pMOS transistor M13, the nMOS transistor M14, the pMOS transistor M15, and the nMOS transistor M16.

[0256] 8.2 Operations of the Eighth Implementation

[0257] Fig.18 1 is a circuit diagram showing a part of the operation of the on / off switching circuit 11 e in the switch circuit according to the eighth embodiment.

[0258] In the eighth embodiment, when the high frequency switch 20 is switched from the on state to the off state, or from the off state to the on state, the high frequency switch 20 is supplied with Figure 3 The signals shown are the same as the signals EP and EN.

[0259] exist Figure 2 In the on / off switching circuit 11 of the first embodiment shown in FIG. 1 , when the high frequency switch 20 is switched from the off state to the on state, as shown in FIG. Fig.18 As shown in (b), the signal SWG rises from the voltage Vn (eg, −3.5 V) to the power supply voltage VDD (eg, 1.2 V) by the current flowing from the power supply voltage VDD node to the terminal TSW via the diode D1 and the nMOS transistor M3.

[0260] In the on / off switching circuit 11e of the eighth embodiment, when the high frequency switch 20 is switched from the off state to the on state, during the period from time t1 to time t2, as shown in FIG. Fig.18As shown in (a), the current flows from the node connected to the source of the nMOS transistor M2 to the terminal TSW through the parasitic diode PD2 present in the nMOS transistor M2. At this time, the node connected to the source of the nMOS transistor M2 is set to the ground voltage GND. As a result, the signal SWG rises from the voltage Vn (e.g., -3.5V) to the ground voltage GND (e.g., 0V). In addition, the period from time t1 to t2 is the period when the signal EP is "L" and the signal EN is "H".

[0261] The operation when the high-frequency switch 20 is switched from the on state to the off state is the same as that of the seventh embodiment.

[0262] 8.3 Effects of the Eighth Implementation Method

[0263] According to the eighth embodiment, it is possible to provide a semiconductor device capable of increasing the speed of switching on and off of a high-frequency switch.

[0264] Furthermore, in the eighth embodiment, when the high frequency switch 20 is switched from the off state to the on state, that is, when the signal SWG is switched from the voltage Vn to the voltage Vp, by setting the period during which the signal EP is set to "L" and the signal EN is set to "H" (the period from time t1 to time t2), a current is caused to flow from the node connected to the source of the nMOS transistor M2 to the terminal TSW via the parasitic diode PD2 present in the nMOS transistor M2 during this period. Thus, the signal SWG can be increased from the voltage Vn to the ground voltage GND.

[0265] In addition, when the high-frequency switch 20 is switched from the on state to the off state, similarly to the seventh embodiment, by setting the period during which the signal EP is set to "L" and the signal EN is set to "H" (the period from time t3 to time t4), the charge of the voltage Vp in the signal SWG can be discharged to the ground voltage GND via the parasitic diode PD1 present in the pMOS transistor M1.

[0266] Through the above, we can Figure 2 The structure of the first embodiment shown is obtained by removing the nMOS transistor M3 , the diode D1 , the pMOS transistor M4 , the diode D2 , the pMOS transistor M13 , the nMOS transistor M14 , the pMOS transistor M15 , and the nMOS transistor M16 to obtain the structure of the eighth embodiment.

[0267] 9. Ninth Implementation Method

[0268] Next, a semiconductor device according to a ninth embodiment is described. In the second embodiment, the signal RGN input to the gate of the nMOS transistor M3 in the switch control circuit 10 is set to a signal corresponding to the signal EN, but in the ninth embodiment, the signal RGN input to the gate of the nMOS transistor M3 is set to a signal corresponding to the signal EP. In the ninth embodiment, description of the same points as the structure, operation, and effects of the switch circuit 1 of the second embodiment is omitted, and the description will focus on the different points.

[0269] 9.1 Structure of the Ninth Embodiment

[0270] Fig.19 : is a circuit diagram showing the configuration of a switch circuit according to a ninth embodiment.

[0271] In the switch circuit 1 of the ninth embodiment, the configuration of the on / off switching circuit 11f included in the switch control circuit 10 is different from that of the second embodiment.

[0272] The on / off switching circuit 11f is Figure 5 The configuration of the on / off switching circuit 11a shown is obtained by removing the wiring connecting the output end of the buffer B4 to the gates of the pMOS transistor M13 and the nMOS transistor M14, the pMOS transistor M4, and the diode D2, and adding a level shifter LS3.

[0273] The input terminal of the level shifter LS3 receives the signal EP. The output terminal of the level shifter LS3 is connected to the gates of the pMOS transistor M13 and the nMOS transistor M14. The level shifter LS3 converts the signal EP to a voltage level using the power supply voltage VDD and the voltage Vn as power supplies.

[0274] 9.2 Operations of the Ninth Implementation Method

[0275] Fig. 20 11 is a circuit diagram showing a part of the operation of the on / off switching circuit 11f in the switch circuit according to the ninth embodiment.

[0276] In the ninth embodiment, when the high frequency switch 20a is switched from the on state to the off state, or from the off state to the on state, the high frequency switch 20a is supplied with Figure 3 The signals shown are the same as the signals EP and EN.

[0277] exist Figure 5 In the on / off switching circuit 11a of the second embodiment shown in FIG. 1 , when the high frequency switch 20a is switched from the on state to the off state, as shown in FIG. Fig. 20As shown in (b), a leakage current flows from the power supply voltage VDD node to the node connected to the source of the pMOS transistor M1 through the diode D1, the nMOS transistor M3, and the parasitic diode PD1 of the pMOS transistor M1. This leakage current prevents the voltage drop of the signal SWG when switching from the on state to the off state. Therefore, it becomes a cause of delay in switching from the on state to the off state of the high-frequency switch 20a.

[0278] In the on / off switching circuit 11f of the ninth embodiment, when the high frequency switch 20a is switched from the on state to the off state, the switching of the signal RGN from "H" (for example, VDD) to "L" (for example, Vn) is controlled according to the timing of the signal EP. That is, the switching of the signal RGN from "H" to "L" is made to coincide with the switching timing of the signal EP. As a result, the timing of the signal RGN switching from "H" to "L" is accelerated, such as Fig. 20 As shown in (a), the nMOS transistor M3 is turned off to stop the current from the power supply voltage VDD node to the terminal TSW, and the charge in the terminal TSW is discharged to the node connected to the source of the pMOS transistor M1 through the parasitic diode PD1 of the pMOS transistor M1. Thus, the action that hinders the voltage drop of the signal SWG is eliminated, and the speed of switching the signal SWG from the voltage Vp to the voltage Vn is accelerated.

[0279] The operation when the high-frequency switch 20a is switched from the off state to the on state is the same as that of the seventh embodiment.

[0280] 9.3 Effects of the Ninth Implementation Method

[0281] According to the ninth embodiment, it is possible to provide a semiconductor device capable of speeding up the switching between on and off of a high-frequency switch.

[0282] Furthermore, in the ninth embodiment, when the high frequency switch 20a is switched from the on state to the off state, that is, when the signal SWG is switched from the voltage Vp to the voltage Vn, the switching of the signal RGN from "H" to "L" is made to coincide with the switching timing of the signal EP. Thus, the current flowing from the power supply voltage VDD node to the terminal TSW via the nMOS transistor M3 is stopped, and the switching of the signal SWG from the voltage Vp to the voltage Vn is accelerated. As a result, the switching of the high frequency switch 20a from the on state to the off state can be accelerated.

[0283] 10. Others

[0284] The semiconductor device of the above-mentioned embodiment can adopt the following embodiments.

[0285] 1. A semiconductor device comprising:

[0286] a first transistor (M1) supplied with a first voltage (Vp) higher than a power supply voltage (VDD), and supplying the first voltage to a first terminal (TSW);

[0287] a second transistor (M2) supplied with a second voltage (Vn) lower than a ground voltage (GND), and supplying the second voltage to the first terminal;

[0288] a third transistor (M3) supplied with the power supply voltage and supplying the power supply voltage to the first terminal;

[0289] a fourth transistor (M4), supplied with the ground voltage, supplying the ground voltage to the first terminal;

[0290] a first level shifter (LS1) which, when the first signal (EP) is the power supply voltage, converts the power supply voltage into the first voltage (Vp) and outputs a second signal (RGP); and

[0291] The second level shifter (LS2) converts the ground voltage into the second voltage (Vn) and outputs a fourth signal (RGN) when the third signal (EN) is the ground voltage.

[0292] When the first voltage is output from the first terminal,

[0293] the power supply voltage is supplied from the third transistor to the first terminal according to the fourth signal, and then the first voltage is supplied from the first transistor to the first terminal according to the second signal,

[0294] When the second voltage is output from the first terminal,

[0295] The ground voltage is supplied from the fourth transistor to the first end according to the second signal, and then the second voltage is supplied from the second transistor to the first end according to the fourth signal.

[0296] 2. The semiconductor device according to item 1 above, wherein:

[0297] It also has a high frequency switch (20),

[0298] The high frequency switch has:

[0299] a second terminal (T1) and a third terminal (T2);

[0300] a first plurality of transistors connected in series between the second terminal and the third terminal; and

[0301] The first plurality of resistor elements are connected in series between the gate of a fifth transistor connected to the second end among the first plurality of transistors and the first end, and are respectively connected between the gates of the first plurality of transistors.

[0302] 3. The semiconductor device according to 2 above, wherein:

[0303] It also has a fourth terminal (TRN) for outputting the fourth signal,

[0304] The high frequency switch also has:

[0305] a second plurality of transistors connected in series between the gate of the fifth transistor and the first end; and

[0306] The second plurality of resistor elements are connected in series between the gate of a sixth transistor connected to the gate of the fifth transistor among the second plurality of transistors and the fourth end, and are respectively connected between the gates of the second plurality of transistors.

[0307] 4. The semiconductor device according to 2 above, wherein:

[0308] further comprising a fifth terminal (TRP) for outputting the second signal,

[0309] The high frequency switch also has:

[0310] A third plurality of transistors connected in series between the gate of the fifth transistor and the first end; and

[0311] The third plurality of resistor elements are connected in series between the gate of a seventh transistor connected to the gate of the fifth transistor among the third plurality of transistors and the fifth end, and are respectively connected between the gates of the third plurality of transistors.

[0312] 5. The semiconductor device according to item 1 above, further comprising:

[0313] a high frequency switch having a second terminal and a third terminal; and

[0314] The fourth terminal (TRN) outputs the fourth signal,

[0315] The high frequency switch has:

[0316] a first plurality of transistors connected in series between the second terminal and the third terminal;

[0317] A second plurality of transistors and a first plurality of resistor elements are connected in parallel between respective gates of the first plurality of transistors and the first end; and

[0318] The second plurality of resistor elements are respectively connected between the gates of the second plurality of transistors and the fourth end.

[0319] 6. The semiconductor device according to any one of 1 to 5 above, wherein:

[0320] A power supply circuit (8) for generating the first voltage and the second voltage is also provided.

[0321] 7. The semiconductor device according to item 6 above, wherein:

[0322] The power supply circuit includes a charge pump.

[0323] 8. The semiconductor device according to item 1 above, further comprising:

[0324] a first diode (D1) connected between a node supplied with the power supply voltage and the third transistor; and

[0325] A second diode (D2) is connected between a node to which the ground voltage is supplied and the fourth transistor.

[0326] 9. The semiconductor device according to item 1 above, wherein:

[0327] A delay circuit (12) is also provided, and the delay circuit (12) delays a control signal (CNT) to output the first signal and the third signal.

[0328] 10. A semiconductor device comprising:

[0329] A plurality of switch circuits (1); and

[0330] A delay circuit (12a) delays a plurality of control signals corresponding to the plurality of switch circuits,

[0331] The plurality of switch circuits respectively include:

[0332] A first transistor is supplied with a first voltage higher than a power supply voltage and supplies the first voltage to a first terminal;

[0333] a second transistor supplied with a second voltage lower than a ground voltage and supplying the second voltage to the first terminal;

[0334] a third transistor, supplied with the power supply voltage, supplying the power supply voltage to the first terminal;

[0335] a fourth transistor, supplied with the ground voltage, supplying the ground voltage to the first terminal;

[0336] a first level shifter, which, when the first signal is the power supply voltage, converts the power supply voltage into the first voltage and outputs a second signal; and

[0337] The second level shifter converts the ground voltage into the second voltage and outputs a fourth signal when the third signal is the ground voltage.

[0338] When the first voltage is output from the first terminal,

[0339] the power supply voltage is supplied from the third transistor to the first terminal according to the fourth signal, and then the first voltage is supplied from the first transistor to the first terminal according to the second signal,

[0340] When the second voltage is output from the first terminal,

[0341] the ground voltage is supplied from the fourth transistor to the first terminal according to the second signal, and then the second voltage is supplied from the second transistor to the first terminal according to the fourth signal,

[0342] The delay circuit includes: a first circuit for generating a delay signal according to the plurality of control signals; and a plurality of logic circuits for generating the first signal and the third signal using each of the plurality of control signals and the delay signal.

[0343] Each of the plurality of logic circuits outputs each of the plurality of control signals as one of the first signal and the third signal.

[0344] Each of the plurality of logic circuits delays each of the plurality of control signals using the delay signal, and outputs each of the plurality of control signals after the delay as the other of the first signal and the third signal.

[0345] 11. The semiconductor device according to 10 above, wherein:

[0346] The first circuit includes a set of a resistor element and a capacitor element.

[0347] 12. The semiconductor device according to 10 above, wherein:

[0348] The plurality of control signals maintain a voltage level of either a low level or a high level,

[0349] The first circuit has:

[0350] a counting circuit for counting the number of transitions of the plurality of control signals from a low level to a high level and the number of transitions from a high level to a low level; and

[0351] A variable resistance element has a resistance value that is variable according to the number of transitions counted by the counting circuit.

[0352] 13. The semiconductor device according to 10 above, wherein:

[0353] The plurality of control signals maintain a voltage level of either a low level or a high level,

[0354] The first circuit includes a plurality of triggers provided corresponding to the plurality of control signals, a plurality of switch elements and a plurality of resistor elements provided corresponding to the plurality of triggers, and a capacitor element.

[0355] The plurality of resistor elements are connected in series, and one end and the other end of each of the plurality of switch elements are connected to one end and the other end of each of the plurality of resistor elements.

[0356] Each of the plurality of triggers outputs a fifth signal when each of the plurality of control signals changes from a low level to a high level, or changes from a high level to a low level.

[0357] Each of the plurality of switch elements is set to one of a connected state and a disconnected state according to the fifth signal.

[0358] 14. The semiconductor device according to any one of 10 to 13 above, wherein:

[0359] A power supply circuit for generating the first voltage and the second voltage is further provided.

[0360] The semiconductor device of the above-described embodiment can be applied to an antenna tuning switch of a portable terminal such as a mobile phone or a smartphone, a switch for a base station, a phase shift switch, and the like.

[0361] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: A first transistor is supplied with a first voltage higher than a power supply voltage and supplies the first voltage to a first terminal; a second transistor supplied with a second voltage lower than a ground voltage and supplying the second voltage to the first terminal; a third transistor, supplied with the power supply voltage, supplying the power supply voltage to the first terminal; a fourth transistor, supplied with the ground voltage, supplying the ground voltage to the first terminal; a first level shifter, which, when the first signal is the power supply voltage, converts the power supply voltage into the first voltage and outputs a second signal; as well as The second level shifter converts the ground voltage into the second voltage and outputs a fourth signal when the third signal is the ground voltage. When the first voltage is output from the first terminal, the power supply voltage is supplied from the third transistor to the first terminal according to the fourth signal, and then the first voltage is supplied from the first transistor to the first terminal according to the second signal, When the second voltage is output from the first terminal, The ground voltage is supplied from the fourth transistor to the first end according to the second signal, and then the second voltage is supplied from the second transistor to the first end according to the fourth signal.

2. The semiconductor device according to claim 1, wherein: It also has high frequency switching. The high frequency switch has: The second and third ends; a first plurality of transistors connected in series between the second terminal and the third terminal; and The first plurality of resistor elements are connected in series between the gate of a fifth transistor connected to the second end among the first plurality of transistors and the first end, and are respectively connected between the gates of the first plurality of transistors.

3. The semiconductor device according to claim 2, wherein: further comprising a fourth terminal for outputting the fourth signal, The high frequency switch also has: a second plurality of transistors connected in series between the gate of the fifth transistor and the first end; and The second plurality of resistor elements are connected in series between the gate of a sixth transistor connected to the gate of the fifth transistor among the second plurality of transistors and the fourth end, and are respectively connected between the gates of the second plurality of transistors.

4. The semiconductor device according to claim 2, wherein: further comprising a fifth terminal for outputting the second signal, The high frequency switch also has: A third plurality of transistors connected in series between the gate of the fifth transistor and the first end; and The third plurality of resistor elements are connected in series between the gate of a seventh transistor connected to the gate of the fifth transistor among the third plurality of transistors and the fifth end, and are respectively connected between the gates of the third plurality of transistors.

5. The semiconductor device according to claim 1, wherein: Also available: a high frequency switch having a second terminal and a third terminal; and The fourth terminal outputs the fourth signal. The high frequency switch has: a first plurality of transistors connected in series between the second terminal and the third terminal; A second plurality of transistors and a first plurality of resistor elements are connected in parallel between respective gates of the first plurality of transistors and the first end; as well as The second plurality of resistor elements are respectively connected between the gates of the second plurality of transistors and the fourth end.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that A power supply circuit for generating the first voltage and the second voltage is further provided.

7. The semiconductor device according to claim 6, wherein: The power supply circuit includes a charge pump.

8. The semiconductor device according to claim 1, wherein: Also available: a first diode connected between a node to which the power supply voltage is supplied and the third transistor; and The second diode is connected between a node to which the ground voltage is supplied and the fourth transistor.

9. The semiconductor device according to claim 1, wherein: A delay circuit is further provided, the delay circuit delaying a control signal to output the first signal and the third signal.

10. A semiconductor device, characterized in that: have: a plurality of switching circuits; and a delay circuit for delaying a plurality of control signals corresponding to the plurality of switch circuits, The plurality of switch circuits respectively include: A first transistor is supplied with a first voltage higher than a power supply voltage and supplies the first voltage to a first terminal; a second transistor supplied with a second voltage lower than a ground voltage and supplying the second voltage to the first terminal; a third transistor, supplied with the power supply voltage, supplying the power supply voltage to the first terminal; a fourth transistor, supplied with the ground voltage, supplying the ground voltage to the first terminal; a first level shifter, which, when the first signal is the power supply voltage, converts the power supply voltage into the first voltage and outputs a second signal; as well as The second level shifter converts the ground voltage into the second voltage and outputs a fourth signal when the third signal is the ground voltage. When the first voltage is output from the first terminal, the power supply voltage is supplied from the third transistor to the first terminal according to the fourth signal, and then the first voltage is supplied from the first transistor to the first terminal according to the second signal, When the second voltage is output from the first terminal, the ground voltage is supplied from the fourth transistor to the first terminal according to the second signal, and then the second voltage is supplied from the second transistor to the first terminal according to the fourth signal, The delay circuit includes: a first circuit for generating a delay signal according to the plurality of control signals; and a plurality of logic circuits for generating the first signal and the third signal using each of the plurality of control signals and the delay signal. Each of the plurality of logic circuits outputs each of the plurality of control signals as one of the first signal and the third signal. Each of the plurality of logic circuits delays each of the plurality of control signals using the delay signal, and outputs each of the plurality of control signals after the delay as the other of the first signal and the third signal.

11. The semiconductor device according to claim 10, wherein: The first circuit includes a set of a resistor element and a capacitor element.

12. The semiconductor device according to claim 10, wherein: The plurality of control signals maintain a voltage level of either a low level or a high level, The first circuit has: a counting circuit for counting the number of transitions of the plurality of control signals from a low level to a high level and the number of transitions from a high level to a low level; and A variable resistance element has a resistance value that is variable according to the number of transitions counted by the counting circuit.

13. The semiconductor device according to claim 10, wherein: The plurality of control signals maintain a voltage level of either a low level or a high level, The first circuit includes a plurality of triggers provided corresponding to the plurality of control signals, a plurality of switch elements and a plurality of resistor elements provided corresponding to the plurality of triggers, and a capacitor element. The plurality of resistor elements are connected in series, and one end and the other end of each of the plurality of switch elements are connected to one end and the other end of each of the plurality of resistor elements. Each of the plurality of triggers outputs a fifth signal when each of the plurality of control signals changes from a low level to a high level, or changes from a high level to a low level. Each of the plurality of switch elements is set to one of a connected state and a disconnected state according to the fifth signal.

14. The semiconductor device according to any one of claims 10 to 13, characterized in that A power supply circuit for generating the first voltage and the second voltage is further provided.

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