Resistance test structure of flash memory and forming method thereof

Abstract

The invention provides a resistance test structure of a flash memory and a forming method thereof, and the method comprises the steps: forming N rows of word lines on a provided substrate, and respectively distributing a row of control gates on the two sides of each row of word lines along the column direction; in the two sides of the two rows of control gates on the two sides of each row of word lines in the row direction, the ends of the two control gates on one side are connected with each other, and the ends of the two control gates on the other side are disconnected with each other; the first row of control gates are electrically connected with the head-end metal layer; the two rows of control gates between every two adjacent rows of word lines are electrically connected through a middle metal layer; and the last row of control gates is electrically connected with the tail end metal layer. The two rows of control gates on the two sides of each row of word lines are connected with each other without additional metal layers. The control gates on the two sides of the N rows of word lines are sequentially connected in series through the metal layers and the plugs in the contact holes, the test structure is simplified, and disconnection of a series access of the control gates is avoided. The test structure is simple, the wafer acceptance test is easy, the influence of process and test fluctuation is smaller, and the test result is more stable.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a resistance test structure of a flash memory and a forming method thereof. Background Art

[0002] Flash memory (FLASH) has become the mainstream of non-volatile semiconductor storage technology. FLASH can not only program, erase and read data by electrical methods, but also retain data during power outages. It has the advantages of fast access speed, light weight, large capacity and small access device size. It is widely used in various electronic products such as smart cards, SIM cards (user identity cards), microcontrollers and mobile phones.

[0003] The control gate block resistance of flash memory is an important parameter in the acceptance test of flash memory wafers. An existing flash memory test structure has always had problems. The test results are unstable and the connection in the control gate series path is often disconnected. Summary of the invention

[0004] The object of the present invention is to provide a resistance test structure of a flash memory and a method for forming the same. The two control gates on both sides of each word line no longer need to pass through an additional metal layer, and can be connected to each other. The control gates on both sides of the N word lines are connected in series in sequence through the metal layer and the plugs in the contact hole to form a resistance test path for the control gates. The present invention simplifies the test structure and avoids the phenomenon of disconnection in the control gate series path. The test structure is simple, easy to perform wafer acceptance test, less affected by process and test fluctuations, and more stable test results.

[0005] The present invention provides a resistance test structure of a flash memory, comprising:

[0006] Step S1, providing a substrate, on which N rows of word lines are formed in parallel along a row direction, and each row of the word lines has a row of control gates on both sides along a column direction; two rows of control gates on both sides of each row of the word lines along the row direction have ends of two control gates on one side connected to each other, and ends of two control gates on the other side disconnected from each other;

[0007] Step S2, forming a dielectric layer, the dielectric layer covering the control gate layer, the word line and the substrate; forming a contact hole in the dielectric layer; the two control gates on both sides of the word line in each row are provided with the contact hole on one side away from the word line in the column direction;

[0008] Step S3, forming a metal layer located on the dielectric layer, the metal layer comprising a head metal layer, an intermediate metal layer and a terminal metal layer; the control gate of the first row is electrically connected to the head metal layer; the two rows of control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; the control gate of the last row is electrically connected to the terminal metal layer; the control gates on both sides of the N rows of word lines are connected in series in sequence through the metal layer and the plugs in the contact holes to form a resistance test path for the control gates.

[0009] Furthermore, step S1 specifically includes:

[0010] S11, sequentially forming a floating gate material layer and a control gate material layer on the substrate;

[0011] S12, patterning the control gate material layer and the floating gate material layer using a floating gate correction mask to form N rows of floating gate patterns distributed at intervals; the control gate material layer and the floating gate material layer in the area where the floating gate pattern is located are retained;

[0012] S13, etching and removing the control gate material layer and the floating gate material layer in the middle area of ​​each row of the floating gate pattern to form an opening, and forming a word line in the opening; etching the remaining control gate material layer in the floating gate pattern to form control gates located on both sides of the word line;

[0013] S14, etching and removing one side of the two sides of each row of the floating gate pattern along the row direction, so that the ends of the two control gates on one side are connected to each other, and the ends of the two control gates on the other side are disconnected from each other.

[0014] Furthermore, in the floating gate correction mask, correction patterns are set at two corner positions where the two rows of control gates are connected to each other on both sides of each row of word lines, and the floating gate pattern is used as the target pattern. The target pattern is combined with the correction pattern to obtain the floating gate correction mask.

[0015] Furthermore, in a top view, the floating gate pattern is rectangular; and the correction pattern is square or rectangular.

[0016] Furthermore, two control gates on both sides of the word line in each row each have an extension block extending from one side away from the word line in the column direction, and the control gate material layer and the floating gate material layer in the area where the extension block is located are retained;

[0017] The projection of the contact hole on the substrate falls within the projection of the extension block on the substrate; and the bottom of the plug in the contact hole is electrically connected to the extension block.

[0018] The present invention also provides a resistance test structure for a flash memory, comprising:

[0019] A substrate, on which N rows of word lines are arranged in parallel along a row direction, and each row of the word lines has a row of control gates on both sides along a column direction; two ends of the two control gates on one side of the two rows of control gates on both sides of each row of the word lines along the row direction are connected to each other, and two ends of the two control gates on the other side are disconnected from each other;

[0020] A dielectric layer, the dielectric layer covers the control gate, the word line and the substrate; a contact hole is formed in the dielectric layer; two control gates on both sides of the word line in each row are provided with a contact hole on one side away from the word line in the column direction;

[0021] A metal layer is located on the dielectric layer, the metal layer includes a head metal layer, an intermediate metal layer and a terminal metal layer; the control gate of the first row is electrically connected to the head metal layer; the two control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; the control gate of the last row is electrically connected to the terminal metal layer; the control gates on both sides of the N rows of word lines are connected in series in sequence through the metal layer and the plugs in the contact holes to form a resistance test path for the control gates.

[0022] Further, two sides of the control gate along the row direction are respectively defined as a first side and a second side.

[0023] Furthermore, the ends of the two rows of control gates on both sides of each row of word lines in the column direction are connected to each other on the first side, and are disconnected from each other on the second side.

[0024] Furthermore, the ends of the control gates in two rows on both sides of the word lines in the column direction of the odd-numbered rows are connected to each other on the first side, and are disconnected from each other on the second side;

[0025] The ends of the two rows of control gates on both sides of the word lines in the column direction of the even-numbered rows are disconnected from each other on the first side, and are connected to each other on the second side.

[0026] Furthermore, in the resistance test path of the control gate, the resistance R between the head metal layer and the terminal metal layer is measured, the total length of all the control gates is L, the width of the control gates is W, the square resistance of the control gates is Rs, and Rs=R*W / L.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention provides a resistance test structure of a flash memory and a forming method thereof, comprising: providing a substrate, on which N rows of word lines are formed in parallel along a row direction, and a row of control gates are respectively distributed on both sides of each row of word lines along a column direction; of the two rows of control gates on both sides of each row of word lines along the row direction, the ends of the two control gates on one side are connected to each other, and the ends of the two control gates on the other side are disconnected from each other; forming a dielectric layer, the dielectric layer covering the control gate layer, the word lines and the substrate; forming contact holes in the dielectric layer; the two control gates on both sides of each row of word lines are respectively provided with contact holes on one side away from the word lines in the column direction; forming a metal layer located on the dielectric layer, the metal layer comprising a head metal layer, an intermediate metal layer and an end metal layer; the first row of control gates is electrically connected to the head metal layer; the two rows of control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; and the last row of control gates is electrically connected to the end metal layer.

[0029] The two control gates on both sides of each word line of the present invention no longer need to pass through an additional metal layer, and can be connected to each other by themselves. The control gates on both sides of the N word lines are connected in series in sequence through the metal layer and the plugs in the contact hole to form a resistance test path for the control gates. The present invention simplifies the test structure and avoids the phenomenon of disconnection in the control gate series path. The test structure is simple, easy to perform wafer acceptance test, less affected by process and test fluctuations, and more stable test results.

[0030] Furthermore, in the floating gate correction mask, correction patterns are set at two corner positions where two rows of control gates are connected to each other on both sides of each word line, and the floating gate pattern is used as a target pattern. The target pattern is combined with the correction pattern to obtain the floating gate correction mask. Through the optical proximity effect correction of the floating gate correction mask, the control gate structure at the two corners where the two rows of control gates are connected to each other on both sides of each word line is regular and uniform, and the control gate resistance at the corner is uniform and stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a resistance test structure of a flash memory.

[0032] Figure 2 The figure is a schematic flow chart of a method for forming a resistance test structure of a flash memory according to an embodiment of the present invention.

[0033] Figure 3 The figure is a schematic diagram of a floating gate correction mask used in a method for forming a resistance test structure of a flash memory according to an embodiment of the present invention.

[0034] Figure 4 FIG. 1 is a schematic diagram of a first example of a resistance test structure of a flash memory according to an embodiment of the present invention.

[0035] Figure 5 Schematic diagram of a second example of a resistance test structure of a flash memory according to an embodiment of the present invention.

[0036] The reference numerals are as follows:

[0037] 01-word line; 02-control gate; 03-metal layer; 04-contact hole;

[0038] 11-word line; 12, 22-control gate; 131-head metal layer; 132-middle metal layer; 133-end metal layer; 14-contact hole; F-floating gate pattern; 120-target pattern; 121-correction pattern. DETAILED DESCRIPTION

[0039] As described in the background art, the control gate block resistance test result of a flash memory is unstable and the connection in the control gate series path is often disconnected.

[0040] like Figure 1 As shown, in a resistance test structure of a flash memory, the control gate series path structure is relatively complex. For example, the control gate signal can only be led out through one or more contact holes 04 in the thickness direction of the flash memory; the contact hole connection structure is complex and the size is relatively small. The process and test fluctuations have a great impact on the results, resulting in frequent open circuits (disconnections) in the test results, and the actual situation of the control gate resistance cannot be monitored. In addition, in the plane parallel to the upper surface of the flash memory, the control gates 02 on both sides of each word line 01 are disconnected, and an additional metal layer 03 is required to cross two rows of control gates 02 to achieve connection. Whether there is a problem with the vertical metal connection in the thickness direction of the flash memory or a problem with the parallel connection of the metal layer in the plane parallel to the upper surface of the flash memory, the control gate block resistance test will fail.

[0041] Based on the above research, the present invention provides a resistance test structure of a flash memory and a method for forming the same. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0043] The present invention provides a method for forming a resistance test structure of a flash memory, such as Figure 2 As shown, including:

[0044] Step S1, providing a substrate, on which N rows of word lines are formed in parallel along a row direction, and a row of control gates is respectively distributed on both sides of each row of word lines along a column direction; two control gates on both sides of each row of word lines along the row direction have ends of two control gates on one side connected to each other, and ends of two control gates on the other side disconnected from each other;

[0045] Step S2, forming a dielectric layer, the dielectric layer covering the control gate layer, the word line and the substrate; forming a contact hole in the dielectric layer; two control gates on both sides of each row of word lines are provided with a contact hole on one side away from the word line in the column direction;

[0046] Step S3, forming a metal layer located on the dielectric layer, the metal layer includes a head metal layer, an intermediate metal layer and a terminal metal layer; the first row of control gates is electrically connected to the head metal layer; the two rows of control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; the last row of control gates is electrically connected to the terminal metal layer; the control gates on both sides of the N rows of word lines are connected in series in sequence through the head metal layer, the plug in the contact hole, the intermediate metal layer, and the terminal metal layer to form a control gate resistance test path.

[0047] The steps of the method for manufacturing the resistance test structure of the flash memory according to the embodiment of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figure 3 The figure is a top view schematic diagram of a floating gate correction mask used in a method for forming a resistance test structure of a flash memory according to an embodiment of the present invention. Figure 4 FIG. 1 is a top view of a first example of a resistance test structure of a flash memory according to an embodiment of the present invention. Figure 3 and Figure 4 As shown, step S1 specifically includes:

[0049] S11, sequentially forming a floating gate material layer and a control gate material layer on a substrate;

[0050] S12, patterning the control gate material layer and the floating gate material layer using a floating gate correction mask to form N rows of floating gate patterns F spaced apart; the control gate material layer and the floating gate material layer in the area where the floating gate patterns F are located are retained;

[0051] S13, etching and removing the control gate material layer and the floating gate material layer in the middle area of ​​each row of floating gate patterns F to form an opening, and forming a word line 11 in the opening; etching the remaining control gate material layer in the floating gate pattern F to form control gates 12 located on both sides of the word line 11;

[0052] S14, etching and removing one side of the two sides of each row of floating gate patterns F along the row direction, so that the ends of the two control gates 12 on one side are connected to each other, and the ends of the two control gates 12 on the other side are disconnected from each other.

[0053] The floating gate correction mask in step S12 adopts optical proximity correction (OPC). As integrated circuit manufacturing technology develops towards higher integration and smaller feature sizes, photolithography has become a key factor restricting the development of integrated circuits towards smaller feature sizes. The main task of the photolithography process is to transfer the design layout of the integrated circuit from the mask to the surface of the silicon wafer. However, as the feature size decreases, the interference and diffraction effects of light cause a large difference between the actual pattern produced by photolithography on the silicon wafer and the ideal pattern of the design layout, and the mask pattern transfer is distorted, thereby affecting the performance and yield of the circuit.

[0054] Optical proximity correction is a method of pre-correcting the circuit design layout to compensate for defects caused by light interference and diffraction effects, and then transferring the corrected pattern from the mask to the surface of the silicon wafer to meet the requirements of the exposure process. Optical proximity correction is used to correct the correction pattern formed on a specific layer of the semiconductor. That is, the target pattern to be exposed on the semiconductor substrate of the wafer is calculated and corrected using a computer and software calculation to obtain a corrected mask pattern different from the target pattern. The corrected mask pattern is then made on the mask, and the pattern projected on the semiconductor substrate by the light beam through the mask can be almost the same as the target pattern.

[0055] like Figure 3 and Figure 4As shown, in the floating gate correction mask, correction patterns 121 are set at the two corner positions corresponding to the two rows of control gates 12 on both sides of each row of word lines 11, and the floating gate pattern F is used as the target pattern 120. The floating gate correction mask is obtained by combining the target pattern 120 with the correction pattern 121. The control gate 11 at the corner has a regular and uniform structure, and the resistance of the control gate 11 at the corner is uniform and stable. From a top view, the target pattern 120 is rectangular; the correction pattern 121 is square or rectangular. The two control gates 12 on both sides of each row of word lines 11 extend an extension block 15 on each side away from the word line 11 in the column direction, and the control gate material layer and the floating gate material layer in the area where the extension block is located are retained; the control gate 12 and the extension block 15 are both formed by the control gate material layer. The projection of the contact hole 14 on the substrate falls into the projection of the extension block 15 on the substrate; the bottom of the plug in the contact hole 14 is electrically connected to the extension block 15.

[0056] The present invention also provides a resistance test structure of a flash memory, comprising:

[0057] A substrate, on which N rows of word lines 11 are arranged in parallel along a row direction, and a row of control gates 12 are arranged on both sides of each row of word lines 11 along a column direction; two control gates on both sides of each row of word lines 11 along the row direction have ends of two control gates on one side connected to each other, and ends of two control gates on the other side disconnected from each other;

[0058] A dielectric layer, the dielectric layer covers the control gate, the word line 11 and the substrate; a contact hole 14 is formed in the dielectric layer; two control gates 12 on both sides of each row of word lines 11 are provided with a contact hole 14 on one side away from the word line in the column direction;

[0059] The metal layer located on the dielectric layer includes a head metal layer 131, an intermediate metal layer 132 and an end metal layer 133; the first row of control gates is electrically connected to the head metal layer 131; the two rows of control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer 132; the last row of control gates is electrically connected to the end metal layer 133; the control gates on both sides of the N rows of word lines are connected in series in sequence through the metal layer and the plug in the contact hole 14, that is, the control gates of the entire test memory cell array are connected in series to form a resistance test path for the control gate. The row direction is perpendicular to the column direction. The two sides of the control gate along the row direction are defined as the first side and the second side, respectively. A floating gate can be formed directly below the control gate.

[0060] In one example, if Figure 4 As shown, the ends of the two rows of control gates 12 on both sides of each row of word lines 11 in the column direction are connected to each other on the first side (left side) and disconnected from each other on the second side (right side).

[0061] In another example, if Figure 5As shown, the ends of the two rows of control gates 22 on both sides of the odd-numbered word line 11 in the column direction are interconnected on the first side (left side) and disconnected from each other on the second side (left side); the ends of the two rows of control gates 22 on both sides of the even-numbered word line 11 in the column direction are disconnected from each other on the first side (left side) and connected to each other on the second side (right side).

[0062] In the resistance test path of the control gate, the resistance between the head metal layer 131 and the terminal metal layer 133 is measured to be R, the total length of all control gates is L, the width of the control gate is W, the square resistance of the control gate is Rs, and Rs = R*W / L. The test structure and wafer acceptance calculation method are simple, less affected by process and test fluctuations, and the test results are more stable.

[0063] In summary, the present invention provides a resistance test structure of a flash memory and a method for forming the same, comprising: providing a substrate, on which N rows of word lines are formed in parallel along a row direction, and a row of control gates are respectively distributed on both sides of each row of word lines along a column direction; of the two rows of control gates on both sides of each row of word lines along the row direction, the ends of the two control gates on one side are connected to each other, and the ends of the two control gates on the other side are disconnected from each other; forming a dielectric layer, the dielectric layer covering the control gate layer, the word lines and the substrate; forming contact holes in the dielectric layer; the two control gates on both sides of each row of word lines are each provided with a contact hole on one side away from the word lines in the column direction; forming a metal layer located on the dielectric layer, the metal layer comprising a head metal layer, an intermediate metal layer and an end metal layer; the first row of control gates is electrically connected to the head metal layer; the two rows of control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; and the last row of control gates is electrically connected to the end metal layer.

[0064] The two control gates on both sides of each word line of the present invention no longer need to pass through an additional metal layer, and can be connected to each other by themselves. The control gates on both sides of the N word lines are connected in series in sequence through the metal layer and the plugs in the contact hole to form a resistance test path for the control gates. The present invention simplifies the test structure and avoids the phenomenon of disconnection in the control gate series path. The test structure is simple, easy to perform wafer acceptance test, less affected by process and test fluctuations, and more stable test results.

[0065] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0066] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a resistance test structure of a flash memory, characterized in that: include: Step S1, providing a substrate, on which N rows of word lines are formed in parallel along a row direction, and each row of the word lines has a row of control gates on both sides along a column direction; two rows of control gates on both sides of each row of the word lines along the row direction have ends of two control gates on one side connected to each other, and ends of two control gates on the other side disconnected from each other; Step S2, forming a dielectric layer, the dielectric layer covering the control gate layer, the word line and the substrate; forming a contact hole in the dielectric layer; the two control gates on both sides of the word line in each row are provided with the contact hole on one side away from the word line in the column direction; Step S3, forming a metal layer located on the dielectric layer, the metal layer comprising a head metal layer, an intermediate metal layer and a terminal metal layer; the control gate of the first row is electrically connected to the head metal layer; the two rows of control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; the control gate of the last row is electrically connected to the terminal metal layer; the control gates on both sides of the N rows of word lines are connected in series in sequence through the metal layer and the plugs in the contact holes to form a resistance test path for the control gates.

2. The method for forming a resistance test structure of a flash memory according to claim 1, wherein: Step S1 specifically includes: S11, sequentially forming a floating gate material layer and a control gate material layer on the substrate; S12, patterning the control gate material layer and the floating gate material layer using a floating gate correction mask to form N rows of floating gate patterns distributed at intervals; the control gate material layer and the floating gate material layer in the area where the floating gate pattern is located are retained; S13, etching and removing the control gate material layer and the floating gate material layer in the middle area of ​​each row of the floating gate pattern to form an opening, and forming a word line in the opening; etching the remaining control gate material layer in the floating gate pattern to form the control gates located on both sides of the word line; S14, etching and removing one side of the two sides of each row of the floating gate pattern along the row direction, so that the ends of the two control gates on one side are connected to each other, and the ends of the two control gates on the other side are disconnected from each other.

3. The method for forming a resistance test structure of a flash memory according to claim 2, wherein: In the floating gate correction mask, correction patterns are set at two corner positions where the two rows of control gates are connected to each other on both sides of each row of word lines, and the floating gate pattern is used as the target pattern. The target pattern is combined with the correction pattern to obtain the floating gate correction mask.

4. The method for forming a resistance test structure of a flash memory according to claim 3, wherein: In a top view, the floating gate pattern is rectangular; the correction pattern is square or rectangular.

5. The method for forming a resistance test structure of a flash memory according to claim 2, wherein: The two control gates on both sides of the word line in each row each extend an extension block away from the word line on one side in the column direction, and the control gate material layer and the floating gate material layer in the area where the extension block is located are retained; The projection of the contact hole on the substrate falls within the projection of the extension block on the substrate; and the bottom of the plug in the contact hole is electrically connected to the extension block.

6. A resistance test structure of a flash memory, characterized in that: include: A substrate, on which N rows of word lines are arranged in parallel along a row direction, and each row of the word lines has a row of control gates on both sides along a column direction; two ends of the two control gates on one side of the two rows of control gates on both sides of each row of the word lines along the row direction are connected to each other, and two ends of the two control gates on the other side are disconnected from each other; a dielectric layer, the dielectric layer covering the control gate, the word line and the substrate; a contact hole is formed in the dielectric layer; two control gates on both sides of the word line in each row are provided with the contact hole on one side away from the word line in the column direction; A metal layer is located on the dielectric layer, the metal layer includes a head metal layer, an intermediate metal layer and a terminal metal layer; the control gate of the first row is electrically connected to the head metal layer; the two control gates between each two adjacent rows of word lines are electrically connected through the intermediate metal layer; the control gate of the last row is electrically connected to the terminal metal layer; the control gates on both sides of the N rows of word lines are connected in series in sequence through the metal layer and the plugs in the contact holes to form a resistance test path for the control gates.

7. The resistance test structure of flash memory according to claim 6, characterized in that: Two sides of the control gate along the row direction are respectively defined as a first side and a second side.

8. The resistance test structure of flash memory as claimed in claim 7, characterized in that: The ends of the two rows of control gates on both sides of each row of word lines in the column direction are connected to each other on the first side and are disconnected from each other on the second side.

9. The resistance test structure of flash memory according to claim 7, characterized in that: The ends of the control gates in two rows on both sides of the word lines in the column direction of the odd-numbered rows are connected to each other on the first side and are disconnected from each other on the second side; The ends of the control gates in two rows on both sides of the word lines in the column direction of the even-numbered rows are disconnected from each other on the first side, and are connected to each other on the second side.

10. The resistance test structure of a flash memory as claimed in claim 6, characterized in that: In the resistance test path of the control gate, the resistance R between the head metal layer and the terminal metal layer is measured, the total length of all the control gates is L, the width of the control gates is W, the square resistance of the control gates is Rs, and Rs=R*W / L.

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