Error correction code circuit, error correction method, repair system and memory

Abstract

The invention provides an error correction code circuit, an error correction method, a repair system and a memory, and the error correction code circuit comprises a first decoding module which is used for decoding according to the received source data of a storage bit and the received source verification data of a verification bit, and detecting error data; the judgment module is used for judging whether data of short-circuit bits exist in the error data or not according to the received state indication information of the storage bits and the check bits if the error data exist; the first repairing module is used for negating the data of the short-circuit bit in the error data to generate first correction data when the difference value between the total bit of the error data and the data bit of the short-circuit bit does not exceed the error correction capability; the second decoding module is used for decoding according to the first correction data and detecting error data in the first correction data; and the second repairing module is used for performing ECC error correction on error data in the first correction data to generate second correction data. The error correction capability of the error correction code circuit can be enhanced.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an error correction code circuit, an error correction method, a repair system and a memory. Background Art

[0002] MRAM is a new memory and storage technology that has the same fast random read and write characteristics as SRAM / DRAM, and also has the function of flash memory to permanently retain data after power failure. The core structure of MRAM storage bits is a magnetic tunnel junction, which is composed of two layers of ferromagnetic materials sandwiched by a very thin layer of non-ferromagnetic insulating material. The lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction, and the upper ferromagnetic material is a free layer with a variable magnetization direction. The magnetization direction of the free layer can be parallel or anti-parallel to the reference layer.

[0003] When MRAM reads data, the read circuit needs to detect the resistance of the MRAM storage bit. Since the resistance of the magnetic tunnel junction may drift due to production process, number of reads and writes, temperature, etc., data errors may occur, and the data bits read out are opposite to the data bits written previously. To solve this problem, an ECC (Error Correction Code) circuit can be added to encode the data of a word and add some check bits to detect and correct data errors. However, conventional ECC circuits can generally only correct one bit of erroneous data, and the error correction capability is limited. Summary of the invention

[0004] In view of this, the present invention provides an error correction code circuit, an error correction method, a repair system and a memory, which can enhance the error correction capability of the error correction code circuit.

[0005] In a first aspect, the present invention provides an error correction code circuit, comprising:

[0006] A first decoding module, configured to decode the received source data of the storage bit and the source verification data of the verification bit, and detect erroneous data in the source data and the source verification data;

[0007] A judgment module, used for judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit;

[0008] A first repair module, configured to invert the data of the short-circuit bits in the erroneous data to generate first corrected data if the total number of erroneous data bits is greater than the number of short-circuit bits and the difference between the total number of erroneous data bits and the number of short-circuit bits does not exceed the error correction capability;

[0009] a second decoding module, configured to decode the first corrected data and detect erroneous data in the first corrected data;

[0010] The second repair module is used to perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0011] Optionally, it also includes:

[0012] The overflow indication module is used to output an overflow flag bit that cannot be corrected if the total number of erroneous data bits is greater than the number of data bits of the short-circuit bits, and the difference between the total number of erroneous data bits and the number of data bits of the short-circuit bits exceeds the error correction capability.

[0013] Optionally, the first repair module is used to invert the data of the short-circuit bits in the erroneous data to generate third corrected data if the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits.

[0014] Optionally, if the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

[0015] In a second aspect, the present invention provides an error correction method for an error correction code circuit, comprising:

[0016] Decoding is performed according to the received source data of the storage bit and the source check data of the check bit, and detecting erroneous data in the source data and the source check data;

[0017] If there is erroneous data, judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit;

[0018] If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits does not exceed the error correction capability, invert the data of the short-circuit bits in the erroneous data to generate first corrected data;

[0019] Decoding the first corrected data to detect erroneous data in the first corrected data;

[0020] Perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0021] Optionally, it also includes:

[0022] If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits exceeds the error correction capability, an overflow flag that cannot be corrected is output.

[0023] Optionally, it also includes:

[0024] If the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits, the data of the short-circuit bits in the erroneous data are inverted to generate third corrected data.

[0025] Optionally, if the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

[0026] In a third aspect, the present invention provides a memory repair system, comprising the error correction code circuit provided in the first aspect, and further comprising:

[0027] A storage bit array, wherein storage bits of the storage bit array are used to store source data;

[0028] A check bit array, wherein the check bits of the check bit array are used to store source check data, wherein the source check data is obtained by encoding the source data;

[0029] A data reading circuit is connected to the error correction code circuit, the storage bit array and the check bit array, and is used to read the source data of the selected storage bit and the source check data of the selected check bit array, as well as the status indication information of the selected storage bit and the selected check bit, and input the read source data, source check data and status indication information into the error correction code circuit.

[0030] Optionally, the data reading circuit includes:

[0031] A first reference circuit, used for reading the source data of the storage bit and the source check data of the check bit;

[0032] The second reference circuit is used to read the status indication information of the storage bit and the check bit.

[0033] In a fourth aspect, the present invention provides a memory, comprising the memory repair system provided in the third aspect.

[0034] The error correction code circuit, error correction method, repair system and memory provided by the present invention can repair the errors of short-circuited bits according to the status indication information of the bits, and repair the soft errors of normal bits within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit without increasing the check bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic flow chart of an error correction method for an error correction code circuit according to an embodiment of the present invention;

[0036] Figure 2A schematic diagram of an error correction method of an error correction code circuit according to an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of an error correction method of an error correction code circuit according to an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of an error correction method of an error correction code circuit according to an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of the structure of an error correction code circuit according to an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the structure of a memory repair system according to an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of the array structure of a storage bit array and a check bit array according to an embodiment of the present invention;

[0042] Figure 8 FIG. 4 is a schematic diagram of the structure of a data reading circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0046] An embodiment of the present invention provides an error correction method for an error correction code circuit, such as Figure 1As shown, the method comprises the following steps:

[0047] S101, decoding is performed according to the received source data of the storage bit and the source verification data of the verification bit, and erroneous data in the source data and the source verification data is detected;

[0048] S102, if there is erroneous data, judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit;

[0049] S103, if the total number of erroneous data bits is greater than the number of short-circuited bits, and the difference between the total number of erroneous data bits and the number of short-circuited bits does not exceed the error correction capability, invert the data of the short-circuited bits in the erroneous data to generate first corrected data;

[0050] S104, decoding according to the first corrected data, detecting erroneous data in the first corrected data;

[0051] S105, performing ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0052] In the above embodiment, the state indication information of the storage bit and the check bit is used to indicate whether the bit is a short-circuit bit or a normal bit, and its value is related to the circuit design. In one embodiment, if the state indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the state indication information of a bit is 0, it indicates that the bit is a normal bit, and the bit is a storage bit or a check bit.

[0053] Furthermore, the method also includes: if the total number of erroneous data bits is greater than the number of data bits of short-circuited bits, and the difference between the total number of erroneous data bits and the number of data bits of short-circuited bits exceeds the error correction capability, outputting an overflow flag that cannot be corrected.

[0054] Furthermore, the method further comprises: if the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits, inverting the data of the short-circuit bits in the erroneous data to generate third corrected data.

[0055] The following examples illustrate this in detail.

[0056] In one embodiment, Figure 2 As shown, it is assumed that a storage byte has 8 storage bits and 4 check bits (the error correction capability is 1 bit).

[0057] According to the received source data of the storage bit and the source check data of the check bit, decoding is performed to detect that there are 2 bits of error in the source data. Of course, there may also be errors in the source check data, and here only the source data error is used as an example.

[0058] According to the status indication information of the storage bit and the check bit, it is determined that one of the two bits of erroneous data is a short bit. The interpolation between the total number of erroneous data bits and the number of short bit data bits is the number of soft error data bits. Here, soft errors refer to read softfail caused by insufficient high-temperature read window or misread (RDR) and write softfail (WER) caused by tailing.

[0059] The number of soft error data bits is 1 bit, and the error correction capability is 1 bit, which does not exceed the error correction capability. The data of the short-circuit bit is inverted to obtain the first corrected data. Then, decoding is performed based on the first corrected data to detect the erroneous 1 bit data in the first corrected data; ECC error correction is performed on the erroneous 1 bit data in the first corrected data to generate the second corrected data.

[0060] In addition, since the short-circuit bit can only read 0, the process of writing 0 and reading 0 will not go wrong, and no repair is required at this time. Only when writing 1 and reading 0 will an error occur, and data inversion is required. When 1-bit data is wrong, it is compared bit by bit with the status indication information. If the status indication information is 1, it means that it is a short-circuit bit. Simply invert 0 to complete the data repair of the short-circuit bit.

[0061] In one embodiment, Figure 3 As shown, it is assumed that a storage byte has 8 storage bits and 4 check bits (error correction capability is 1 bit). According to the received source data of the storage bits and the source check data of the check bits, it is detected that there are 2 bits of error in the source data, and according to the status indication information of the storage bits and the check bits, it is judged that there is no short-circuit bit data in the 2-bit error data, then the number of soft error data bits is 2 bits, and the error correction capability is 1 bit, which exceeds the error correction capability, and the error correction is abandoned, and the error correction indication flag bit that cannot be corrected is output. The error correction indication flag bit that cannot be corrected can be stored in the status register for user reliability detection.

[0062] In one embodiment, Figure 4 As shown, assuming that a storage byte has 8 storage bits and 4 check bits (error correction capability is 1 bit). According to the received source data of the storage bits and the source check data of the check bits, it is detected that there are 2 bits of error in the source data, and according to the status indication information of the storage bits and the check bits, it is judged that the 2 bits of error data are all short-circuit bit data, then the number of soft error data bits is 0 bit, and the data can be repaired by simply inverting the short-circuit bit data in the error data.

[0063] The error correction capability of the ECC circuit is related to the number of bits of the check data. The error correction capability can be enhanced by increasing the number of bits of the check data. For example, 10 check bits can correct 2 bits of errors. However, no matter how many bits the error correction capability of the ECC circuit is, the error correction method of the error correction code circuit provided in the above embodiment is applicable.

[0064] The error correction method of the error correction code circuit provided by the embodiment of the present invention can repair the error of the short-circuit bit according to the status indication information of the bit without adding the check bit, and repair the soft error of the normal bit within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit. After exceeding the error correction capability, an overflow flag is given to remind the user that there may be a problem with the output data, giving the possibility of rewriting or external repair. Moreover, during the operation of the memory, timely repair can be performed during each read operation, effectively solving the error of the short-circuit bit that occurs during the life of the memory, and improving the reliability of the memory.

[0065] An embodiment of the present invention provides an error correction code circuit, such as Figure 5 As shown, the error correction code circuit includes:

[0066] A first decoding module 501 is used to decode the received source data of the storage bit and the source check data of the check bit, and detect erroneous data in the source data and the source check data;

[0067] The judging module 502 is used to judge whether there is short-circuit bit data in the erroneous data according to the received status indication information of the storage bit and the check bit if there is erroneous data;

[0068] A first repair module 503 is used to invert the data of the short-circuited bits in the erroneous data to generate first corrected data if the total number of erroneous data bits is greater than the number of short-circuited bits and the difference between the total number of erroneous data bits and the number of short-circuited bits does not exceed the error correction capability;

[0069] A second decoding module 504, configured to decode the first corrected data and detect erroneous data in the first corrected data;

[0070] The second repair module 505 is used to perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

[0071] In one embodiment, the error correction code circuit further includes: an overflow indication module, which is used to output an overflow flag bit that cannot be corrected if the total number of erroneous data bits is greater than the number of data bits of the short-circuit bits, and the difference between the total number of erroneous data bits and the number of data bits of the short-circuit bits exceeds the error correction capability.

[0072] In one embodiment, the first repair module 503 is used to invert the data of the short-circuited bits in the erroneous data to generate third corrected data if the total number of erroneous data bits is equal to the number of data bits of the short-circuited bits.

[0073] In one embodiment, if the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit, and the bit is a storage bit or a check bit.

[0074] The error correction code circuit provided by the embodiment of the present invention can repair the error of the short-circuit bit according to the status indication information of the bit, and repair the soft error of the normal bit within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit without adding the check bit. After exceeding the error correction capability, an overflow flag is given to remind the user that there may be a problem with the output data, giving the possibility of rewriting or external repair. Moreover, during the operation of the memory, timely repair can be performed during each read operation, effectively solving the error of the short-circuit bit that occurs during the life of the memory, and improving the reliability of the memory.

[0075] On the other hand, an embodiment of the present invention provides a memory repair system, such as Figure 6 As shown, the memory repair system includes the error correction code circuit 601 provided in the above embodiments, and further includes:

[0076] A storage bit array 602, wherein the storage bits of the storage bit array 602 are used to store source data;

[0077] A check bit array 603, where the check bits of the check bit array 603 are used to store source check data, where the source check data is obtained by encoding the source data;

[0078] The data reading circuit 604 is connected to the error correction code circuit 601, the storage bit array 602 and the check bit array 603, and is used to read the source data of the selected storage bit and the source check data of the selected check bit array, as well as the status indication information of the selected storage bit and the selected check bit, and input the read source data, source check data and status indication information into the error correction code circuit 601.

[0079] Figure 7 The schematic diagram of the array structure of the storage bit array and the check bit array is as follows. The storage bit array includes M columns of storage bits, and the check bit array includes N columns of check bits, wherein M and N are both positive integers and M>N.

[0080] Taking MRAM as an example, the structure of the data reading circuit 604 can be as follows: Figure 8 The circuit structure shown includes:

[0081] A first reference circuit, used for reading source data of storage bits and source check data of check bits;

[0082] The second reference circuit is used to read the status indication information of the storage bit and the check bit.

[0083] like Figure 8 As shown, the first reference circuit compares the resistance of the storage bit / check bit with the reference resistor Rref, and SA outputs the source data / source check data Data bit bit by bit. The second reference circuit compares the resistance of the storage bit / check bit with the reference resistor Rref_short, and SA outputs the state indication information Short / Normal by bit.

[0084] In the memory repair system provided by the embodiment of the present invention, the data reading circuit inputs the read source data, source check data and status indication information into the error correction code circuit. The error correction code circuit can repair the error of the short-circuited bit according to the status indication information of the bit, and repair the soft error of the normal bit within the error correction capability, thereby enhancing the error correction capability of the error correction code circuit without increasing the check bit.

[0085] On the other hand, an embodiment of the present invention further provides a memory, wherein the memory includes the above-mentioned memory repair system.

[0086] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0087] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An error correction code circuit, characterized in that: include: A first decoding module, configured to decode the received source data of the storage bit and the source verification data of the verification bit, and detect erroneous data in the source data and the source verification data; A judgment module, used for judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit; A first repair module, configured to invert the data of the short-circuit bits in the erroneous data to generate first corrected data if the total number of erroneous data bits is greater than the number of short-circuit bits and the difference between the total number of erroneous data bits and the number of short-circuit bits does not exceed the error correction capability; a second decoding module, configured to decode the first corrected data and detect erroneous data in the first corrected data; The second repair module is used to perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

2. The error correction code circuit according to claim 1, characterized in that: Also includes: The overflow indication module is used to output an overflow flag bit that cannot be corrected if the total number of erroneous data bits is greater than the number of data bits of the short-circuit bits, and the difference between the total number of erroneous data bits and the number of data bits of the short-circuit bits exceeds the error correction capability.

3. The error correction code circuit according to claim 1, characterized in that: The first repair module is used to invert the data of the short-circuit bits in the erroneous data to generate third corrected data if the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits.

4. The error correction code circuit according to claim 1, characterized in that: If the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

5. An error correction method for an error correction code circuit, characterized in that: include: Decoding is performed according to the received source data of the storage bit and the source check data of the check bit, and detecting erroneous data in the source data and the source check data; If there is erroneous data, judging whether there is short-circuited bit data in the erroneous data according to the received status indication information of the storage bit and the check bit; If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits does not exceed the error correction capability, invert the data of the short-circuit bits in the erroneous data to generate first corrected data; Decoding the first corrected data to detect erroneous data in the first corrected data; Perform ECC error correction on erroneous data in the first corrected data to generate second corrected data.

6. The method according to claim 5, characterized in that Also includes: If the total number of erroneous data bits is greater than the number of short-circuit bits, and the difference between the total number of erroneous data bits and the number of short-circuit bits exceeds the error correction capability, an overflow flag that cannot be corrected is output.

7. The method according to claim 5, characterized in that Also includes: If the total number of erroneous data bits is equal to the number of data bits of the short-circuit bits, the data of the short-circuit bits in the erroneous data are inverted to generate third corrected data.

8. The method according to claim 5, characterized in that If the status indication information of a bit is 1, it indicates that the bit is a short-circuit bit; if the status indication information of a bit is 0, it indicates that the bit is a normal bit and the bit is a storage bit or a check bit.

9. A memory repair system, characterized in that: include: The error correction code circuit according to any one of claims 1 to 4, further comprising: A storage bit array, wherein storage bits of the storage bit array are used to store source data; A check bit array, wherein the check bits of the check bit array are used to store source check data, wherein the source check data is obtained by encoding the source data; A data reading circuit is connected to the error correction code circuit, the storage bit array and the check bit array, and is used to read the source data of the selected storage bit and the source check data of the selected check bit array, as well as the status indication information of the selected storage bit and the selected check bit, and input the read source data, source check data and status indication information into the error correction code circuit.

10. The memory repair system according to claim 9, characterized in that: The data reading circuit comprises: A first reference circuit, used for reading the source data of the storage bit and the source check data of the check bit; The second reference circuit is used to read the status indication information of the storage bit and the check bit.

11. A memory, characterized in that: The memory comprises the memory repair system according to claim 9 or 10.

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