PMOS transistor and preparation method thereof, CMOS circuit and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and provides a preparation method of a PMOS (P-channel Metal Oxide Semiconductor) transistor, which is suitable for manufacturing the PMOS transistor with the line width of a source / drain structure smaller than 40nm, and comprises the following steps of: providing a substrate, and forming a source / drain groove on the substrate; growing a SiGe material in the source / drain groove to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a laminated structure of the SiGe layer and the Si thin film layer; growing a first Co thin film layer on the laminated structure, and then performing annealing treatment to enable Co in the first Co thin film layer to react with Si in the Si thin film layer to generate a first CoSi2 thin film layer; wherein the overall structure formed in the source / drain groove is a source / drain electrode, and the first CoSi2 thin film layer is the upper structure of the source / drain electrode. The invention also provides a PMOS (P-channel Metal Oxide Semiconductor) transistor, a CMOS (Complementary Metal Oxide Semiconductor) circuit and a preparation method of the CMOS circuit. According to the technical scheme, Si epitaxy is carried out on the SiGe layer to form the Si thin film layer, so that enough Si is provided for the subsequent CoSi2 manufacturing process, and formation of low-resistance-phase CoSi2 is promoted.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a PMOS transistor and a preparation method thereof, a CMOS circuit and a preparation method thereof. Background Art

[0002] There are three phases of silicon-cobalt alloy, Si2Co / SiCo / CoSi2, among which CoSi2 is a low-resistance phase and Co2Si / CoSi has a higher resistance, which will lead to an increase in the resistance of the source / drain of PMOS. In the thin film deposition process, the Co film is deposited first. After RTP (250℃~410℃), the Co film diffuses into Si as a diffusion source, forming Co2Si first. As the RTP (410℃~510℃) temperature increases, the Co film further diffuses and gradually forms CoSi. When the RTP (>750℃) temperature is further increased, Si begins to diffuse into the CoSi film, and finally forms a single low-resistance phase CoSi2.

[0003] If the CoSi2 process is used, for the PMOS area, especially the PMOS with small line width (the line width of the source / drain structure is less than 40nm), when SiGe is epitaxially grown at the source / drain, the Si content in the SiGe epitaxial structure is lower than that of the pure Si content, resulting in insufficient Si to react with Co, which increases the temperature required to form the low-resistance phase CoSi2. When the temperature is too high, CoSi2 is prone to agglomeration, resulting in wire breakage and affecting product quality.

[0004] For logic circuits below 28nm, most semiconductor companies are beginning to develop in the direction of NiSi. However, since NiSi begins to undergo phase change at higher temperatures (>650℃) and turns into the high-resistance phase NiSi2, the NiSi back-end process is required to be less than 650℃. If high temperatures are required for the back-end process, NiSi alloys are difficult to use. That is, for processes that require high temperatures, the CoSi2 process solution is still required.

[0005] Based on this, a new process solution is needed to solve the problem of insufficient Si content in the SiGe epitaxial structure of the source / drain of the small line width PMOS, so as to ensure the formation of a low-resistance phase CoSi2 on the surface of the SiGe epitaxial structure. Summary of the invention

[0006] The embodiment of the present invention provides a method for preparing a PMOS transistor, aiming to solve the technical problem that in the case of small line width, the silicon-cobalt alloy cannot be converted into a low-resistance phase at a lowered temperature due to insufficient Si content in SiGe in the CoSi2 process.

[0007] The embodiment of the present invention is implemented as follows: a method for preparing a PMOS transistor, the method being applicable to the manufacture of a PMOS transistor with a source / drain structure having a line width less than 40 nm, the method comprising the following steps:

[0008] Providing a substrate, and forming source / drain trenches on the substrate;

[0009] Growing SiGe material in the source / drain trench to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; and

[0010] Growing a first Co thin film layer on the stacked structure, and then performing an annealing treatment to allow Co in the first Co thin film layer to react with Si in the Si thin film layer to form a first CoSi2 thin film layer;

[0011] The overall structure formed in the source / drain groove is a source / drain electrode, and the first CoSi2 thin film layer is an upper structure of the source / drain electrode.

[0012] Furthermore, the preparation method further comprises the following steps:

[0013] A first gate layer is prepared on the substrate, wherein the material of the first gate layer is polysilicon;

[0014] Growing a second Co thin film layer on the first gate layer, and then performing an annealing treatment to allow Co in the second Co thin film layer to react with Si in the first gate layer to form a second CoSi2 thin film layer;

[0015] The overall structure of the first gate layer and the second CoSi2 thin film layer is the first gate, and the second CoSi2 thin film layer is the upper structure of the first gate.

[0016] Furthermore, the first Co thin film layer and the second Co thin film layer are grown simultaneously and then annealed, and the first CoSi2 thin film layer and the second CoSi2 thin film layer generated by the reaction are the upper structure of the source / drain and the upper structure of the first gate, respectively.

[0017] Furthermore, in the step of growing a Si thin film layer on the surface of the SiGe layer, the thickness of the Si thin film layer satisfies: when it subsequently reacts with the first Co thin film layer to generate the first CoSi2 thin film layer, all the Si contained in the Si thin film layer is consumed by Co and there is no Si supply shortage, and the Si supply shortage means that there is remaining Co that has not been reacted after annealing.

[0018] Furthermore, the thickness of the Si thin film layer is less than 20 nm.

[0019] The present invention also provides a PMOS transistor, which is manufactured using the manufacturing method of the PMOS transistor according to any one of the above items.

[0020] The present invention also provides a CMOS circuit, comprising:

[0021] substrate;

[0022] at least one NMOS transistor formed on the substrate; and

[0023] At least one PMOS transistor according to the above is formed on the substrate.

[0024] Furthermore, the NMOS transistor comprises:

[0025] an active region, the active region comprising a source / drain region for forming a source / drain of the NMOS transistor;

[0026] a second gate dielectric layer formed on the active area; and

[0027] a second gate formed on the second gate dielectric layer, the source / drain regions being located at both sides of the second gate, and the second gate comprising a second gate layer;

[0028] Wherein, the material of the second gate layer is polysilicon.

[0029] The present invention also provides a method for manufacturing a CMOS circuit, which is used to manufacture the CMOS circuit according to any one of the above items, comprising the following steps:

[0030] Providing a substrate, forming at least two active regions on the substrate, and two adjacent active regions are isolated by a shallow trench isolation structure;

[0031] forming a source / drain trench of the PMOS transistor in the active area corresponding to the PMOS transistor;

[0032] Growing SiGe material in the source / drain trench to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer;

[0033] A first Co thin film layer is grown on the stacked structure and annealed to allow the first Co thin film layer to react with Si in the Si thin film layer to generate a first CoSi2 thin film layer.

[0034] Furthermore, the NMOS transistor comprises:

[0035] an active region, the active region comprising a source / drain region for forming a source / drain of the NMOS transistor;

[0036] a second gate dielectric layer formed on the active area; and

[0037] a second gate formed on the second gate dielectric layer, the source / drain regions being located at both sides of the second gate, and the second gate comprising a second gate layer;

[0038] Wherein, the first gate layer and the second gate layer are both made of polysilicon.

[0039] Furthermore, the method comprises the following steps:

[0040] Providing a substrate, forming at least two active regions on the substrate, and two adjacent active regions are isolated by a shallow trench isolation structure;

[0041] Simultaneously forming a first gate layer of the PMOS transistor and a second gate layer of the NMOS transistor on each of the active regions;

[0042] forming a source / drain trench of the PMOS transistor in the active area corresponding to the PMOS transistor;

[0043] Growing SiGe material in the source / drain trench of the PMOS transistor to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; and

[0044] simultaneously growing a first Co thin film layer, a second Co thin film layer, a third Co thin film layer and a fourth Co thin film layer on the stacked structure, the first gate layer, the second gate layer and the source / drain region of the NMOS transistor respectively; and

[0045] Annealing treatment allows the first Co thin film layer, the second Co thin film layer, the third Co thin film layer and the fourth Co thin film layer to react with corresponding Si respectively to generate a first CoSi2 thin film layer, a second CoSi2 thin film layer, a third CoSi2 thin film layer and a fourth CoSi2 thin film layer.

[0046] In the preparation method of the PMOS transistor of the present invention, a SiGe layer is formed by epitaxial growth in a substrate, and the stress acting on the channel region is enhanced by utilizing the difference between the lattice constant of SiGe and the lattice constant of Si in the substrate, thereby providing compressive stress for the PMOS transistor and improving its carrier mobility. On the other hand, compared with Si material, Ge material itself has a higher carrier mobility, which can increase the driving current of the PMOS transistor, thereby achieving the purpose of improving the electrical performance of the PMOS transistor.

[0047] Furthermore, Si epitaxy is performed on the SiGe layer to form a Si thin film layer, aiming to provide sufficient Si for the subsequent CoSi2 process and promote the formation of a low-resistance phase of CoSi2, effectively avoiding the problem of the subsequent CoSi2 process being unable to convert the silicon-cobalt alloy into a low-resistance phase due to insufficient Si content in the SiGe layer. At the same time, it also avoids the CoSi2 agglomeration problem caused by the need to increase the reaction temperature in order to convert the silicon-cobalt alloy into a low-resistance phase, thereby optimizing the process of PMOS transistors and SiGe epitaxy. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 and Figure 2 is a cross-sectional schematic diagram of a PMOS transistor formed with a silicon-cobalt alloy in the related art;

[0049] Figure 3 and Figure 4 Schematic diagram of a process for preparing a PMOS transistor according to an embodiment of the present invention;

[0050] Figures 5 to 11 A schematic cross-sectional structure diagram of a PMOS transistor forming process according to an embodiment of the present invention;

[0051] Figures 12 to 22 A schematic cross-sectional structure diagram of a CMOS circuit forming process according to an embodiment of the present invention;

[0052] Fig.23 and Fig.24 The figure is a flow chart of a method for manufacturing a CMOS circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated in the description of the direction and positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0056] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0057] From the above background technology section, it can be seen that: (1) If the NiSi process is used in the existing technical solution, it cannot adapt to the subsequent high-temperature process; (2) If the traditional structure CoSi2 process is used, the small line width effect of the CoSi2 process cannot be solved; (3) For the source / drain region of the PMOS transistor, the process of forming CoSi2 on the SiGe surface requires the design of a new SiGe process solution to solve the problem of insufficient Si content in the SiGe epitaxial structure.

[0058] See also Figure 1 and Figure 2 , combined with the structure of the conventional PMOS transistor 101 and the process of the conventional PMOS transistor 101, taking the above-mentioned point (3) as an example:

[0059] like Figure 1 As shown, in the conventional CoSi2 process, a Co film is directly deposited on the surface of the substrate 2 on both sides of the gate structure 1 to react with the Si in the substrate 2. Since the Si content in the substrate 2 is relatively high, SiGe is not deposited in the source / drain region of the PMOS transistor, and there is no small line width effect. Therefore, the Co film can directly react with the substrate 2 in sufficient quantity to form a low-resistance CoSi2 layer 3 to meet usage requirements.

[0060] like Figure 2As shown, if a SiGe layer 4 is epitaxially formed in the substrate 2 on both sides of the gate structure 1 to enhance the compressive stress on the PMOS transistor 101, then during the process of depositing a Co film on the surface of the SiGe layer 4 to react and form a silicon-cobalt alloy, due to the low Si content in the SiGe layer 4 and the small line width effect, only a high-resistance Si2Co layer or SiCo layer 5 can be formed, thereby affecting the performance of the PMOS transistor 101.

[0061] Different from the prior art, the technical solution of the present invention adds Si epitaxy at the end of SiGe epitaxy and controls the thickness of Si epitaxy so that Si is completely consumed when reacting with Co film to form low-resistance phase CoSi2, thereby ensuring sufficient Si supply in the process of forming CoSi2 and ensuring that the low-resistance phase CoSi2 will not increase the resistance at the source / drain, thereby ensuring the performance of the PMOS transistor.

[0062] That is, the technical solution not only ensures the stress provision for the PMOS transistor by epitaxially forming SiGe in the substrate 10, while improving the carrier mobility, but also provides sufficient Si for the subsequent CoSi process to form a low-resistance phase CoSi2 by epitaxially growing Si on SiGe, thereby effectively optimizing the process of PMOS transistor and SiGe epitaxy.

[0063] See also Figure 3 and Figures 5 to 11 The method for manufacturing the PMOS transistor 100 according to the embodiment of the present invention is suitable for manufacturing the PMOS transistor 100 with a source / drain structure having a line width less than 40 nm.

[0064] Specifically, Figure 3 As shown, the preparation method comprises the following steps:

[0065] S101: providing a substrate 10, and forming source / drain trenches 11 on the substrate 10;

[0066] S102: growing SiGe material in the source / drain trench 11 to form a SiGe layer 30, and growing a Si thin film layer 40 on the surface of the SiGe layer 30 to form a stacked structure of the SiGe layer 30 and the Si thin film layer 40; and

[0067] S103: A first Co thin film layer 50 is grown on the stacked structure in the source / drain groove 11, and then annealed to allow the Co in the first Co thin film layer 50 to react with the Si in the Si thin film layer 40 to form a first CoSi2 thin film layer 60; wherein the overall structure formed in the source / drain groove 11 is the source / drain electrode, and the first CoSi2 thin film layer 60 is the upper structure of the above-mentioned source / drain electrode.

[0068] Specifically, in step S101, the material of the substrate 10 can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or it can be silicon on insulator (SOI) or germanium on insulator (GOI); or it can also be other materials, such as III-V compounds such as gallium arsenide.

[0069] In this embodiment, the substrate 10 is made of single crystal silicon (Si).

[0070] Please combine Figures 5 to 7 , exemplarily, the step of forming the source / drain trench 11 in step S101 may specifically include:

[0071] S1011: patterning the substrate 10;

[0072] S1012: forming an opening 12 in the substrate 10 (the opening 12 may be Figure 6 U-shaped grooves of the source / drain shown);

[0073] S1013 : etching the substrate 10 along the opening 12 to form source / drain trenches 11 .

[0074] In one embodiment, the opening 12 may be formed by dry etching or wet etching.

[0075] In one embodiment, the source / drain trench 11 may be in a square, U-shaped or sigma (Σ) shape.

[0076] Preferably, in a conventional manufacturing process, the source / drain trench 11 has a Σ shape.

[0077] Specifically, the sidewalls of the Σ-shaped source / drain trenches 11 are concave inwardly toward the device channel direction. This shape can effectively shorten the device channel length and meet the requirement of miniaturization of the device size.

[0078] Moreover, the Σ-shaped source / drain trench 11 has the characteristic of being greatly undercut below the gate gap. Forming stress material in the source / drain trench 11 of this shape can generate greater stress on the channel region of the device.

[0079] In one embodiment, the source / drain trench 11 may be formed by dry etching, wet etching, or a combination of dry etching and wet etching.

[0080] By way of example, the formation of a Σ-shaped source / drain trench 11 is described as follows:

[0081] The substrate 10 can be etched along the opening 12 by a RIE (reactive ion etching) dry etching process to form an inverted trapezoidal preliminary source / drain groove. Afterwards, a wet etching process is performed using tetramethylamine (TMAH) or ammonia water (NH4OH) to continue etching the preliminary source / drain groove, thereby forming a Σ-shaped source / drain groove 11.

[0082] like Figure 7 As shown, due to the limitations of other structures in the substrate 10 (such as the shallow trench isolation structure 15 and the liner 16 described below), the shape of the source / drain trench 11 in the embodiment of the present invention is not square, U-shaped or sigma (Σ) shaped, but partially Σ-shaped, such as the portion of the source / drain trench 11 closer to the gate of the PMOS transistor 100 is Σ-shaped, and the other portions are irregularly shaped.

[0083] Please combine Figure 7 and Figure 8 In step S102 , after the substrate 10 is etched to form a source / drain trench 11 , a SiGe layer 30 is grown in the source / drain trench 11 .

[0084] The SiGe layer 30 may be a single-layer structure or a multi-layer structure, which can increase the stress acting on the channel region of the PMOS transistor 100 , thereby increasing the carrier mobility of the PMOS transistor 100 and optimizing the performance of the PMOS transistor 100 .

[0085] In one embodiment, the SiGe layer 30 may be formed using a selective epitaxial process.

[0086] In one embodiment, after the Σ-shaped source / drain trenches 11 are filled with SiGe, the SiGe layer 30 may be substantially in the shape of a regular hexagon.

[0087] like Figure 7 As shown in FIG. 1 , since the source / drain trench 11 in this embodiment is not a complete Σ-shaped, the SiGe layer 30 epitaxially formed in the source / drain trench 11 is not a regular hexagon, but Figure 8 As shown, the top and one side of the SiGe layer 30 have relatively obvious regular hexagonal outlines, and still have the function of a regular hexagonal SiGe layer in a conventional process.

[0088] It is understood that Si and Co must be formed before forming the first CoSi2 thin film layer 60. Fig. 9 As shown, in this embodiment, a Si thin film layer 40 of a set thickness is first formed on the surface of the SiGe layer 30 in step S102, and then as shown in FIG. Fig.10 and Fig.11 As shown, in the subsequent step S103 , a first Co thin film layer 50 is formed on the Si thin film layer 40 , and the two are fully reacted through annealing reaction to form a first CoSi 2 thin film layer 60 .

[0089] The Si film layer 40 with a set thickness is ensured to be completely consumed during the reaction process, thereby ensuring sufficient Si supply during the formation of the first CoSi2 film layer and preventing excess Si from increasing the resistance at the source and drain.

[0090] It is understandable that if the thickness of the Si film layer 40 is too small, there will not be enough Si to react with Co in the subsequent reaction process with the first Co film layer 50 , which will affect the formation of the low-resistance phase CoSi2 and the performance of the PMOS transistor 100 .

[0091] If the thickness of the Si film layer 40 is too large, although it does not affect the transformation of the silicon-cobalt alloy into a low-resistance phase, it will have the following effects: first, the time required for the reaction with Co is too long and too much of the first Co film layer 50 needs to be deposited, which is not conducive to the formation efficiency of the PMOS transistor 100; second, the first CoSi2 film layer 60 formed by the reaction is relatively thick, which not only affects the size of the PMOS transistor 100, but also causes excessive Si loss in the source and drain regions, which increases the device leakage and affects the performance of the PMOS transistor 100.

[0092] Therefore, in step S102, during the process of growing a Si thin film layer 40 on the surface of the SiGe layer 30, a preferred embodiment is that the thickness of the Si thin film layer 40 satisfies the following conditions:

[0093] When the Si thin film layer 40 subsequently reacts with the first Co thin film layer 50 to generate the first CoSi2 thin film layer 60, all Si contained in the Si thin film layer 40 is consumed by Co and there is no insufficient supply of Si, wherein insufficient supply of Si can be understood as remaining Co that has not been reacted after annealing. That is, the thickness of the Si thin film layer 40 satisfies the condition that Si and Co fully react and neither of them remains.

[0094] Furthermore, in step S102 , the thickness of the Si thin film layer 40 deposited on the surface of the SiGe layer 30 is less than 20 nm.

[0095] Preferably, the thickness of the Si thin film layer 40 is about 12 nm.

[0096] In one embodiment, the Si thin film layer 40 may be formed by a selective epitaxial process.

[0097] In one embodiment, the first Co thin film layer 50 may be formed on the surface of the Si thin film layer 40 by physical vapor deposition.

[0098] In another embodiment, the first Co thin film layer 50 may be formed on the surface of the Si thin film layer 40 by magnetron sputtering.

[0099] In this embodiment, the first Co thin film layer 50 is formed by physical vapor deposition. It can be understood that any suitable process can be used to form the Si thin film layer 40 and the first Co thin film layer 50.

[0100] Please combine Fig.10 and Fig.11 After the first Co thin film layer 50 is deposited on the surface of the Si thin film layer 40 , the Si thin film layer 40 reacts with the first Co thin film layer 50 to form a first CoSi 2 thin film layer 60 .

[0101] Generally, the Si thin film layer 40 and the first Co thin film layer 50 can be reacted to form the first CoSi2 thin film layer 60 by heat treatment, such as laser annealing, and the heat treatment temperature can be 500°C to 750°C.

[0102] In an embodiment of the present invention, the overall structure formed in the source / drain groove 11 is the source / drain of the PMOS transistor 100, and the first CoSi2 thin film layer 60 is the upper structure of the source / drain, that is, the source / drain includes the SiGe layer 30 in the source / drain groove 11 and the first CoSi2 thin film layer 60 thereon, and the distance between the source / drain is less than 40nm.

[0103] It is worth noting that the first gate 20 may be formed on the surface of the substrate 10 first, and then the source / drain trenches 11 may be formed in the substrate 10 on both sides of the first gate 20 , and then other subsequent processes may be performed.

[0104] In the method for preparing the PMOS transistor 100 of the embodiment of the present invention, the SiGe layer 30 is first formed by performing SiGe epitaxy in the substrate 10, and the stress acting on the channel region is enhanced by using the difference between the lattice constant of SiGe and the lattice constant of Si in the substrate 10, thereby providing compressive stress for the PMOS transistor 100 and improving its carrier mobility. On the other hand, compared with Si material, Ge material itself has a higher carrier mobility, which can increase the driving current of the PMOS transistor 100, thereby achieving the purpose of improving the electrical performance of the PMOS transistor 100.

[0105] After SiGe is epitaxially grown to a certain thickness, the Si thin film layer 40 is epitaxially grown to provide sufficient Si for the subsequent CoSi2 process to form the first CoSi2 thin film layer 60. At the same time, the CoSi2 agglomeration problem caused by increasing the reaction temperature in order to convert the silicon-cobalt alloy into a low-resistance phase is avoided, thereby optimizing the process of the PMOS transistor 100 and the SiGe epitaxial growth.

[0106] See also Figure 4 , Fig.10 and Fig.11 The method for preparing the PMOS transistor of the embodiment of the present invention further comprises the following steps:

[0107] S104: preparing a first gate layer 22 on the substrate 10, wherein the material of the first gate layer 22 is polysilicon;

[0108] S105: A second Co thin film layer 70 is grown on the first gate layer 22, and then annealed so that the Co in the second Co thin film layer 70 reacts with the Si in the first gate layer 22 to generate a second CoSi2 thin film layer 23; wherein the overall structure of the formed first gate layer 22 and the second CoSi2 thin film layer 23 is the first gate 20, and the second CoSi2 thin film layer 23 is the upper structure of the first gate 20.

[0109] In addition, it is worth noting that in the embodiment of the present invention, the first Co thin film layer 50 and the second Co thin film layer 70 are grown simultaneously, and then annealed, so that the first Co thin film layer 50 and the second Co thin film layer 70 react with the Si thin film layer 40 and the first gate layer 22 simultaneously, respectively. Fig.11 As shown, the first CoSi2 thin film layer 60 and the second CoSi2 thin film layer 23 formed by the reaction are the upper structure of the source / drain and the upper structure of the gate 20 of the PMOS transistor respectively.

[0110] How to prepare the first gate layer 22 on the substrate 10 is a mature technology in the art and will not be described in detail here.

[0111] Conventionally, a first gate dielectric layer 21 may be formed on the surface of the substrate 10 , and the first gate 20 includes a first gate layer 22 formed on the surface of the first gate dielectric layer 21 and a second CoSi2 thin film layer 23 formed on the surface of the first gate layer 22 .

[0112] Specifically, the material of the first gate dielectric layer 21 may be SiO2 or a High-k dielectric material, wherein the High-k dielectric material may be one or a combination of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or HfO2-Al2O3.

[0113] In one embodiment, the first gate dielectric layer 21 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0114] It can be understood that any suitable material and deposition process can be used to form the first gate dielectric layer 21 .

[0115] In this embodiment, the first gate layer 22 is made of polysilicon.

[0116] In one embodiment, the first gate layer 22 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0117] It is understood that any suitable material and deposition process may be used to form the first gate layer 22 .

[0118] In addition, the line width of the first gate 20 in the embodiment of the present invention is less than 40nm, that is, the line width of the first gate layer 22 is less than 40nm, which can control the size of the first gate 20 and further control the size of the entire PMOS transistor 100, thereby promoting integration and miniaturization.

[0119] Moreover, as known to those skilled in the art, when the line width of the first gate 20 is less than 40 nm, the resistance caused by the line width effect is very high, and by forming a first CoSi2 thin film layer 60 of a low resistance phase, the resistance between the gate / source / drain can be controlled while enhancing device performance.

[0120] In the conventional manufacturing process of the PMOS transistor 100, the surface of the first gate 20 is a mask layer, that is, the surface of the first gate layer 22 is a mask layer. The difference between the embodiment of the present invention and the conventional process is that the mask layer on the first gate 20 is removed, and instead a second CoSi2 thin film layer 23 is formed on the surface of the first gate layer 22 to increase the conductivity between the metal wire and the polysilicon gate and promote ohmic contact.

[0121] It can be understood that since the first gate layer 22 in this embodiment is made of polysilicon, when the second Co thin film layer 70 is deposited on the surface of the first gate layer 22, there is a sufficient amount of Si in the first gate layer 22 to react with the second Co thin film layer 70 to form a second CoSi2 thin film layer 23.

[0122] Furthermore, depositing the second Co thin film layer 70 on the surface of the first gate layer 22 and depositing the first Co thin film layer 50 on the surface of the Si thin film layer 40 are performed in the same step, which can improve the production efficiency of the PMOS transistor 100 .

[0123] See also Figures 5 to 11 The PMOS transistor 100 of the embodiment of the present invention is manufactured by using the manufacturing method of the PMOS transistor 100 of any of the above embodiments.

[0124] In the PMOS transistor 100 of the embodiment of the present invention, for the beneficial effects, specific structural composition and description of the PMOS transistor 100, please refer to the above contents about the method for preparing the PMOS transistor 100, which will not be elaborated here.

[0125] See also Figures 12 to 22The CMOS circuit 1000 of the embodiment of the present invention includes: a substrate 10; at least one NMOS transistor 200 formed on the substrate 10; and at least one PMOS transistor 100 according to any of the above embodiments formed on the substrate 10.

[0126] In the CMOS circuit 1000 of the embodiment of the present invention, for the beneficial effects, specific structural composition and description of the PMOS transistor 100 in the above embodiments, please refer to the above contents related to the PMOS transistor 100, which will not be repeated here.

[0127] The CMOS circuit 1000 includes a PMOS transistor 100 and an NMOS transistor 200 which are also well known to those skilled in the art, and their working principles and related structural features are not described in detail here.

[0128] The following description will focus on the contents of the NMOS transistor 200 in the CMOS circuit 1000 and the parts of the preparation of the PMOS transistor 100 that are related to the preparation of the NMOS transistor 200 .

[0129] The NMOS transistor 200 is a conventional planar transistor. For the contents about the source / drain, please refer to the contents about the formation of the source / drain in the PMOS transistor 100 mentioned above. The difference lies in the difference in ion implantation.

[0130] Please refer to Figures 5 to 11 Furthermore, first sidewall spacers 25 are formed on both sides of the first gate 20 in the embodiment of the present invention. The first sidewall spacers 25 are located on the surface of the substrate 10 and are in contact with both side surfaces of the first gate 20 .

[0131] In this embodiment, the first spacer 25 is used to protect the sidewall of the first gate 20 from being damaged during subsequent etching or ion implantation, thereby ensuring the performance of the first gate 20 .

[0132] The material of the first sidewall spacer 25 may be silicon oxide, silicon carbide, silicon nitride, or silicon oxynitride.

[0133] In one embodiment, the first spacer 25 may be a stacked structure of silicon oxide-silicon nitride, or a stacked structure of silicon nitride-silicon oxide-silicon nitride, or a stacked structure of silicon oxide-silicon nitride-silicon oxide.

[0134] In one embodiment, the first spacer 25 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0135] It can be understood that any suitable material and deposition process can be used to form the first spacer 25 .

[0136] In addition, before forming the first spacer 25 , a low-doped drain (LDD) may be formed in the substrate 10 at both sides of the gate 20 to prevent hot electron degradation effects.

[0137] Please combine Figures 5 to 9 Before the second Co thin film layer 70 is grown on the surface of the first gate layer 22, the first gate mask layer 24 is formed on the surface of the first gate layer 22. Furthermore, the preparation step S105 of the first gate 20 of the embodiment of the present invention may specifically include the following steps:

[0138] S1051: removing the first gate mask layer 24 to expose the upper surface of the first gate layer 22; and

[0139] S1052 : growing a second Co thin film layer 70 on the surface of the first gate layer 22 , and then performing annealing treatment so that Co in the second Co thin film layer 70 reacts with Si in the first gate layer 22 to generate a second CoSi2 thin film layer 23 .

[0140] In conventional process flow, the material of the first gate mask layer 24 can be silicon nitride. Since silicon nitride does not react with inorganic acids other than hydrofluoric acid, it has strong corrosion resistance and is not wetted or corroded by many molten metals or alloys such as aluminum, copper or nickel. Therefore, it can effectively protect the first gate layer 22 from being damaged during the process.

[0141] In one embodiment, the first gate mask layer 24 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0142] In another embodiment, the first gate mask layer 24 may be formed by a low pressure atomic layer deposition method.

[0143] It can be understood that any suitable material and deposition process can be used to form the first gate mask layer 24 .

[0144] The embodiment of the present invention is different from the conventional process in that the first gate mask layer 24 on the first gate 20 is removed, and instead a second CoSi2 thin film layer 23 is formed on the surface of the first gate layer 22 to increase the conductivity between the metal wire and the polysilicon gate and promote ohmic contact.

[0145] See also Figures 12 to 22Furthermore, in the embodiment of the present invention, a second gate 210 is formed on the surface of the active region of the substrate 10 corresponding to the NMOS transistor 200, wherein a second gate dielectric layer 211 is formed on the surface of the substrate 10 to separate the second gate 210 and the active region, and the second gate 210 specifically includes a second gate layer 212 located on the surface of the second gate dielectric layer 211 and a third CoSi2 thin film layer 213 formed on the surface of the second gate layer 212. In addition, a fourth CoSi2 thin film layer 216 is also formed on the surface of the substrate 10 corresponding to the NMOS transistor 200.

[0146] The specific structure of the second gate 210 is the same as that of the first gate 20 , and the materials and process steps used are also basically the same. For the content of the second gate 210 , please refer to the content of the first gate 20 in the PMOS transistor 100 above, and no further details will be given here.

[0147] Second sidewalls 215 are also formed on both sidewalls of the second gate 210 . For details about the second sidewalls 215 , reference may be made to the above details about the first sidewalls 24 , and no detailed description will be given here.

[0148] In the present embodiment, the second gate mask layer 214 is also removed, and instead a third Co thin film layer 80 is grown on the surface of the second gate layer 212 and then reacted to form a third CoSi2 thin film layer 213, and a fourth Co thin film layer 90 is grown on the surface of the substrate 10 corresponding to the NMOS transistor 200 to form a fourth CoSi2 thin film layer 216. In this way, the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 can be used to increase the conductivity between the metal wire and the polysilicon gate, promote ohmic contact, and enhance device performance.

[0149] The removal of the second gate mask layer 214 and the removal of the first gate mask layer 24 may be achieved in the same step, that is, the first gate mask layer 24 and the second gate mask layer 214 may be removed at the same time.

[0150] How to remove the gate mask layer is a mature technology in this field and will not be described in detail here.

[0151] The formation of the third CoSi 2 thin film layer 213 and the fourth CoSi 2 thin film layer 216 can also be achieved in the same step as the formation of the first CoSi 2 thin film layer 60 and the formation of the second CoSi 2 thin film layer 23 .

[0152] That is to say, after removing the first gate mask layer 24 and the second gate mask layer 214 at the same time, a Co thin film layer can be deposited on the surface of the entire CMOS circuit 1000, so that the Co thin film is deposited on the surface of the Si thin film layer 40, the first gate layer 22, the second gate layer 212 and the source and drain regions of the NMOS transistor 200 for reaction, thereby forming the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 at the same time or in a shorter period of time, thereby further improving the production efficiency of the CMOS circuit 1000.

[0153] It can be understood that since the second gate layer 212 in this embodiment is made of polysilicon like the first gate layer 22, and the substrate 10 is also a silicon substrate 10, when the Co thin film layer is deposited on the surface of the second gate layer 212 and the surface of the source and drain regions of the NMOS transistor 200, there is sufficient Si in the second gate layer 212 and the source and drain regions of the NMOS transistor 200 to react with the Co thin film layer, thereby forming a third CoSi2 thin film layer 213 and a fourth CoSi2 thin film layer 216.

[0154] Furthermore, in one embodiment, a SiGe layer 30 may be formed in the substrate 10 on both sides of the second gate 210 of the NMOS transistor 200 to further improve the electrical performance of the CMOS circuit 1000 .

[0155] The specific steps may refer to the above content of forming the SiGe layer 30 in the substrate 10 on both sides of the first gate 20, and will not be described in detail here.

[0156] In the CMOS circuit 1000 , for the PMOS transistor 100 , a first gate dielectric layer 21 is formed on the surface of the substrate 10 , and the first gate 20 includes a first gate layer 22 located on the surface of the first gate dielectric layer 21 and a second CoSi2 thin film layer 23 located on the surface of the first gate layer 22 .

[0157] See also Figures 12 to 22 For the NMOS transistor 200 , a second gate dielectric layer 211 is formed on the surface of the substrate 10 , and the second gate 210 includes a second gate layer 212 located on the surface of the second gate dielectric layer 211 and a third CoSi2 thin film layer 213 located on the surface of the second gate layer 212 .

[0158] Under conventional processes, before the third Co thin film layer 80 is grown on the surface of the second gate layer 212 , a second gate mask layer 214 is formed on the surface of the second gate layer 212 . In addition, a first mask layer 13 is formed on the surface of the substrate 10 on both sides of the second gate 210 .

[0159] Please combine Figures 17 to 22Based on the above basic structure, more steps in the preparation process of the PMOS transistor 100: after growing the Si thin film layer 40 on the SiGe layer 30, the steps may include:

[0160] S106: forming a photoresist layer 14 on the surfaces of the first gate mask layer 24 and the Si thin film layer 40;

[0161] S107: removing the first mask layer 13 to expose the source and drain regions of the NMOS transistor 200;

[0162] S108: removing the photoresist layer 14 to expose the surface of the first gate mask layer 24 and the surface of the Si thin film layer 40;

[0163] S109: removing the first gate mask layer 24 and the second gate mask layer 214 to expose the surface of the first gate layer 22 and the surface of the second gate layer 212; and

[0164] S110: A second Co thin film layer 70, a third Co thin film layer 80 and a fourth Co thin film layer 90 are deposited on the surface of the first gate layer 22, the surface of the second gate layer 212 and the source and drain regions of the NMOS transistor 200, respectively, and then annealed to react and form a second CoSi2 thin film layer 23, a third CoSi2 thin film layer 213 and a fourth CoSi2 thin film layer 216, respectively.

[0165] In step S201, the first gate mask layer 24 and the Si thin film layer 40 are first covered with a photoresist to prevent the Si thin film layer 40 from being damaged when the first mask layer 13 on the surface of the substrate 10 is removed. The first mask layer 13 can be formed in the process of forming the first gate 20 on the substrate 10. The material and composition of the first gate mask layer 24 can refer to the above content, and no detailed description is given here.

[0166] In one embodiment, the process of removing the photoresist layer 14 may be a wet cleaning or an ashing process.

[0167] If an ashing process is used to remove the photoresist layer 14 , after the ashing process is completed, residual photoresist and byproducts of the ashing process will exist on the surface of the substrate 10 , and the surface of the substrate 10 needs to be wet cleaned.

[0168] Therefore, in this embodiment, wet cleaning is used to remove the first gate mask layer 24 and the photoresist layer 14 on the Si thin film layer 40 as an example.

[0169] Specifically, the wet chemical substances that can be used for wet cleaning are aqueous solutions of ammonia and hydrogen peroxide. The CMOS circuit 1000 having a photoresist layer 14 on its surface is placed in a reaction chamber, and the photoresist layer 14 is removed by spraying the aqueous solution of ammonia and hydrogen peroxide on the surface of the photoresist layer 14.

[0170] In this embodiment, the first gate mask layer 24 on the first gate 20 and the second gate mask layer 214 on the second gate 210 are removed at the same time, and instead, a second CoSi2 thin film layer 23 is formed on the surface of the first gate layer 22, a third CoSi2 thin film layer 213 is formed on the surface of the second gate layer 212, and a fourth CoSi2 thin film layer 216 is formed in the source and drain regions of the NMOS transistor 200. The second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 are used to increase the conductivity between the metal wire and the polysilicon gate, promote ohmic contact, and enhance device performance.

[0171] In this embodiment, the formation of the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216 can be achieved in the same step as the formation of the first CoSi2 thin film layer 60. Fig.21 As shown, after removing the first gate mask layer 24 and the second gate mask layer 214, a Co thin film layer is deposited on the surface of the entire CMOS circuit 1000, so that the Co thin film layer is respectively deposited on the surface of the Si thin film layer 40, the first gate layer 22, the second gate layer 212 and the surface of the source and drain region substrate 10 of the NMOS transistor 200 to react, thereby forming a first CoSi2 thin film layer 60, a second CoSi2 thin film layer 23, a third CoSi2 thin film layer 213 and a fourth CoSi2 thin film layer 216 at the same time or in a shorter period of time, further improving the production efficiency of the CMOS circuit 1000.

[0172] It can be understood that since the Si thin film layer 40 in this embodiment is formed by Si epitaxy, the first gate layer 22 and the second gate layer 212 are both made of polycrystalline silicon, and the substrate 10 is also a silicon substrate. Therefore, when the Co thin film layer is simultaneously deposited on the surfaces of the Si thin film layer 40, the first gate layer 22, the second gate layer 212 and the substrate 10, there is sufficient Si in the Si thin film layer 40, the first gate layer 22, the second gate layer 212 and the substrate 10 to react with the Co thin film layer to form a first CoSi2 thin film layer 60, a second CoSi2 thin film layer 23, a third CoSi2 thin film layer 213 and a fourth CoSi2 thin film layer 216.

[0173] Please combine Figures 12 to 22 , and see Fig.23 The method for manufacturing a CMOS circuit 1000 according to an embodiment of the present invention is used to manufacture the CMOS circuit 1000 according to any of the above embodiments. The method may include the following steps:

[0174] S201: providing a substrate 10, forming at least two active regions on the substrate 10, wherein two adjacent active regions are isolated by a shallow trench isolation structure 15;

[0175] S202: forming a source / drain trench 11 of the PMOS transistor 100 in an active region corresponding to the PMOS transistor 100;

[0176] S203: growing SiGe material in the source / drain trench 11 to form a SiGe layer 30, and growing a Si thin film layer 40 on the surface of the SiGe layer 30 to form a stacked structure of the SiGe layer 30 and the Si thin film layer 40; and

[0177] S204 : growing a first Co thin film layer 50 on the surface of the stacked structure, and performing annealing treatment to make the first Co thin film layer 50 react with Si in the Si thin film layer 40 to generate a first CoSi2 thin film layer 60 .

[0178] For the specific contents of each step of the method for preparing the CMOS circuit 1000 according to the embodiment of the present invention and the specific structures involved therein, please refer to the above contents on the preparation of the PMOS transistor 100 and the structural composition of the CMOS circuit 1000, which will not be elaborated here.

[0179] The new technical features mentioned in the above preparation method will be described below.

[0180] Please continue reading Figures 12 to 22 In the embodiment of the present invention, a plurality of shallow trench isolation (STI) structures 15 are formed on the substrate 10 and are spaced apart from each other. The shallow trenches divide the substrate 10 into a plurality of active regions. The first gate 20 of the PMOS transistor 100 and the second gate 210 of the NMOS transistor 200 are respectively located between two adjacent shallow trench isolation structures 15, that is, the first gate 20 and the second gate 210 are respectively located on the corresponding active regions.

[0181] Specifically, the shallow trench isolation structure 15 can be formed by first etching a shallow trench at a set position of the substrate 10 and then filling the shallow trench with an insulating material.

[0182] The insulating material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon dioxide.

[0183] In this embodiment, the material filled in the shallow trench isolation structure 15 is silicon dioxide.

[0184] Different from the conventional process, a liner 16 is formed between the shallow trench isolation structure 15 and the substrate 10 in the embodiment of the present invention, and the SiGe layer 30 is in contact with the side of the liner 16. The liner 16 is mainly used to isolate the shallow trench isolation structure 15 from the SiGe layer 30, and prevent the SiGe layer 30 from extending into the substrate 10 of the adjacent transistor when the SiGe layer 30 is epitaxially formed in the source / drain trench 11.

[0185] Exemplarily, after forming a shallow trench, the liner 16 may be formed by depositing an insulating isolation material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon dioxide, on the substrate 10, so that the insulating isolation material adheres to the shallow trench to form a layer of a set thickness, and then the insulating material is continued to be filled in the remaining space of the shallow trench to form a shallow trench isolation structure 15, so that the liner 16 is located between the substrate 10 and the shallow trench isolation structure 15.

[0186] In one embodiment, the liner 16 may be a thermal oxide layer, which may be formed by a furnace thermal oxidation process.

[0187] In addition, since the SiGe layer 30 is in contact with the liner 16 in the substrate 10, the portion of the SiGe layer 30 located above the surface of the substrate 10 will extend to cover the portion of the surface of the shallow trench isolation structure 15, which can increase the volume and surface area of ​​the SiGe layer 30, thereby increasing the volume and surface area of ​​the first CoSi2 thin film layer 60 formed on the surface of the SiGe layer 30, thereby achieving the purpose of increasing the contact area.

[0188] On the basis of preparing the above CMOS circuit 1000, further, the NMOS transistor 200 may specifically include:

[0189] An active region, the active region including a source / drain region for forming a source / drain of the NMOS transistor 200;

[0190] A second gate dielectric layer 211 formed on the active region; and

[0191] The second gate 210 is formed on the second gate dielectric layer 211 , and the source / drain regions are located on both sides of the second gate 210 . The second gate 210 includes a second gate layer 212 . The material of the second gate layer 212 is the same as that of the first gate layer 22 , both of which are polysilicon.

[0192] Please combine Figures 12 to 22 Also see Fig.24 Based on the structure of the NMOS transistor 200, a method for manufacturing a CMOS circuit 1000 according to another embodiment of the present invention may include the following steps:

[0193] S301: providing a substrate 10, forming at least two active regions on the substrate 10, wherein two adjacent active regions are isolated by a shallow trench isolation structure 15;

[0194] S302: forming a first gate layer 22 of the PMOS transistor 100 and a second gate layer 212 of the NMOS transistor 200 simultaneously on each active region;

[0195] S303: forming source / drain trenches 11 of the PMOS transistor 100 in the active region corresponding to the PMOS transistor 100;

[0196] S304: growing SiGe material in the source / drain trench 11 to form a SiGe layer 30, and growing a Si thin film layer 40 on the surface of the SiGe layer 30 to form a stacked structure of the SiGe layer 30 and the Si thin film layer 40;

[0197] S305: simultaneously growing a first Co thin film layer 50, a second Co thin film layer 70, a third Co thin film layer 80 and a fourth Co thin film layer 90 on the stacked structure, the first gate layer 22, the second gate layer 212 and the source / drain region of the NMOS transistor 200; and

[0198] S306: Annealing treatment to make the first Co thin film layer 50, the second Co thin film layer 70, the third Co thin film layer 80 and the fourth Co thin film layer 90 react with the corresponding Si respectively to generate the first CoSi2 thin film layer 60, the second CoSi2 thin film layer 23, the third CoSi2 thin film layer 213 and the fourth CoSi2 thin film layer 216.

[0199] For the specific contents of each step in the method for preparing the CMOS circuit 1000 of this embodiment and the specific structures involved therein, please refer to the above contents about the preparation of the PMOS transistor 100 and the structural composition of the CMOS circuit 1000, which will not be elaborated here.

[0200] Furthermore, in order to realize electrical connection between the CMOS circuit 1000 and peripheral circuits or devices, a contact process of the CMOS circuit 1000 is required to supply signal lines of the peripheral circuits for connection. The contact process may specifically include the following steps:

[0201] S401: Fig. 22 A first insulating layer is deposited on the surface of the CMOS circuit 1000 shown. The material of the first insulating layer may be silicon nitride. The deposition process may refer to the deposition process of each layer described above.

[0202] S402: depositing a layer of HARP (High Aspect Ratio Process, HARP) film on the surface of the insulating layer, wherein the material of the HARP film may be silicon dioxide;

[0203] S403: depositing an oxide layer on the surface of the HARP film. This deposition step can be achieved by using a HDP (High-Density Plasma)-CVD process. The material of the oxide layer can be silicon dioxide.

[0204] S404: depositing a second insulating layer on the surface of the oxide layer, wherein the second insulating layer may be made of silicon nitride;

[0205] S405: forming a photoresist layer on the surface of the second insulating layer, and forming a plurality of holes in the photoresist layer, wherein the plurality of holes correspond to positions of a plurality of contact holes to be formed on the CMOS circuit 1000, and the plurality of contact holes correspond to the gate, source and drain of the PMOS transistor 100 and the NMOS transistor 200, respectively;

[0206] S406: etching the CMOS circuit 1000 through the plurality of holes to form a plurality of contact holes penetrating the second insulating layer, the oxide layer, the HARP film and the first insulating layer from top to bottom to contact the first CoSi2 film layer 60, the second CoSi2 film layer 23, the third CoSi2 film layer 213 and the fourth CoSi2 film layer 216;

[0207] S407: removing the photoresist layer to expose the second insulating layer on which a plurality of contact holes are formed;

[0208] S408: depositing a metal layer on the surface of the second insulating layer, so that the metal of the metal layer is deposited along the plurality of contact holes to contact the first CoSi2 film layer 60, the second CoSi2 film layer 23, the third CoSi2 film layer 213 and the fourth CoSi2 film layer 216 respectively, the metal that achieves contact can be understood as a metal signal line, and the material of the metal layer can be titanium nitride;

[0209] S409: remove the metal layer on the surface of the second insulating layer, and retain multiple metal signal lines in multiple contact holes that are respectively in contact with the first CoSi2 film layer 60, the second CoSi2 film layer 23, the third CoSi2 film layer 213 and the fourth CoSi2 film layer 216 to achieve contact with the CMOS circuit 1000.

[0210] Through the above steps S401 to S409 , metal signal lines are prepared on the CMOS circuit 1000 , so that the CMOS circuit 1000 has the ability to be electrically connected to peripheral circuits and the like.

[0211] In the description of this specification, the description with reference to the terms "Example 1", "Example 2", etc. means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0212] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a PMOS transistor, characterized in that: The method is applicable to the manufacture of a PMOS transistor with a source / drain structure having a line width less than 40 nm, and the method comprises the following steps: Providing a substrate, and forming source / drain trenches on the substrate; Growing SiGe material in the source / drain trench to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; and Growing a first Co thin film layer on the stacked structure, and then performing an annealing treatment to allow Co in the first Co thin film layer to react with Si in the Si thin film layer to form a first CoSi2 thin film layer; The overall structure formed in the source / drain groove is a source / drain electrode, and the first CoSi2 thin film layer is an upper structure of the source / drain electrode.

2. The method for preparing a PMOS transistor according to claim 1, characterized in that: The method further comprises the following steps: A first gate layer is prepared on the substrate, wherein the material of the first gate layer is polysilicon; Growing a second Co thin film layer on the first gate layer, and then performing an annealing treatment so that Co in the second Co thin film layer reacts with Si in the gate layer to form a second CoSi2 thin film layer; The overall structure of the first gate layer and the second CoSi2 thin film layer is the first gate, and the second CoSi2 thin film layer is the upper structure of the first gate.

3. The method for preparing a PMOS transistor according to claim 2, characterized in that: The first Co thin film layer and the second Co thin film layer are grown simultaneously and then annealed. The first CoSi2 thin film layer and the second CoSi2 thin film layer generated by the reaction are the upper structure of the source / drain and the upper structure of the first gate respectively.

4. The method for preparing a PMOS transistor according to claim 1, characterized in that: In the step of growing a Si thin film layer on the surface of the SiGe layer, the thickness of the Si thin film layer satisfies: When the first Co thin film layer subsequently reacts with the first Co thin film layer to generate the first CoSi2 thin film layer, all Si contained in the Si thin film layer is consumed by Co and there is no insufficient Si supply. The insufficient Si supply means that there is remaining Co that has not been reacted after the annealing treatment.

5. The method for preparing a PMOS transistor according to claim 4, characterized in that: The thickness of the Si thin film layer is less than 20 nm.

6. A PMOS transistor, characterized in that: The method is prepared according to any one of claims 1 to 5.

7. A CMOS circuit, characterized in that: include: substrate; at least one NMOS transistor formed on the substrate; as well as At least one PMOS transistor according to claim 6 is formed on the substrate.

8. The CMOS circuit according to claim 7, characterized in that: The NMOS transistor comprises: an active region, the active region comprising a source / drain region for forming a source / drain of the NMOS transistor; a second gate dielectric layer formed on the active area; and a second gate formed on the second gate dielectric layer, the source / drain regions being located at both sides of the second gate, and the second gate comprising a second gate layer; Wherein, the material of the second gate layer is polysilicon.

9. A method for manufacturing a CMOS circuit, for manufacturing the CMOS circuit according to any one of claims 7 to 8, characterized in that: The following steps are involved: Providing a substrate, forming at least two active regions on the substrate, and two adjacent active regions are isolated by a shallow trench isolation structure; forming a source / drain trench of the PMOS transistor in the active area corresponding to the PMOS transistor; Growing SiGe material in the source / drain trench of the PMOS transistor to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; as well as A first Co thin film layer is grown on the surface of the stacked structure and annealed to allow the first Co thin film layer to react with Si in the Si thin film layer to generate a first CoSi2 thin film layer.

10. The preparation method according to claim 9, characterized in that: The NMOS transistor comprises: an active region, the active region comprising a source / drain region for forming a source / drain of the NMOS transistor; a second gate dielectric layer formed on the active area; and a second gate formed on the second gate dielectric layer, the source / drain regions being located at both sides of the second gate, and the second gate comprising a second gate layer; Wherein, the first gate layer and the second gate layer are both made of polysilicon.

11. The preparation method according to claim 10, characterized in that: The method comprises the following steps: Providing a substrate, forming at least two active regions on the substrate, and two adjacent active regions are isolated by a shallow trench isolation structure; Simultaneously forming a first gate layer of the PMOS transistor and a second gate layer of the NMOS transistor on each of the active regions; forming a source / drain trench of the PMOS transistor in the active area corresponding to the PMOS transistor; Growing SiGe material in the source / drain trench of the PMOS transistor to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a stacked structure of the SiGe layer and the Si thin film layer; and simultaneously growing a first Co thin film layer, a second Co thin film layer, a third Co thin film layer and a fourth Co thin film layer on the stacked structure, the first gate layer, the second gate layer and the source / drain region of the NMOS transistor respectively; and Annealing treatment allows the first Co thin film layer, the second Co thin film layer, the third Co thin film layer and the fourth Co thin film layer to react with corresponding Si respectively to generate a first CoSi2 thin film layer, a second CoSi2 thin film layer, a third CoSi2 thin film layer and a fourth CoSi2 thin film layer.

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