Redistribution structures, contact structures and methods of forming same

Abstract

The embodiment of the invention provides a redistribution structure. The redistribution structure comprises a metal wire; a first dielectric layer disposed over the metal line; a first etch stop layer (ESL) disposed over the first dielectric layer; a second dielectric layer disposed over the first ESL; and a conductive via extending through the second dielectric layer, the first ESL, and the first dielectric layer to contact the metal line. A lower portion of the second dielectric layer extends downwardly through the first ESL and the first dielectric layer and partially into the metal line. The embodiment of the invention also relates to a contact structure and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to a redistribution structure, a contact structure, and a method for forming the same. Background Art

[0002] A redistribution layer (RDL) is an additional metal layer that redirects signals from pads of an integrated circuit (IC) die to other locations for better access. Because the RDL structure is typically located on top of the die, it is typically where test pads or probe pads, such as wafer acceptance test (WAT) pads, are located. By probing the WAT pads, process control monitoring data is generated to improve yield and reduce defects. Test pads can be substantially larger than the line spacing in the RDL and occupy spaces that can be used to place functional pads for three-dimensional (3D) packaging. Summary of the invention

[0003] Some embodiments of the present application provide a redistribution structure, including: a metal line; a first dielectric layer, disposed above the metal line; a first etch stop layer (ESL), disposed above the first dielectric layer; a second dielectric layer, disposed above the first etch stop layer; and a conductive via, extending through the second dielectric layer, the first etch stop layer and the first dielectric layer to contact the metal line, wherein a lower portion of the second dielectric layer extends downward through the first etch stop layer and the first dielectric layer, and partially extends into the metal line.

[0004] Other embodiments of the present application provide a contact structure, including: a passivation layer; a metal line disposed above the passivation layer; a first dielectric layer disposed above the metal line; a metal component disposed in the first dielectric layer and in contact with a top surface of the metal line; a second dielectric layer disposed above the first dielectric layer and the top surface of the metal component; and a conductive via extending through the second dielectric layer and the first dielectric layer to contact the metal line, wherein the top surfaces of the first dielectric layer and the metal component are coplanar.

[0005] Still other embodiments of the present application provide a method for forming a contact structure, comprising: depositing a first dielectric layer above a metal line; depositing a first etch stop layer (ESL) above the first dielectric layer; forming a test contact opening through the first dielectric layer and the first etch stop layer to expose a portion of the metal line; forming a test pad above the test contact opening; performing a test by contacting the test pad with a probe; after performing the test, removing the test pad to expose the test contact opening; and after removing the test pad, depositing a second dielectric layer above the first etch stop layer and the test contact opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A flow chart of a method 100 for forming sacrificial test pads for testing purposes and subsequently removing the sacrificial test pads to free up space for functional pads is shown in accordance with various aspects of an embodiment of the present disclosure.

[0008] Figures 2 to 18 Including the various aspects of the embodiments of the present disclosure in the implementation Figure 1 A partial cross-sectional view of a work-in-progress (WIP) structure undergoing various stages of operation during method 100 in FIG.

[0009] Fig.19 A flow chart of a method 300 for forming a sacrificial test pad for testing purposes and subsequently removing portions thereof to make room for a functional pad is shown in accordance with various aspects of an embodiment of the present disclosure.

[0010] Figure 20 to Figure 24 Including the various aspects of the embodiments of the present disclosure in the implementation Fig.19 A partial cross-sectional view of a WIP structure undergoing various stages of operation during method 300 in FIG.

[0011] Fig.25 A flow chart of a method 400 for forming sacrificial test pads for testing purposes and subsequently patterning the sacrificial test pads to free up space for functional pads is shown in accordance with various aspects of embodiments of the present disclosure.

[0012] Figures 26 to 30 Including the various aspects of the embodiments of the present disclosure in the implementation Fig.25 A partial cross-sectional view of a WIP structure undergoing various stages of operation during method 400 in FIG. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0016] Redistribution layer (RDL) is an additional metal layer that redirects the signal from the pad of the integrated circuit (IC) die to other locations for better access. Because the RDL structure is usually located on the top of the die and is formed at the end of the back-end process, it is usually the location of the test pad or detection pad (such as wafer acceptance test (WAT) pad). By detecting the WAT pad, process control monitoring data is generated to improve yield and reduce defects. Existing test pads are generally larger than the line spacing in the RDL. Although inserting test pads is necessary for detection, their presence may increase the distance between metal parts, and they may occupy the interval where the through hole may be engaged. The implementation of the test pad causes little or no problem to single-die packaging or two-dimensional (2D) packaging. However, it is not very compatible with three-dimensional (3D) packaging. The test pad not only increases the spacing of the metal parts, but also may hinder the effective placement of through holes and contact pads for device stacking.

[0017] Embodiments of the present disclosure provide a method for forming a sacrificial test pad that can be used for probe testing during acceptance testing and removing or trimming the sacrificial test pad to increase the through-hole bonding area. An exemplary process includes: depositing a first dielectric layer over a metal line in a redistribution layer; depositing a first etch stop layer (ESL) over the first dielectric layer; forming a test contact opening through the first dielectric layer and the first ESL to expose a portion of the metal line; forming a sacrificial test pad over the test contact opening; performing a test by contacting the sacrificial test pad with a probe; after performing the test, removing the sacrificial test pad to expose the test contact opening; and after removing the test pad, depositing a second dielectric layer over the first ESL and the test contact opening. In other exemplary processes, the sacrificial test pad is flattened or patterned to have a smaller form factor so that it does not hinder the bonding of the contact through-hole.

[0018] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 , Fig.19 and Fig.25 Flowcharts illustrating methods 100, 300, and 400 for forming a test pad, followed by removal, planarization, or patterning of the test pad, according to various aspects of embodiments of the present disclosure. Methods 100, 300, and 400 are merely examples and are not intended to limit embodiments of the present disclosure to those explicitly shown in methods 100, 300, or 400. Additional steps may be provided before, during, and after methods 100, 300, or 400, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the respective methods. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 18 Describing method 100, Figures 2 to 18is a partial cross-sectional view of a work-in-progress (WIP) structure 200 (or an intermediate structure 200) at different manufacturing stages according to an embodiment of the method 100. Figures 2 to 7 and Figure 20 to Figure 24 Describing method 300, Figures 2 to 7 and Figure 20 to Figure 24 is a partial cross-sectional view of the WIP structure 200 at different manufacturing stages according to an embodiment of the method 300. Figures 2 to 7 and Figures 26 to 30 Describing method 400, Figures 2 to 7 and Figures 26 to 30 4 is a partial cross-sectional view of a WIP structure 200 at different manufacturing stages according to an embodiment of the method 400. Because the WIP structure 200 will be manufactured into a semiconductor structure 200 at the end of the manufacturing process, the WIP structure 200 may be referred to as a semiconductor structure 200 as the context requires. In addition, throughout the present application and across different embodiments, the same reference numerals represent the same components having similar structures and compositions, unless otherwise specified.

[0019] refer to Figure 1 and Figure 2 , the method 100 includes block 102, where a WIP structure 200 is received. The WIP structure 200 includes a top metal layer 203 above the interconnect structure 202. Figure 2, the WIP structure 200 includes a substrate 201, an interconnect structure 202 disposed above the substrate 201, and a top metal layer 203 above the interconnect structure 202. As will be further described below, the substrate 201 is formed of a semiconductor material and has undergone a front-end-of-line (FEOL) process. Such a FEOL process can form individual transistors on the substrate 201 to provide different functions. For example, these individual transistors can form a central processing unit (CPU), a graphics processing unit (GPU), an access transistor for a memory device, or an image signal processing (ISP) circuit. The transistor can be a planar transistor or a multi-gate transistor. A planar device refers to a device having a gate structure with a planar surface that engages a semiconductor active region. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and full-all-around gate (GAA) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that may extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor may also be referred to as a surround gate transistor (SGT) or a multi-bridge channel (MBC) transistor. The channel region of a GAA transistor may be formed by nanowires, nanosheets, or other nanostructures, and therefore, a GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. The interconnect structure 202 includes multiple metal layers and is part of a back-end of line (BEOL) structure. A top metal layer 203 may include a top metal feature 206 disposed in a top dielectric layer 204.

[0020] In some embodiments, substrate 201 includes silicon (Si). Alternatively or additionally, substrate 201 includes: another elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some embodiments, substrate 201 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some embodiments, substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be manufactured using isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Because method 100 is implemented on layers and structures above substrate 201 and interconnect structure 202, for simplicity, substrate 201 and interconnect structure 202 are only described in detail. Figure 2 It is shown in dashed lines in the figure and is omitted from the remaining drawings.

[0021] The interconnect structure 202 includes about five (5) to about twenty (20) metal layers (or metallization layers). Each metal layer of the interconnect structure 202 includes a plurality of vias and metal lines embedded in an inter-metal dielectric (IMD) layer. The vias and metal lines may be formed of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), or aluminum (Al). In one embodiment, they are formed of copper (Cu). The IMD layer may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG) and / or other suitable dielectric materials. In one embodiment, the IMD layer includes silicon oxide.

[0022] As with the IMD layer in the interconnect structure 202, the top dielectric layer 204 of the top metal layer 203 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG) and / or other suitable dielectric materials. In one embodiment, the top dielectric layer 204 includes silicon oxide. The top metal feature 206 in the top metal layer 203 may include copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), aluminum (Al) or aluminum copper (Al-Cu).

[0023] Figure 2 The WIP structure 200 in FIG. 1 includes a passivation layer 208 above the top metal layer 203. The passivation layer 208 may include silicon nitride and may have a thickness between about 1 μm and about 2 μm to shield stress from underlying structures. A redistribution layer is disposed above the passivation layer 208. Figure 2 In the partial cross-sectional view in FIG. 1 , the redistribution layer includes a first redistribution component 210, a second redistribution component 212, and a third redistribution component 214. Each of the first redistribution component 210, the second redistribution component 212, and the third redistribution component 214 redirects the signal to other locations for better access or spacing. When the redistribution component is elongated Figure 2 When the first redistribution component 210 is shown in FIG. 1 , it may also be referred to as a metal line. In some embodiments, the first redistribution component 210, the second redistribution component 212, and the third redistribution component 214 may include copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), or aluminum (Al). In one embodiment, they include copper (Cu). Figure 2 In some embodiments shown in , the contact via 209 extends continuously from the first redistribution feature 210 through the passivation layer 208 to contact the top metal feature 206. To prevent oxygen diffusion or electromigration, a dielectric liner 216 is disposed along the top surface and sidewalls of the first redistribution feature 210, the second redistribution feature 212, and the third redistribution feature 214. In some examples, the dielectric liner 216 may include silicon nitride and have a thickness between about 100 nm and about 200 nm. Figure 2 As shown in , a first dielectric layer 218 and a first etch stop layer (ESL) 220 are sequentially deposited over the dielectric liner 216. In some embodiments, the first dielectric layer 218 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG) and / or other suitable dielectric materials. In one embodiment, the first dielectric layer 218 includes silicon oxide. The first ESL 220 may include silicon nitride. The first dielectric layer 218 may have a thickness between about 300nm and about 700nm. The first ESL 220 may have a thickness between about 300nm and about 1000nm.

[0024] refer to Figure 1 and Figure 2, method 100 includes frame 104, wherein test contact opening 222 is formed to expose the portion of first metal line 206 located in top metal layer 203. In frame 104, first ESL 220 and first dielectric layer 218 are patterned to form test contact opening 222 to expose top metal component 206. Although not explicitly shown in the figure, the patterning in frame 104 includes a combination of photolithography and etching steps. For example, at least one hard mask is deposited above first ESL 220 using CVD, flowable CVD (FCVD) or a suitable process. Then a photoresist layer is deposited above at least one hard mask layer using spin coating. The deposited photoresist layer can undergo a pre-exposure baking process, exposure to radiation reflected from a photomask or transmitted through a photomask, a post-exposure baking process and a developing process to form a patterned photoresist. Then at least one hard mask layer is etched using the patterned photoresist as an etching mask to form a patterned hard mask. The patterned hard mask is then used as an etching mask to etch the first ESL 220 to form the test contact opening 222. The appropriate etching process in box 104 may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process in box 104 may be a dry etching process (e.g., a reactive ion etching (RIE) process) including using an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), or a chlorine-containing gas (e.g., Cl2 and / or BCl3). Figure 2 , the first contact opening 222 extends completely through the first ESL 220 and the first dielectric layer 218 to expose the top metal feature 206. In some examples, the test contact opening 222 has a first width W1 along a horizontal direction relative to the substrate 201. The first width W1 can be between about 10 μm and about 20 μm. Although not explicitly shown in the figure, the test contact opening 222 can be circular in a top view along the Z direction. When the test contact opening 222 is circular or substantially circular, the first width W1 is the diameter of the circular shape of the test contact opening 222.

[0025] refer to Figure 1 and Figures 3 to 6 The method 100 includes block 106, where a sacrificial pad 232 is formed over the test contact opening 222. The operations in block 116 may include: depositing a barrier layer 224 ( Figure 3 ); a seed layer 226 is deposited over the barrier layer 224 ( Figure 3 ); forming a patterned mask 228 ( Figure 4 ); depositing a metal filler 232 ( Figure 5 and a patterned barrier layer 224 and a seed layer 226 ( Figure 6In some embodiments, the sacrificial pad 232 is formed using electroplating or chemical plating.

[0026] refer to Figure 3 , a barrier layer 224 is conformally deposited over the WIP structure 200, including over the test contact opening 222. The barrier layer 224 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN), and may have a thickness of about Peace The barrier layer 224 may be deposited using physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD), or CVD. A seed layer 226 is then deposited over the barrier layer 224. The seed layer 226 includes copper (Cu) and may be deposited using PVD or CVD and may have a thickness between about Peace The thickness between.

[0027] Then refer to Figure 4 . After depositing the seed layer 226, a patterned mask 228 is formed over the seed layer 226. The patterned mask 228 may include a photoresist layer or a bottom anti-reflective coating (BARC) layer. In an exemplary process, a material for the patterned mask 228 is deposited over the seed layer 226 using spin coating or flowable CVD (FCVD). Thereafter, photolithography techniques may be used to pattern the material into a patterned mask 228, which defines a pad opening 230. After forming the patterned mask 228, plating (e.g., electroplating or chemical plating) is performed to deposit copper (Cu), gold (Au), titanium tungsten (TiW), nickel (Ni), or platinum (Pt) over the seed layer 226 in the pad opening 230 exposed in the patterned mask 228. In one embodiment, aluminum-copper (Al-Cu) is deposited over the seed layer 226. After removing the patterned mask 228, a conductive layer is deposited in the pad opening 230 to form a sacrificial pad 232. Figure 5 In some embodiments not explicitly shown in the drawings, a solder component may be formed over the sacrificial pad 232. The solder component may include tin (Sn). After the sacrificial pad 232 is formed in the pad opening 230, the patterned mask 228 is selectively removed by ashing or selective etching, such as Figure 5 As shown in . Figure 6 After removing the patterned mask 228, the barrier layer 224 and the seed layer 226 not covered by the sacrificial pad 232 are selectively etched away, as shown in FIG. Figure 6 As shown in Figure 6As shown in FIG, sacrificial pad 232 is separated from first ESL 220, first dielectric layer 218, dielectric liner 216, and first redistribution component 210 by barrier layer 224 and seed layer 226. For ease of reference, sacrificial pad 232 and barrier layer 224 and seed layer 226 covered by sacrificial pad 232 may be collectively referred to as sacrificial pad 232.

[0028] The sacrificial pad 232 may be rectangular or square in shape in top view. Figure 6 , the sacrificial pad 232 has a second width W2 along the X direction or the Y direction. The second width W2 may be between about 40 μm and 60 μm. Because the sacrificial pad 232 needs to be large enough to accommodate the probing operation in the frame 108, it is substantially larger than the test contact opening 222. In some instances, it may be large enough to occupy the space and hinder the through-hole bonding. For example, the sacrificial pad 232 is at least suspended above the second redistribution component 212 and prevents the through-hole from bonding on the second redistribution component 212.

[0029] refer to Figure 1 and Figure 7 , method 100 includes block 108, where sacrificial pad 232 is probed. In block 108, probe 1000 is brought into contact with sacrificial pad 232. In some embodiments, probe 1000 is one of many probes in a probe card. By having physical and electrical contact between probe 1000 and the top surface of sacrificial pad 232, an electronic test system can implement automated integrated circuit testing. Probe 1000 may also be referred to as an electrical connector or needle. After probing in block 108, all tests that require the presence of sacrificial pad 232 have been implemented.

[0030] refer to Figure 1 and Figure 8, the method 100 includes a block 110, in which the sacrificial pad 232 is removed to expose the test contact opening 222. Because all tests requiring the presence of the sacrificial pad 232 have been performed at this time, the operations in block 110 are performed to remove the sacrificial pad 232 to release the space it once occupied. In block 110, each of the sacrificial pad 232, the seed layer 226, and the barrier layer 224 can be selectively removed by dry etching, wet etching, or a combination thereof. For example, the sacrificial pad 232 and the seed layer 226 can be selectively etched away using a wet etchant including nitric acid, ferric chloride, hydrogen chloride, sulfuric acid, potassium dichlorate. For another example, the barrier layer 224 can be selectively etched away using a wet etchant including ammonium hydroxide, hydrogen peroxide, hydrofluoric acid, or nitric acid. Because the chemical that etches the sacrificial pad 232 also etches the first redistribution component 210, a groove 240 can be formed. The groove 240 extends into the first redistribution component 210. That is, the bottom surface of the groove 240 is lower than the top surface of the first redistribution part 210. The position of the removed sacrificial pad 232 is marked using a dotted line.

[0031] refer to Figure 1 and Figures 9 and 10 , the method 100 includes block 112, where a dielectric layer is deposited over the WIP structure 200. Fig. 9 and Fig.10 As shown in FIG. 1 , block 112 deposits a second dielectric layer 242 over the first ESL 220 and the recess 240, a second ESL 244 over the second dielectric layer 242, and a third dielectric layer 246 over the second ESL 244. In some embodiments, the second dielectric layer 242 and the third dielectric layer 246 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The second dielectric layer 242 and the third dielectric layer 246 may be deposited using spin coating or flowable CVD (FCVD). The second ESL 244 may include silicon nitride. In some embodiments, the second dielectric layer 242 has a thickness between about 0.25 μm and about 1.5 μm. The second ESL 244 has a thickness between about 50 nm and about 100 nm. The second ESL 244 can be deposited using PVD or CVD. It should be noted that the lower portion of the second dielectric layer 242 extends through the first ESL 220 and the first dielectric layer 218 and extends into the groove 240. That is, the lowermost surface of the second dielectric layer 242 is lower than the top surface of the first redistribution component 210.

[0032] refer to Figure 1 and Figures 11 to 13The method 100 includes block 114, in which through-hole features 260, 262, and 264 are formed through the dielectric layer. The operations in block 114 may include: forming a first trench 250, a second trench 252, and a third trench 254 through the third dielectric layer 246 and the second ESL 244 ( Fig.11 ); extending the first trench 250, the second trench 252 and the third trench 254 through the second dielectric layer 242, the first ESL 220 and the first dielectric layer 218 to form a first dual inlay opening 2500, a second dual inlay opening 2520 and a third dual inlay opening 2540 ( Fig.12 ); and depositing a conductive material in the dual damascene openings 2500, 2520, and 2540 ( Fig.13). In an exemplary process, the first trench 250, the second trench 252, and the third trench 254 are first formed by a combination of photolithography and etching steps. Etching through the third dielectric layer 246 and the second ESL 244 can be accomplished with a dry etching process, which includes using an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), or a chlorine-containing gas (e.g., Cl2 and / or BCl3). Then, each of the first trench 250, the second trench 252, and the third trench 254 extends downward, having a through-hole opening through the second dielectric layer 242, the first ESL 220, and the first dielectric layer 218. Etching through the second dielectric layer 242, the first ESL 220, and the first dielectric layer 218 can be accomplished with a dry etching process, which includes using an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), or a chlorine-containing gas (e.g., Cl2 and / or BCl3). Each of the first dual damascene opening 2500, the second dual damascene opening 2520, and the third dual damascene opening 2540 includes a trench opening (such as the first trench 250, the second trench 252, and the third trench 254) and a via opening in fluid communication with the trench opening above. Then, block 114 continues to deposit a metal fill layer into the first dual damascene opening 2500, the second dual damascene opening 2520, and the third dual damascene opening 2540 to form a first via component 260, a second via component 262, and a third via component 264. In some embodiments, the metal fill layer may include copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), or aluminum (Al). In one embodiment, the metal fill layer may include copper (Cu). In some embodiments not explicitly shown in the figure, each of the first via component 260, the second via component 262, and the third via component 264 may include a barrier layer to be spaced apart from the first dielectric layer 218, the second dielectric layer 242, and the third dielectric layer 246, and the barrier layer includes oxygen. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess material and provide coplanar top surfaces for the third dielectric layer 246 , the first via feature 260 , the second via feature 262 , and the third via feature 264 .

[0033] refer to Figure 1 and Fig.14 The method 100 includes block 116 , where further processing is performed. Such further processing may include directly bonding the WIP structure 200 (as a die) to another die 290 . Fig.14An example of a WIP structure 200 flipped and directly bonded to another die 290 having a similar through-hole component arrangement is shown. In order to bond the WIP structure 200 and the die 290, the surfaces of the third dielectric layer 246, the first through-hole component 260, the second through-hole component 262, and the third through-hole component 264 are cleaned to remove organic and metal contaminants. For example, a sulfuric acid hydrogen peroxide mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or both thereof can be used to remove organic contaminants on the surfaces of the third dielectric layer 246, the first through-hole component 260, the second through-hole component 262, and the third through-hole component 264. A mixture of hydrochloric acid and hydrogen peroxide (SC2) can be used to remove metal contaminants. In addition to cleaning, the planarized surfaces of the third dielectric layer 246, the first through-hole component 260, the second through-hole component 262, and the third through-hole component 264 can be treated by argon plasma or nitrogen plasma to activate their surfaces. After the via features (and their corresponding via features in die 290) are vertically aligned, an anneal is performed to promote van der Waals bonding of the third dielectric layer 246s and surface activated bonding (SAB) of the first via feature 260, the second via feature 262, and the third via feature 264 (and their corresponding via features in die 290). In some examples, the anneal includes a temperature between about 200° C. and about 300° C.

[0034] In some optional embodiments, it is possible to apply Figure 1 The method 100 of the present invention can be used to form an alternative structure in which the WIP structure 200 is not bonded to another die by direct bonding. Fig.15 After removing the sacrificial pad 232, in block 112, a second dielectric layer 242 is deposited over the first ESL 220 and the recess 240. Fig.15 In the embodiment shown in FIG. 2 , the second ESL 244 and the third dielectric layer 246 are not deposited over the second dielectric layer 242. The composition and deposition of the second dielectric layer 242 have been described above and will not be repeated here for the sake of brevity. Fig.16, a first through hole opening 270 and a second through hole opening 272 are formed through the second dielectric layer 242, the first ESL 220, the first dielectric layer 218, and the dielectric liner 216 to expose the top surfaces of the first redistribution component 210 and the second redistribution component 212, respectively. The formation of the first through hole opening 270 and the second through hole opening 272 may include a combination of photolithography and etching steps. The etching through the second dielectric layer 242, the first ESL 220, the first dielectric layer 218, and the dielectric liner 216 may be completed using a dry etching process, which includes using an oxygen-containing gas (e.g., O2), a fluorine-containing gas (e.g., SF6 or NF3), or a chlorine-containing gas (e.g., Cl2 and / or BCl3). Then, in block 114, a first contact pad 280 and a second contact pad 282 are formed over the first through hole opening 270 and the second through hole opening 272, respectively. The formation of the first contact pad 280 and the second contact pad 282 can be similar to the formation of the sacrificial pad 232 described above. For example, a barrier layer 274 and a seed layer 276 are sequentially deposited over the first through-hole opening 270 and the second through-hole opening 272. After forming a patterned mask, the first contact pad 280 and the second contact pad 282 are deposited using electroplating or chemical plating. A solder component 284 is formed over each of the first contact pad 280 and the second contact pad 282. Fig.17 As shown in FIG. 1 , each of the first contact pad 280 and the second contact pad 282 includes a via portion extending through the second dielectric layer 242, the first ESL 220, the first dielectric layer 218, and the dielectric liner 216 to contact the first redistribution component 210 and the second redistribution component 212, respectively. For the avoidance of doubt, the barrier layer 274 may be similar to the barrier layer 224; the seed layer 276 may be similar to the seed layer 226; and the metal in the first contact pad 280 and the second contact pad 282 may be similar to the metal in the sacrificial pad 232. Further processing in block 116 may include placing Fig.17 The WIP structure 200 in FIG. 5 is flipped over and bonded to a circuit substrate 500 using the first contact pad 280 and the second contact pad 282. The circuit substrate 500 may be a silicon interposer.

[0035] Fig.19 The method 300 in the embodiment differs from the method 100 in at least that the method 100 completely removes the sacrificial pad 232 after the probe test is completed, while the method 300 uses a planarization process to remove a portion of the sacrificial pad. The method 300 shares several similar operations with the method 100. For the sake of brevity, the detailed description of these similar steps will be omitted.

[0036] refer to Fig.19 and Figure 2, the method 100 includes block 302, where a WIP structure 200 is received. The operations in block 302 are similar to those in block 102. For this reason, a detailed description of the operations in block 302 is omitted for brevity.

[0037] refer to Fig.19 and Figure 2 , method 300 includes block 304, in which a test contact opening 222 is formed to expose a portion of the first metal line 206 located in the top metal layer 203. The operations in block 304 are similar to those in block 104. Therefore, for the sake of brevity, a detailed description of the operations in block 304 is omitted.

[0038] refer to Fig.19 and Figures 3 to 6 , the method 300 includes block 306, in which a sacrificial pad 232 is formed over the test contact opening 222. The operations in block 306 are similar to those in block 106. Therefore, for the sake of brevity, a detailed description of the operations in block 306 is omitted.

[0039] refer to Fig.19 and Figure 7 , the method 300 includes block 308, in which the sacrificial pad 232 is detected. The operations in block 308 are similar to those in block 108. Therefore, for the sake of brevity, a detailed description of the operations in block 308 is omitted.

[0040] refer to Fig.19 and Fig. 20 , method 300 includes block 310, wherein sacrificial pad 232 is partially removed by planarization process 221. Instead of etching away sacrificial pad 232, block 310 performs planarization process 221, such as chemical mechanical polishing (CMP) process, on WIP structure 200 until the top surface of remaining portion 2320 of sacrificial pad 232 is coplanar with first dielectric layer 218. Remaining portion 2320 includes all layers in sacrificial pad 232. Fig.21 As shown in FIG. 2 , the remaining portion 2320 includes the barrier layer 224, the seed layer 226, and the metal filler 232. Fig. 20 Although not explicitly shown, a planarization dielectric layer may be deposited over WIP structure 200 (including over sacrificial pad 232) before the planarization process is performed. At the end of planarization process 221, the planarization dielectric layer is completely removed. In some examples, the planarization dielectric layer may include silicon oxide and may be deposited using CVD. Fig. 20 As shown in FIG. , the remaining portion 2320 may have Figure 2 The dimensions of the test contact opening 222 shown in . For example, the remaining portion 2320 may have a width similar to the first width W1 of the test contact opening 222 .

[0041] refer to Fig.19 and Fig.21 , method 300 includes block 312, where a dielectric layer is deposited over WIP structure 200. The operations in block 312 are similar to those in block 112. Therefore, for the sake of brevity, a detailed description of the operations in block 312 is omitted. Fig.21 In some embodiments shown in , the second dielectric layer 242 is deposited on top of the first dielectric layer 218 and the remaining portion 2320 .

[0042] refer to Fig.19 and Figure 22 to Figure 23 , the method 300 includes block 314, in which via features 260, 262, and 264 are formed through the dielectric layer. The operations in block 314 are similar to those in block 114. Therefore, for the sake of brevity, a detailed description of the operations in block 314 is omitted.

[0043] refer to Fig.19 and Fig.24 , method 300 includes block 316, where further processing is performed. The operations in block 316 are similar to those in block 116. Therefore, for the sake of brevity, a detailed description of the operations in block 316 is omitted. Fig.24 As shown in , the remaining portion 2320 remains in the final structure. In some embodiments, the remaining portion 2320 in the lower die can be vertically aligned with the corresponding remaining portion in the upper die.

[0044] Fig.25 The method 400 in the present invention differs from the method 100 in at least that the method 100 completely removes the sacrificial pad 232 after the probe test is completed, while the method 400 patterns the sacrificial pad. The method 400 shares several similar operations with the method 100. For the sake of brevity, the detailed description of these similar steps will be omitted.

[0045] refer to Fig.25 and Figure 2 , the method 400 includes block 402, where a WIP structure 200 is received. The operations in block 402 are similar to those in block 102. For this reason, a detailed description of the operations in block 402 is omitted for brevity.

[0046] refer to Fig.25 and Figure 2 , method 400 includes block 404, in which a test contact opening 222 is formed to expose a portion of the first metal line 206 located in the top metal layer 203. The operations in block 404 are similar to those in block 104. Therefore, for the sake of brevity, a detailed description of the operations in block 404 is omitted.

[0047] refer to Fig.25 and Figures 3 to 6, the method 400 includes block 406, in which a sacrificial pad 232 is formed over the test contact opening 222. The operations in block 406 are similar to those in block 106. Therefore, for the sake of brevity, a detailed description of the operations in block 406 is omitted.

[0048] refer to Fig.25 and Figure 7 , the method 400 includes block 408, where the sacrificial pad 232 is detected. The operations in block 408 are similar to those in block 108. Therefore, for the sake of brevity, a detailed description of the operations in block 408 is omitted.

[0049] refer to Fig.25 and Fig.26 , method 400 includes frame 410, in which the sacrificial pad 232 is patterned. Instead of completely removing the sacrificial pad 232 in method 100 or planarizing the sacrificial pad 232 in method 300, method 400 reduces the footprint of the sacrificial pad 232 by patterning the sacrificial pad 232. In some embodiments, a photolithography and etching process is performed to remove the portion of the sacrificial pad 232 that is suspended above the second redistribution component 212. For example, a patterned etching mask can be formed above the sacrificial pad 232 by a photolithography step. Then, the sacrificial pad 232 is etched using the patterned etching mask as an etching mask. Etching can be performed using a dry etching process, a wet etching process, or a combination thereof. An exemplary dry etching process may include using hydrogen plasma and nitrogen (N2). As Fig.26 As shown in FIG. 4 , the patterning in block 410 produces a truncated pad 2322 . The truncated pad 2322 has a third width W3 , which is greater than the first width W1 of the test contact opening 222 , but less than the second width W2 of the sacrificial pad 232 . Fig.26 In some embodiments shown in , the shortened pad 2322 has a small size such that it no longer overhangs the second redistribution feature 212 .

[0050] refer to Fig.25 and Fig. 27 , method 400 includes block 412, where a dielectric layer is deposited over WIP structure 200. The operations in block 412 are similar to those in block 112. Therefore, for the sake of brevity, a detailed description of the operations in block 412 is omitted. Fig. 27 In some embodiments shown in , the second dielectric layer 242 is disposed around the shortened pad 2322. The second dielectric layer 242 is in direct contact with the sidewalls of the shortened pad 2322. The second ESL 244 may be deposited on the shortened pad 2322 and the top surface of the second dielectric layer 242.

[0051] refer to Fig.25 and Figure 28 to Figure 29, method 400 includes block 414, in which via features 260, 262, and 264 are formed through the dielectric layer. The operations in block 414 are similar to those in block 114. Therefore, for the sake of brevity, a detailed description of the operations in block 414 is omitted.

[0052] refer to Fig.25 and Fig.30 , method 400 includes block 416, where further processing is performed. The operations in block 416 are similar to those in block 116. Therefore, for the sake of brevity, a detailed description of the operations in block 416 is omitted. Fig.30 As shown in , the truncated pads 2322 remain in the final structure. In some embodiments, the truncated pads 2322 in the lower die can be vertically aligned with the corresponding truncated pads in the upper die.

[0053] One aspect of the disclosed embodiments relates to a redistribution structure. The redistribution structure includes: a metal line; a first dielectric layer disposed above the metal line; a first etch stop layer (ESL) disposed above the first dielectric layer; a second dielectric layer disposed above the first ESL; and a conductive via extending through the second dielectric layer, the first ESL, and the first dielectric layer to contact the metal line. A lower portion of the second dielectric layer extends downward through the first ESL and the first dielectric layer, and partially extends into the metal line.

[0054] In some embodiments, the redistribution structure further includes: a dielectric liner sandwiched between the first dielectric layer and the surface of the metal line. In some embodiments, the lower portion of the second dielectric layer also extends through the dielectric liner. In some instances, the dielectric liner includes silicon nitride, and the dielectric liner includes a thickness between about 100 nm and about 200 nm. In some embodiments, the dielectric liner is disposed above the sidewall of the metal line and in contact with the sidewall of the metal line. In some embodiments, the lower portion of the second dielectric layer is in direct contact with the sidewalls of the first ESL, the first dielectric layer, and the dielectric liner. In some embodiments, the metal line is disposed above the passivation layer, the passivation layer includes silicon nitride, and the passivation layer includes a thickness between about 1 μm and about 2 μm. In some embodiments, the lower portion includes a width between about 10 μm and about 20 μm. In some instances, the metal line includes copper (Cu).

[0055] Another aspect of the disclosed embodiments relates to a contact structure. The contact structure includes: a passivation layer; a metal line disposed above the passivation layer; a first dielectric layer disposed above the metal line; a metal component disposed in the first dielectric layer and in contact with a top surface of the metal line; a second dielectric layer disposed above the first dielectric layer and the top surface of the metal component; and a conductive via extending through the second dielectric layer and the first dielectric layer to contact the metal line. The top surfaces of the first dielectric layer and the metal component are coplanar.

[0056] In some embodiments, the metal component includes: a barrier layer, directly contacting the first dielectric layer and the metal line; a seed layer, disposed on the barrier layer; and a metal fill layer, located above the seed layer. In some embodiments, the second dielectric layer is in contact with the barrier layer, the seed layer, and the metal fill layer. In some embodiments, the barrier layer includes titanium (Ti), tantalum (Ta), or tantalum nitride (TaN), and the seed layer and the metal fill layer include copper (Cu). In some embodiments, the metal component includes a width between about 10 μm and about 20 μm. In some embodiments, the contact structure also includes: a dielectric liner, sandwiched between the first dielectric layer and the surface of the metal line. In some instances, the metal component extends through the dielectric liner to contact the top surface of the metal line.

[0057] Another aspect of the disclosed embodiments relates to a method. The method includes: depositing a first dielectric layer over a metal line; depositing a first etch stop layer (ESL) over the first dielectric layer; forming a test contact opening through the first dielectric layer and the first ESL to expose a portion of the metal line; forming a test pad over the test contact opening; performing a test by contacting the test pad with a probe; after performing the test, removing the test pad to expose the test contact opening; and after removing the test pad, depositing a second dielectric layer over the first ESL and the test contact opening.

[0058] In some embodiments, forming the test pad includes: depositing a barrier layer over the test contact opening and the first ESL; depositing a seed layer over the barrier layer; and depositing a metal fill layer over the seed layer using electroplating. In some embodiments, removing the test pad extends the test contact opening into the metal line. In some embodiments, after depositing the second dielectric layer, a portion of the second dielectric layer extends below the top surface of the metal line.

[0059] Some embodiments of the present application provide a redistribution structure, including: a metal line; a first dielectric layer, disposed above the metal line; a first etch stop layer (ESL), disposed above the first dielectric layer; a second dielectric layer, disposed above the first etch stop layer; and a conductive via, extending through the second dielectric layer, the first etch stop layer and the first dielectric layer to contact the metal line, wherein a lower portion of the second dielectric layer extends downward through the first etch stop layer and the first dielectric layer, and partially extends into the metal line.

[0060] In some embodiments, the redistribution structure further comprises: a dielectric liner sandwiched between the first dielectric layer and the surface of the metal line. In some embodiments, the lower portion of the second dielectric layer also extends through the dielectric liner. In some embodiments, wherein the dielectric liner comprises silicon nitride, wherein the dielectric liner comprises a thickness between about 100 nm and about 200 nm. In some embodiments, the dielectric liner is disposed above the sidewall of the metal line and in contact with the sidewall of the metal line. In some embodiments, the lower portion of the second dielectric layer is in direct contact with the sidewalls of the first etch stop layer, the first dielectric layer, and the dielectric liner. In some embodiments, wherein the metal line is disposed above a passivation layer, wherein the passivation layer comprises silicon nitride, wherein the passivation layer comprises a thickness between about 1 μm and about 2 μm. In some embodiments, the lower portion comprises a width between about 10 μm and about 20 μm. In some embodiments, the metal line comprises copper (Cu).

[0061] Other embodiments of the present application provide a contact structure, including: a passivation layer; a metal line disposed above the passivation layer; a first dielectric layer disposed above the metal line; a metal component disposed in the first dielectric layer and in contact with a top surface of the metal line; a second dielectric layer disposed above the first dielectric layer and the top surface of the metal component; and a conductive via extending through the second dielectric layer and the first dielectric layer to contact the metal line, wherein the top surfaces of the first dielectric layer and the metal component are coplanar.

[0062] In some embodiments, the metal component includes: a barrier layer in direct contact with the first dielectric layer and the metal line; a seed layer disposed on the barrier layer; and a metal fill layer located above the seed layer. In some embodiments, the second dielectric layer is in contact with the barrier layer, the seed layer, and the metal fill layer. In some embodiments, wherein the barrier layer includes titanium (Ti), tantalum (Ta), or tantalum nitride (TaN), wherein the seed layer and the metal fill layer include copper (Cu). In some embodiments, the metal component includes a width between about 10 μm and about 20 μm. In some embodiments, the contact structure further includes: a dielectric liner sandwiched between the first dielectric layer and the surface of the metal line. In some embodiments, the metal component extends through the dielectric liner to contact the top surface of the metal line.

[0063] Still other embodiments of the present application provide a method for forming a contact structure, comprising: depositing a first dielectric layer above a metal line; depositing a first etch stop layer (ESL) above the first dielectric layer; forming a test contact opening through the first dielectric layer and the first etch stop layer to expose a portion of the metal line; forming a test pad above the test contact opening; performing a test by contacting the test pad with a probe; after performing the test, removing the test pad to expose the test contact opening; and after removing the test pad, depositing a second dielectric layer above the first etch stop layer and the test contact opening.

[0064] In some embodiments, forming the test pad includes: depositing a barrier layer over the test contact opening and the first etch stop layer; depositing a seed layer over the barrier layer; and depositing a metal fill layer over the seed layer using electroplating. In some embodiments, removing the test pad extends the test contact opening into the metal line. In some embodiments, after depositing the second dielectric layer, a portion of the second dielectric layer extends below a top surface of the metal line.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A redistribution structure, comprising: Metal wire; A first dielectric layer disposed above the metal line; a first etch stop layer (ESL) disposed over the first dielectric layer; a second dielectric layer disposed above the first etch stop layer; as well as a conductive via extending through the second dielectric layer, the first etch stop layer, and the first dielectric layer to contact the metal line, The lower portion of the second dielectric layer extends downward through the first etch stop layer and the first dielectric layer, and partially extends into the metal line.

2. The redistribution structure according to claim 1, further comprising: A dielectric liner is sandwiched between the first dielectric layer and the surface of the metal line.

3. The redistribution structure according to claim 2, wherein: The lower portion of the second dielectric layer also extends through the dielectric liner.

4. The redistribution structure according to claim 2, in, The dielectric liner comprises silicon nitride, Wherein the dielectric liner comprises a thickness between about 100 nm and about 200 nm.

5. The redistribution structure according to claim 2, wherein: The dielectric liner is disposed over and in contact with the sidewalls of the metal line.

6. The redistribution structure according to claim 2, wherein: The lower portion of the second dielectric layer is in direct contact with the first etch stop layer, the first dielectric layer, and sidewalls of the dielectric liner.

7. The redistribution structure according to claim 1, in, The metal line is disposed above the passivation layer, Wherein, the passivation layer comprises silicon nitride, Wherein, the passivation layer comprises a thickness between about 1 μm and about 2 μm.

8. The redistribution structure according to claim 1, wherein: The lower portion includes a width between about 10 μm and about 20 μm.

9. A contact structure comprising: Passivation layer; A metal line disposed above the passivation layer; A first dielectric layer disposed above the metal line; a metal component disposed in the first dielectric layer and contacting a top surface of the metal line; a second dielectric layer disposed above the first dielectric layer and a top surface of the metal component; as well as a conductive via extending through the second dielectric layer and the first dielectric layer to contact the metal line, Wherein, the first dielectric layer and the top surface of the metal component are coplanar.

10. A method of forming a contact structure, comprising: depositing a first dielectric layer over the metal line; depositing a first etch stop layer (ESL) over the first dielectric layer; forming a test contact opening through the first dielectric layer and the first etch stop layer to expose a portion of the metal line; forming a test pad above the test contact opening; Performing a test by contacting a probe with the test pad; After performing the test, removing the test pad to expose the test contact opening; as well as After removing the test pad, a second dielectric layer is deposited over the first etch stop layer and the test contact opening.

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