Electronic rectifier circuit for adaptive gate voltage regulation of synchronous rectifier field effect transistors

Abstract

An electronic rectifier circuit for adaptive gate voltage regulation of a synchronous rectifier field effect transistor, where the electronic rectifier circuit is configured to clamp a drain-source voltage of the SR FET to a first regulated voltage when the SR FET is turned on less than a threshold time in a current switching period, wherein the electronic rectifier circuit is configured to clamp the Vds of the SR FET to a second regulated voltage when the SR FET is turned on greater than the threshold time in the current switching period, where the threshold time is configured as part of the time when the SR FET is turned on in one or more previous switching periods, and where Vreg2 is less than Vreg1.

Description

Technical Field

[0001] The present disclosure relates to an electronic rectifier circuit for adaptive gate voltage (Vg) regulation of a synchronous rectifier field effect transistor (SR FET), a fast charging power supply including such an electronic rectifier circuit, and a method for adaptive Vg regulation of a SR FET. Background Art

[0002] In power electronics, rectifiers can be used to convert alternating current (AC) to direct current (DC). Synchronous rectification is a technique used to improve the efficiency of rectifiers. In SR circuits, power MOSFETs (metal oxide semiconductor field effect transistors), or FETs for short, can be used as switches in place of traditional diodes. SR FETs can typically be controlled on the secondary side of the transformer by a gate signal, such as a drain-source voltage (Vds), that is synchronized with the input AC waveform. In the example, when the input AC voltage is negative, the SR FET turns on, allowing current to flow. When the AC voltage becomes positive, the SR FET turns off to prevent reverse current from flowing. By using SR FETs, the voltage drop across the rectifier can be significantly reduced compared to diodes, thereby improving efficiency.

[0003] A primary side (Pri) FET can be used as a switch in series with the primary winding of the transformer. When the Pri FET is turned on, it allows current to flow through the transformer, and when it is turned off, the current is interrupted.

[0004] Continuous conduction mode (CCM) is an operating mode of a switching power converter. CCM is commonly used in DC-DC converters, such as buck, boost, and buck-boost converters. In CCM, the inductor in the converter is typically kept on continuously throughout the switching cycle. Discontinuous conduction mode (DCM) is another operating mode of a switching power converter. Similar to CCM, DCM is commonly used in DC-DC converters, such as buck, boost, and buck-boost converters. In DCM, the inductor current typically drops to zero during a portion of the switching cycle.

[0005] CCM flyback is the operating mode of a flyback converter, which is an isolated DC-DC converter. In CCM flyback operation, the transformer's primary magnetizing current remains continuous throughout the switching cycle. A flyback converter typically includes a transformer, a power switch (usually a MOSFET), a diode, an input capacitor, and an output capacitor. It operates by storing energy in the transformer during the on-time of the power switch and releasing it to the output during the off-time. In CCM flyback operation, the power switch can be turned on and energy from the input source can be stored in the primary winding of the transformer, generating a magnetic field. Energy transfer occurs when the power switch is turned off. The energy stored in the magnetic field induces a voltage across the secondary winding of the transformer, which is rectified by the diode and transferred to the output capacitor and the load. CCM flyback converters are commonly used in a variety of applications, including low-power offline power supplies, LED drivers, battery chargers, and isolated power supplies.

[0006] Figure 1 A high power fast charging power supply 100 with a flyback circuit architecture is shown, which includes a transformer 102, a PriFET 104, an SR FET 106, and a driver circuit 108. For each of the FETs 104, 106, the gate (G), source (S), and drain (D) are identified. At the SR FET 106, the DS current (Ids) and Vg are also indicated. This fast charging power supply can operate in CCM under heavy loads. A conventional SR controller can detect the zero-crossing Vds of the SR FET when the Pri FET is turned on, which forces the SR FET to turn off. Due to voltage sampling delays and drive voltage drop delays, the SR FET may not turn off in time. Then, the Pri FET and the SR FET may be turned on at the same time, which may result in large cross-losses, low efficiency, high stress on the switch, and device damage.

[0007] SR controllers that employ a fixed Vg regulation mode with a one-step gate regulation are known. In this mode, when the Vds voltage reaches the clamping value, the Vg amplitude can be reduced to regulate the Vds voltage at the clamping value, thereby accelerating the turn-off speed of the SR FET. However, the one-step regulation circuit is significantly dependent on the choice of the drain-source on-resistance (Rdson) of the MOSFET, and Vg is difficult to regulate in deep CCM because the Vds voltage is too low to trigger the Vds clamping level before the Pri FET turn-on signal arrives. This may result in Vg regulation failure or insufficient regulation, and therefore a fast turn-off cannot be achieved.

[0008] Figure 2A graph 200 of current, voltage and time delay is shown. Lines of SR current 202, SR voltage 204 and Vg are shown. In the Y-axis direction, voltage levels are indicated for the clamping level at the gate voltage threshold (Vg_th) and the first regulated voltage (Vreg1). The X-axis represents time. In the X-axis direction, a turn-on delay 210 and a turn-off delay 212 are indicated. Vds can be clamped at a fixed level and Vg can be regulated under mild CCM conditions. In this case, if the clamping level is high and when a high Rdson FET is used, it may be difficult or even impossible to regulate the Vg of the switch low enough before the SR FET is turned off, which may result in a long turn-off delay and high switch stress when the switch turn-off signal arrives. If the clamping level is low and when a low Rdson FET is used, the turn-off delay time 212 may be relatively short because Vg is deeply regulated, but the conduction losses may be much higher and may result in low efficiency.

[0009] During deep CCM or when using high Rdson FETs, it may be difficult or even impossible to regulate Vg, resulting in relatively long turn-off delay times. Figure 3 A graph 300 of current, voltage and time delay for such a scenario is shown. Lines of SR current 302, SR voltage 304 and Vg are shown. In the Y-axis direction, voltage levels are indicated for Vg_th and Vreg1. The X-axis represents time. In the X-axis direction, a time turn-on delay 310 and a time turn-off delay 312 are indicated.

[0010] In the above CCM flyback gate regulation scenario, it is difficult or even impossible to achieve high efficiency and low switch stress at the same time. On the other hand, with the release of fast charger protocols such as "Power Delivery (PD) 3.1", fast chargers and adapters for smartphones, tablets, laptops, power tools and other fast charging devices have higher and higher power requirements, and the power density of products is also getting higher and higher. Such fast charger power supplies are required to be highly efficient. For traditional diode rectifiers, it is difficult or impossible to meet the requirements of high current and high power density while the application of SR is becoming more and more popular. Summary of the invention

[0011] The following describes an overview of aspects of some examples disclosed herein. It should be understood that these aspects are presented only to provide the reader with a brief overview of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass various aspects and / or combinations of aspects that may not be described.

[0012] The present disclosure is directed to overcoming the disadvantages identified in the background section. In particular, the present disclosure is directed to achieving a turn-off delay time with adaptive Vg regulation, wherein the turn-off delay time is much shorter than current solutions. Advantageously, this can result in switching devices such as SR FETs having less stress, less cross-conduction losses, and better reliability.

[0013] According to one aspect of the present disclosure, an electronic rectifier circuit for adaptive Vg regulation of an SR FET is provided. The electronic rectifier circuit may be configured to clamp the Vds of the SR FET to Vreg1 when the SR FET is turned on for less than a threshold time in the current switching cycle. The electronic rectifier circuit may be configured to clamp the Vds of the SR FET to a second regulation voltage (Vreg2) when the SR FET is turned on for more than a threshold time in the current switching cycle. The threshold time may be configured as a portion of the time that the SR FET was turned on in one or more previous switching cycles. Vreg2 may be less than Vreg1.

[0014] In an embodiment, the electronic rectifier circuit may include a first Vg detection component configured to measure the amount of time that the SR FET is turned on. The first Vg detection component may also be configured to store a first signal representing the amount of time in a sample holder. The electronic rectifier circuit may also include a second Vg detection component configured to measure another amount of time that the SR FET is turned on to obtain a second signal. The electronic rectifier circuit may also include a comparator having a first signal and a second signal obtained from the sample holder as inputs. The comparator may have a selection signal as an output. The electronic rectifier circuit may also include a multiplexer configured to output Vreg1 or Vreg2 according to the selection signal.

[0015] In an embodiment, the first Vg detection component may include a first capacitor. The second Vg detection component may include a second capacitor. The first capacitor and the second capacitor may be sized at a ratio that defines a threshold time.

[0016] In an embodiment, the second capacitor may be sized at 90% of the value of the first capacitor.

[0017] According to one aspect of the present disclosure, a fast charging power supply is proposed. The fast charging power supply may include a transformer. The fast charging power supply may also include a primary side field effect transistor (Pri FET). The fast charging power supply may also include an SRFET. The fast charging power supply may also include an electronic rectifier circuit having one or more of the above features.

[0018] According to one aspect of the present disclosure, a method for adaptive Vg regulation of an SR FET is provided. The method may include turning on the SR FET by setting the Vg of the SR FET to high. The method may also include starting a timer for counting the on-time of the SR FET in the current switching cycle. The method may also include determining whether the on-time of the SR FET exceeds a portion of the previous on-time of the SR FET in one or more previous switching cycles. The method may also include clamping Vds to Vreg1 if the on-time does not exceed a portion of the previous on-time. The method may also include clamping Vds to Vreg2 if the on-time exceeds a portion of the previous on-time.

[0019] In an embodiment, the method may further include turning on the SR FET after detecting that the Vds of the SR FET is below a turn-on threshold (Von_th).

[0020] In an embodiment, the method may further include determining whether the Vds of the SR FET exceeds a turn-off threshold (Voff_th) after clamping Vds to Vreg2. The method may further include turning off the SR FET by setting Vg low if the Vds of the SR FET exceeds Voff_th.

[0021] In an embodiment, the method may further include storing the on-time of the SR FET obtained by the timer after the SR FET has been turned off to be used as the previous on-time in the next switching cycle. The timer may be stopped before storing the on-time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, wherein corresponding reference numerals indicate corresponding parts, and wherein:

[0023] Figure 1 A high power fast charging power supply with a flyback circuit architecture is shown;

[0024] Figure 2 Graphs showing current, voltage and time delay of a prior art fast charge power supply during mild CCM;

[0025] Figure 3 Graphs showing current, voltage and time delay of a prior art fast charge power supply during deep CCM or when using a high Rdson FET;

[0026] Figure 4 An electronic rectifier circuit for adaptive gate Vg regulation of SR FETs according to an exemplary embodiment of the present disclosure is shown;

[0027] Figure 5 Graphs showing current, voltage, and time delay of an electronic rectifier circuit for adaptive gate Vg regulation of an SR FET in DCM or mild CCM mode according to an exemplary embodiment of the present disclosure;

[0028] Figure 6 Graphs showing current, voltage, and time delay of an electronic rectifier circuit for adaptive gate Vg regulation of an SR FET in deep CCM mode according to an exemplary embodiment of the present disclosure;

[0029] Figure 7 Graphs showing current, voltage, and time delay of an electronic rectifier circuit for adaptive gate Vg regulation of an SR FET in a resonant mode converter according to an exemplary embodiment of the present disclosure; and

[0030] Figure 8 A flow chart of a method for adaptive gate Vg adjustment of a SR FET according to an exemplary embodiment of the present disclosure is shown.

[0031] The drawings are intended for illustration purposes only and are not intended to limit the scope of protection defined by the claims. DETAILED DESCRIPTION

[0032] It will be readily appreciated that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of the various embodiments, as shown in the drawings, is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0033] The described embodiments should be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes that fall within the meaning and range of equivalents of the claims will be included within their scope.

[0034] References throughout this specification to features, advantages, or similar language do not mean that all features and advantages that can be achieved using the present disclosure should be or are in any single example of the present disclosure. Instead, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present disclosure. Therefore, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same example.

[0035] In addition, the described features, advantages and characteristics of the present disclosure can be combined in any suitable manner in one or more embodiments. According to the description herein, those skilled in the relevant art will recognize that the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present disclosure may be recognized in certain embodiments. References throughout this specification to "one embodiment", "embodiment" or similar language mean that the specific features, structures or characteristics described in conjunction with the indicated embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment", "in an embodiment" and similar language throughout this specification may, but not necessarily all, refer to the same embodiment.

[0036] Figure 4 FIG. 4 is a block diagram of a circuit 400 for adaptive Vg regulation according to an exemplary embodiment. The circuit 400 may be replaced by Figure 1 The circuit 400 enables a pre-regulated gate voltage (Vpre_gate) of a gate 402 to be adaptively regulated to a regulated gate voltage (Vreg_gate). Vreg_gate may be provided to the SR FET, depicted by box 404.

[0037] The circuit 400 may include a first Vg detection component 410 for detecting and storing the on-duration of the SR in one or more previous switching cycles. For example, a signal representing the on-duration of the SR for two previous switching cycles may be measured and stored in a sample holder 430. The circuit 400 may also include a second Vg detection component 420 for detecting the on-duration of the SR in the current switching cycle.

[0038] The selector 440 can determine whether the conduction time (i.e., on-time) of the SR FET in the current switching cycle is within a predetermined portion of the on-duration of the previous switching cycle. For example, if the on-duration of the current switching cycle is within 90% of the on-duration of the previous switching cycle, the size of the second capacitor 422 can be set to 90% of the first capacitor 412, such as Figure 4 In the example of FIG. 4 , 0.9C and C are depicted for capacitors 422 and 412 , respectively.

[0039] The comparator 442 can compare the on-time of the current switching cycle with the on-time of the previous switching cycle, and the result can be output as a selection signal to the multiplexer 444 for selecting Vreg2 446 or Vreg1 448 according to whether the on-time of the SR FET in the current switching cycle is lower or higher than the threshold time.

[0040] The selected regulation voltage level may then be provided to an operational transconductance amplifier (OTA) 450 for use in generating Vreg_gate. Thus, adaptive Vg regulation may be achieved by adapting Vreg_gate using Vreg2 and Vreg1.

[0041] For example, if the conduction time (i.e., on-time) of the SR FET in the current switching cycle is within a threshold time, e.g., within 90% of the on-time of the two previous cycles, the selector 440 may select channel 0 of the multiplexer 444 for the regulation voltage of Vreg1 448. Until the threshold time, the regulation voltage of the OTA 450 is Vreg1 448, which may be input to the non-inverting input terminal of the OTA 450. The Vds sampled voltage may be input to the inverting input terminal of the OTA 450 to regulate the gate driver voltage Vg after being amplified by the OTA 450. The lower the Vg, the higher the Rdson of the SR FET, which results in a lower Vds voltage (current flows from the source (S) pin of the SR FET to the drain (D) pin). If the Vds voltage is too low, the OTA 450 increases Vg to increase the Vds voltage, thereby keeping it equal to the regulation voltage.

[0042] For example, if the conduction time (i.e., on-time) of the SR FET in the current switching cycle reaches a threshold time, e.g., 90% of the on-time of the two previous cycles, the selector 440 may select channel 1 of the multiplexer 444 for the regulated voltage of Vreg2 446. Vds may then be stabilized at Vreg2 by further reducing Vg. When the Pri FETon signal arrives, Vg may drop sharply and quickly reach the on-threshold voltage of the SR FET to quickly turn off the SR FET.

[0043] Figure 5 A first example graph 500 of current, voltage, and time delay of the circuit 400 in DCM or mild CCM mode is shown. Lines of SR current 502, SR voltage 504, and Vg are shown. In the Y-axis direction, voltage levels are indicated for Vg_th, Von_th, Voff_th, Vreg2, and Vreg1. The X-axis represents time. In the X-axis direction, a turn-on time delay 510, a turn-off time delay 512, and 90% 506 of the turn-on time (Ton) are indicated.

[0044] In mild CCM mode, the inductor current in the converter typically remains continuously on during most of the switching cycle, but for short durations, it can drop to zero or near zero. As can be seen from the graph 500, the Vds voltage (i.e., the SR voltage 504) can be increased to a first regulation level Vreg1 and clamped to Vreg1 before reaching 90% (506) of the last Ton cycle. When the Vds voltage is regulated at Vreg1, the gate driver voltage can be reduced. When reaching 90% (506) of the on-time duration Ton, the Vds voltage (i.e., the SR voltage 504) can be pulled down from the Vref2 clamping level to a second regulation level Vreg2 and clamped to Vreg2. Since Vreg2 is typically much lower than Vreg1, Vg can drop at a faster slope and approach the turn-off threshold of the SR FET. As a result, when the turn-on signal of the Pri FET arrives, the SR FET can be quickly turned off in a short time 512.

[0045] Figure 6 A second example graph 600 of current, voltage, and time delay of the circuit 400 in deep CCM mode is shown. Lines of SR current 602, SR voltage 604, and Vg are shown. In the Y-axis direction, voltage levels are indicated for Vg_th, Vreg2, and Vreg1. The X-axis represents time. In the X-axis direction, a time turn-on delay 610 and a time turn-off delay 612 are indicated.

[0046] In deep CCM mode, the inductor current in the converter usually remains continuously turned on throughout the cycle, and the current variation amplitude is usually relatively small compared to the peak current. As can be seen from the curve graph 600, the Vds voltage may not trigger the second clamping level at the first regulation voltage Vreg1. When the time reaches 90% of the conduction duration, the circuit can directly pull the clamping level to the first clamping level at the second regulation voltage Vreg2. At this time, Vg can drop at a fast slope and approach the turn-off threshold of the SR FET. As a result, when the turn-on signal of the Pri FET arrives, the SR FET can be quickly turned off within a short time, that is, the short turn-off delay 612.

[0047] Figure 7 A third example graph 700 of current, voltage, and time delay for the circuit 400 in a resonant mode converter is shown. Lines of SR current 702, SR voltage 704, and Vg are shown. In the Y-axis direction, voltage levels are indicated for Vg_th, Vreg2, and Vreg1. The X-axis represents time. In the X-axis direction, a time turn-on delay 710 and a time turn-off delay 712 are indicated.

[0048] In the resonant mode, also known as resonant switching or resonant operation, the power converter can utilize resonant components (inductors and capacitors) to achieve efficient power conversion. As can be seen in the graph 700, the Vds of the same SR FET can pass through the first and second clamping phases under the control of the first regulated voltage Vreg1 and the second regulated voltage Vreg2, respectively. When the conduction signal of the Pri FET arrives, the SR FET can be quickly turned off within a short time, i.e., the Toff delay 712.

[0049] Compare Figure 2-3 with Figure 5-7 it is clear that the circuit 400 advantageously achieves much shorter Toff delays 512, 612, 712 with adaptive Vg regulation. As a result, the switching device such as the SR FET will experience less stress, less cross-conduction loss, and have better reliability.

[0050] Figure 8 An example control flow 800 of the SR FET showing an exemplary embodiment of the present disclosure is shown. The control flow 800 starts at step 802. The reference numeral "A" represents a continuous loop, i.e., the flow ends and starts with "A".

[0051] In step 804, the SR control integrated circuit (IC) can detect Vds.

[0052] In step 806, it can be determined whether the detected Vds is less than the conduction level: Vds < Von_th? If this is not the case, the control flow 800 can return to step 804. Otherwise, if this is the case, the control flow 800 can continue at step 808.

[0053] In step 808, Vg can be set to "high" to turn on the SR FET, and in step 810, a timer for measuring the on-time of the SR FET can be started.

[0054] In step 812, it can be determined whether the current on-duration of the SR FET exceeds a percentage of the on-duration of one or more previous switching cycles of the SR FET. So far, the on-duration of one or more previous switching cycles is obtained, for example, from the sample and hold circuit 420. For example, it can be determined: Ton_present_cycle > 90% of Ton_previous_two_cycles? If this is not the case, the control flow 800 can continue at step 814. Otherwise, if this is the case, the control flow 800 can continue at step 820.

[0055] In step 814 , it may be determined whether Vds exceeds the first regulated voltage Vreg1 : Vds>Vreg1 ? If this is the case, control flow 800 may continue at step 816 . Otherwise, if this is not the case, control flow 800 may return to step 812 .

[0056] In step 816 , Vg may be adjusted to hold (ie, clamp) Vds at the first regulated voltage Vreg1 : Vds=Vreg1 . Control flow 800 may then return to step 812 .

[0057] In step 820 , Vg may be adjusted to hold (ie, clamp) Vds at a second regulated voltage Vreg2 : Vds=Vreg2 .

[0058] In step 822 , it may be determined whether Vds exceeds the off level: Vds>Voff_th? If this is not the case, control flow 800 may return to step 820 . Otherwise, if this is the case, control flow 800 may continue at step 824 .

[0059] In step 824 , Vg may be set to “low” to turn off the SR FET, and in step 826 , the total on-time (ie, Ton) of the current switching cycle may be stored, for example, in the sample holder 420 .

[0060] In step 828 , the timer for measuring the on-time of the SR FET may be stopped, eg, reset to zero, and the control flow 800 may be run again for the next switching cycle, as indicated by reference numeral “A”.

Claims

1. An electronic rectifier circuit (400) for adaptive gate voltage Vg regulation of a synchronous rectifier field effect transistor (SR FET) (106), wherein the electronic rectifier circuit (400) is configured to clamp the drain-source voltage Vds of the SR FET (106) to a first regulation voltage Vreg1 (448) when the SR FET (106) is turned on for less than a threshold time in a current switching cycle, wherein the electronic rectifier circuit (400) is configured to clamp the Vds of the SR FET (106) to a second regulation voltage Vreg2 (446) when the SR FET (106) is turned on for more than the threshold time in the current switching cycle, wherein the threshold time is configured as a fraction of the time that the SR FET (106) was turned on in one or more previous switching cycles, And wherein Vreg2 is less than Vreg1.

2. The electronic rectifier circuit (400) according to claim 1, comprising: a first Vg detection component (410) configured to measure an amount of time that the SR FET (106) is turned on and store a first signal representative of the amount of time in a sample holder (430); a second Vg sensing component (420) configured to measure another amount of time that the SR FET (106) is turned on to obtain a second signal; a comparator (442) having as inputs the first signal obtained from the sample holder (430) and the second signal and having as output a selection signal; A multiplexer (440) is configured to output Vreg1 or Vreg2 according to the selection signal.

3. The electronic rectifier circuit (400) of claim 2, wherein the first Vg detection component (410) includes a first capacitor (412), and wherein the second Vg detection component (420) includes a second capacitor (422), wherein the first capacitor and the second capacitor are sized in a ratio that defines the threshold time.

4. The electronic rectifier circuit (400) of claim 3, wherein the second capacitor (422) is sized at 90% of the value of the first capacitor (412).

5. A fast charging power supply (100), comprising a transformer (102), a primary side field effect transistor PriFET (104), a synchronous rectifier field effect transistor SR FET (106), and an electronic rectifier circuit (400) according to any one of claims 1 to 4.

6. A method for adaptively regulating a gate voltage Vg of a synchronous rectifier field effect transistor (SR FET), the method comprising: turning on (808) the SR FET by setting the Vg of the SR FET high; Starting a timer (810) for counting the on-time of the SR FET in the current switching cycle; determining (812) whether the on-time of the SR FET exceeds at least a portion of a previous on-time of the SR FET in one or more previous switching cycles; If the on-time does not exceed the portion of the previous on-time, clamping (816) the drain-source voltage Vds to a first regulated voltage Vreg1; If the on-time exceeds the portion of the previous on-time, Vds is clamped (820) to a second regulated voltage Vreg2.

7. The method according to claim 7, further comprising: After detecting that the Vds of the SR FET is lower than a turn-on threshold Von_th, the SR FET is turned on (808).

8. The method according to claim 6 or claim 7, further comprising: After clamping the Vds to the Vreg2, determining (822) whether the Vds of the SR FET exceeds a turn-off threshold Voff_th; and If the Vds of the SR FET exceeds the Voff_th, the SR FET is turned off (824) by setting the Vg low.

9. The method according to any one of claims 6 to 8, further comprising: After the SR FET has been turned off, the timer is stopped (826) and the on-time of the SR FET obtained by the timer is stored to be used as the previous on-time in a next switching cycle.

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