Nested floating converter dynamic amplifier and operation method and circuit thereof

Abstract

The invention discloses a nested floating converter dynamic amplifier and an operation method and circuit thereof. According to an embodiment, a nested floating transducer dynamic amplifier (FIDA) includes: a first FIDA amplifier including a plurality of first transducers switchably coupled to a first storage capacitor; and a second FIDA amplifier including a plurality of second converters switchably coupled to the second storage capacitor, where outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters.

Description

Technical Field

[0001] The present invention relates generally to systems and methods for electronic systems and, in particular embodiments, to systems and methods for nested floating converter based amplifiers. Background Art

[0002] A floating converter dynamic amplifier (FIDA) is an amplifier that uses a converter-based amplifier and a storage capacitor. During operation, the storage capacitor is first charged by a power supply. Next, the storage capacitor is disconnected from the power supply and connected to the power supply terminal of the converter-based amplifier in a floating configuration to supply power to the amplifier. FIDA can achieve high energy efficiency, low noise, and reduce the impact of input common-mode voltage on circuit performance.

[0003] FIDA can be used in various applications that require high-speed and low-power analog signal processing, such as comparators, amplifiers, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). For example, FIDA can be used as a preamplifier for a comparator or as an amplifier in a switched capacitor amplifier system.

[0004] However, existing FIDA designs have some limitations and challenges, such as low gain accuracy and large variations in output response over process, supply voltage, and temperature (PVT) variations. Summary of the invention

[0005] According to an embodiment, a nested floating converter dynamic amplifier (FIDA) includes: a first FIDA amplifier, which includes a plurality of first converters switchably coupled to a first storage capacitor; and a second FIDA amplifier, which includes a plurality of second converters switchably coupled to a second storage capacitor, wherein outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters.

[0006] According to another embodiment, a method of operating a nested floating converter dynamic amplifier (FIDA), the FIDA comprising a first FIDA amplifier and a second FIDA amplifier, the first FIDA amplifier comprising a plurality of first converters switchably coupled to a first storage capacitor, the second FIDA amplifier comprising a plurality of second converters switchably coupled to a second storage capacitor, wherein outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters, the method comprising: during a charging phase, charging the first storage capacitor and the second storage capacitor to a first voltage; and during an amplification phase, connecting the first storage capacitor to the plurality of first converters and connecting the second storage capacitor to the plurality of second converters, wherein the first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase.

[0007] According to another embodiment, a circuit includes: a first converter having an input coupled to a first input node; a first load converter coupled to the output of the first converter, wherein the input of the first load converter is connected to the output of the first load converter; a second converter having an input coupled to a second input node; a second load converter coupled to the output of the first converter, wherein the input of the second load converter is connected to the output of the second load converter; a first storage capacitor switchably coupled to power supply nodes of the first converter and the second converter; and a second storage capacitor switchably coupled to power supply nodes of the first load converter and the second load converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A shows a schematic diagram of a conventional FIDA system; Figure 1B shows a timing diagram that may be used for a conventional FIDA system and an embodiment FIDA system; and Figure 1C shows a graph of gain versus time for a conventional FIDA system;

[0010] Figure 2A shows a schematic diagram of a nested FIDA system according to an embodiment; Figure 2B shows an equivalent circuit for a nested FIDA system according to an embodiment; and Figure 2C , Figure 2D and Figure 2E including a graph showing and comparing gain versus time characteristics of a conventional FIDA system and a FIDA system according to an embodiment;

[0011] Figure 3A shows a schematic diagram of a converter circuit according to an alternative embodiment that can be used in a nested FIDA system according to an embodiment; Figure 3B , Figure 3C and Figure 3D shows a schematic diagram of a FIDA system according to an alternative embodiment; and Figure 3E An implementation of a nested FIDA core circuit is shown;

[0012] Figure 4 A block diagram showing a method according to an embodiment; and

[0013] Figure 5A shows a data converter utilizing a nested FIDA system according to an embodiment; Figure 5B Shows that it can be used Figure 5A A quantizer circuit of a data converter; Figure 5C A noise shaping successive approximation (SAR) analog-to-digital converter (ADC) utilizing a nested FIDA system according to an embodiment is shown; and Figure 5D Shown with Figure 5C Timing diagram associated with a noise shaping SAR ADC.

[0014] Unless otherwise indicated, corresponding reference numerals in different figures generally refer to corresponding parts. The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. In order to more clearly illustrate certain embodiments, letters indicating variations of the same structure, material, or processing step may follow the figure number. DETAILED DESCRIPTION

[0015] The formation and use of the preferred embodiment are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in various specific contexts. The specific embodiments discussed only illustrate the specific ways to form and use the present invention and do not limit the scope of the present invention.

[0016] Embodiments of the present invention relate to FIDA amplifiers with stable gain. In embodiments, the FIDA amplifier comprises a first FIDA amplifier loaded by a second FIDA amplifier having its input coupled to its output. In some embodiments, various components of the second FIDA amplifier are scaled relative to the first FIDA amplifier according to a common scaling factor. The resulting FIDA amplifier according to embodiments advantageously exhibits a stable gain that depends on the common scaling factor. In some embodiments, the stable gain is advantageously robust to PVT variations and random mismatches.

[0017] FIG. 1 shows a conventional FIDA system 100 including a FIDA core 102 and a load circuit 112. As shown, the amplifier core 102 includes two converters 104A and 104B coupled to a storage capacitor C1 via a switching network including switches S1, S2, S3, and S4. The load circuit 112 includes a load capacitor C1 coupled to the outputs of the converters 104A and 104B via a switching network including switches S5, S6, S7, and S8. L As shown, each converter includes a PMOS transistor P1 and an NMOS transistor N1. The reset switching signal Φ R Used to control switches S3, S4, S5 and S6 and amplify the switching signal Φ A Used to control switches S1 and S2 and sample the switching signal Φ S Used to control switches S7 and S8.

[0018] Figure 1BA timing diagram illustrating the operation of the FIDA system 100 and the timing of the embodiments described herein is shown. During the first stage of operation, the switching signal Φ is amplified. A If the reset switching signal Φ is not asserted, R and sampling switching signal Φ S During this phase of operation, the storage capacitor C1 is coupled to the power supply node V via switches S3 and S2. dd and ground. Converters 104A and 104B are disconnected from storage capacitor C1, and the common mode voltage V cm Applied to the output of converters 104A, 104B and load capacitor C via switches S5 and S6 L At time t2, the reset switching signal Φ R is deasserted, which will store capacitor C1 and the power supply node V dd and ground, and the common-mode voltage node V cm The outputs of converters 104A and 104B and load capacitor C L disconnect.

[0019] In the amplified switching signal Φ A When t is enabled, the second phase of operation begins at time t3. In this second phase of operation, storage capacitor C1 is applied to the power supply nodes of converters 104A and 104B, which enables current to flow in converters 104A and 104B, thereby enabling converters 104A and 104B to amplify input signal V ip With V im And generate an amplified output signal V om With V op During this phase of operation, the current through transistors P1 and N1 of converters 104A and 104B steadily decreases as reservoir capacitor C1 is discharged. In some cases, transistors P1 and N1 start with a medium inversion and end with a weak inversion.

[0020] At time t4, the sampling switching signal Φ S is de-asserted, which opens switches S7 and S8 to connect the load capacitor C L The converters 104A and 104B are disconnected, thereby the load capacitor C L The output voltage V op and V om Sampling is performed. This period of time can be referred to as a sampling phase or a readout phase. At time t5, the amplified switching signal Φ A is deasserted and the next cycle operation may occur again starting from time t1.

[0021] The FIDA system 100 is current efficient because it does not require any quiescent bias current. Its structure enables both the PMOS transistor P1 and the NMOS transistor N1 to contribute to amplification and provides intrinsic common-mode feedback because no common-mode current flows to the output. However, due to its structure and operation, the FIDA system 100 has Figure 1C The graph shows the gain increasing logarithmically with time, Figure 1C The gain versus time characteristics of the FIDA core 102 are shown. As shown, for the same amplification time t=t4-t3, a 20% change in the circuit's time constant τ0 causes a 10% gain change. In addition, the gain of the FIDA system 100 is very sensitive to PVT variations, and the speed of the amplifier becomes exponentially slower with increased accuracy requirements. In some cases, calibration circuits and algorithms can be used in conjunction with the FIDA system 100 to calibrate the gain at the expense of increased complexity.

[0022] Figure 2A 1 shows a nested FIDA system 200 according to an embodiment of the present invention. As shown, the nested FIDA system 200 includes a nested FIDA core 202 and a load circuit 112. The nested FIDA core 202 and the load circuit 112 are connected to each other. Figure 1A 1 is similar to the FIDA core 102 shown in FIG. 1 in that it includes a storage capacitor C1 (also referred to as a first storage capacitor) and converters 104A and 104B, each of which includes a PMOS transistor P1 and an NMOS transistor N1; however, the nested FIDA core 202 according to an embodiment further includes a second FIDA circuit, the second FIDA circuit including converters 206A and 206B coupled to the outputs of converters 104A and 104B, respectively, and switchably coupled to a power supply node V via switches S11 and S12. dd A second storage capacitor C2 is switchably coupled to the power supply node of converters 206A and 206B and ground via switches S9 and S10. In some embodiments, each switch S1 to S12 can be implemented using a transistor (e.g., an NMOS transistor, a PMOS transistor, a CMOS transmission gate composed of an NMOS transistor coupled in parallel with a PMOS transistor, or other types of transistors or switching circuits known in the art). In some embodiments, load circuit 112 can be part of an input stage of a load circuit, such as a switched capacitor amplifier and / or a feedback network coupled to FIDA system 200.

[0023] During operation, switches S9, S10, S11 and S12 of the second FIDA circuit are switched in a similar manner as switches S1, S2, S3 and S4 of the first FIDA circuit. For example, during a first stage of operation, the reset switching signal Φ Ris enabled, the second storage capacitor C2 is connected to the power supply node V dd On the other hand, the amplified switching signal Φ A When enabled, the second storage capacitor C2 is connected to the power supply nodes of the converters 206A and 206B. In various embodiments, the size of the components of the second FIDA amplifier is scaled relative to the first FIDA amplifier by a common scaling factor F. For example, the W / L ratio (also referred to as the aspect ratio) of the PMOS transistor P2 and the NMOS transistor N2 of the converters 206A and 206B is one-f times the W / L ratio of the PMOS transistor P1 and the NMOS transistor N1 of the converters 104A and 104B; the capacitance of the second storage capacitor C2 is one-f times the capacitance of the first storage capacitor C1, so that the ratio of the capacitance of the first storage capacitor C1 to the capacitance of the second storage capacitor C2 is the common scaling factor F, and the switches S9, S10, S11 and S12 are one-f times the switches S1, S2, S3 and S4. Therefore, the transconductance ratio of the first FIDA amplifier to the second FIDA amplifier is the common scaling factor F. Another way to express this is that the ratio of the strength of converter 104A to the strength of converter 206A and the ratio of the strength of converter 104B to the strength of converter 206B is a common scaling factor F. Furthermore, the transistors used to implement switches S9, S10, S11, and S12 are one-fifth the transistors used to implement switches S1, S2, S3, and S4. In some embodiments, components (e.g., switches, transistors, and capacitors) of the first FIDA amplifier and the second FIDA amplifier are implemented using unit cells to facilitate a more accurate scaling factor F.

[0024] In various embodiments, some or all of the components of the nested FIDA system 200 and other embodiments disclosed herein may be implemented on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate and / or silicon substrate. The nested FIDA system 200 may be manufactured using one of a variety of different semiconductor processes (e.g., CMOS, FinFET, BiCMOS, SOI, or other types of semiconductor processes).

[0025] Figure 2B 2 shows a simplified single-ended circuit model of the nested FIDA system 200. As shown, the converters 104A and 104B of the first FIDA are modeled as transconductors G m ; The transformers 206A and 206B of the second FIDA are modeled as F / G m and the capacitance at the output of converters 104A and 104B is modeled as capacitor C0, where F is a common scaling factor. Therefore, it can be shown that the asymptotic value of the voltage gain G is ideally the transconductance G mWith load resistance F / G m The product of:

[0026] G=V in / V out =G m ×F / G m =F

[0027] Taking into account the finite transistor self-gain μ, it can be shown that the asymptotic value of the voltage gain G is:

[0028]

[0029] Therefore, in the case where the self-gain μ is greater than the desired gain F, the asymptotic value of the voltage gain G is approximately G. Therefore, in such a case, even though the self-gain μ is PVT-dependent, the resulting asymptotic value of the voltage gain G is insensitive to PVT variations and random mismatches. It should be understood that due to variations in the bias current during operation, the transconductance G m and load resistance F / G m is a quantity that changes with time. However, due to the transconductance G m With load resistance F / G m Due to the symmetry between , the product between these two quantities remains constant.

[0030] Figure 2C A graph of gain versus time is shown. It can be seen that, assuming a value of F=10, the gain settles to a value of about 10 in about six time constants. Furthermore, it can be seen that a 20% change in the time constant τ0 has a negligible effect on the gain G.

[0031] Figure 2D A comparison of the gain of a conventional FIDA system 100 with respect to time is shown. Curves 252, 254, and 256 represent the voltage gain of the FIDA system 100 for a fast process corner, a nominal process corner, and a slow process corner. It can be seen that in addition to the logarithmic increase in gain over time, the gain at the fast process corner 252 is significantly higher than the gain at the slow process corner 256.

[0032] Figure 2EA comparison of gain versus time for a nested FIDA system 200 according to an embodiment is shown, the nested FIDA system 200 according to an embodiment having a common scaling factor F of 12 and a self-gain μ of approximately 60, which yields a gain of 10. Curves 262, 264, and 266 represent the voltage gain of the nested FIDA system 200 according to an embodiment for fast process corners, nominal process corners, and slow process corners. It can be seen that the gain converges to 10 with very little gain variation with fast process corner 262, nominal process corner 264, and slow process corner 266. (The very little gain variation seen is due to variation in self-gain μ with process.) The performance of the nested FIDA system 200 shows similar improvements over the conventional FIDA system 100 over variations in supply voltage and temperature.

[0033] It should be understood that Figure 2C , Figure 2D and Figure 2E The performance of the conventional FIDA system 100 in FIG. 1 and the performance of the nested FIDA system 200 according to an embodiment are merely illustrative examples. The performance of other example systems may vary based on the specific implementation; however, conventional FIDA systems typically have a logarithmic gain characteristic over time and are sensitive to PVT variations and random mismatches, while nested FIDA systems according to embodiments typically have a gain that converges to a specific value over time and is less sensitive to PVT variations and random mismatches than conventional FIDA systems. Therefore, it can be seen that a nested FIDA system according to an embodiment can be used to achieve predictable gain by sampling the output after a certain number of time constants that depends on the desired gain accuracy. Since the gain is stable to a predetermined value, the timing of the sampling phase does not significantly affect the accuracy of the nested FIDA amplifier. On the other hand, in situations where gain accuracy is important to system operation, the time-dependent logarithmic gain characteristic of conventional FIDA amplifiers places significant restrictions on the timing of the sampling phase.

[0034] It should be understood that nested FIDA system 200 is only one example of many possible ways to implement a nested FIDA according to an embodiment. For example, as shown, cascaded converter circuit 302 that can be used to implement converters 104A and 104B and cascaded converter circuit 304 that can be used to implement converters 206A and 206B are shown. Figure 3AAs shown, converter 104A, 104B, 206A and 206B can be implemented differently to provide increased output impedance. As shown, cascade converter 302 includes PMOS transistors P1 and P1C and NMOS transistors N1 and N1C. Similarly, cascade converter 304 includes PMOS transistors P2 and P2C and NMOS transistors N2 and N2C, wherein NMOS transistors N1C and N2C and PMOS transistors P1C and P2C are used as cascade transistors. Cascade bias circuitry known in the art (not shown) can be used to generate a voltage of a node VCP coupled to the gate of PMOS transistors P1C and P2C and a voltage of a node VCN coupled to the gate of NMOS transistors N1C and N2C.

[0035] It should also be understood that Figure 2A The load circuit 112 depicted in FIG. 1 is only one of a number of possible load circuits that may interface with the nested FIDA core 202 according to an embodiment. Figure 3B As shown in FIG. 1 , the nested FIDA system 320 includes a load circuit 322 coupled to the Figure 2A The nested FIDA core 202, where the load capacitor C L By having a coupled to node V x The terminals of the two load capacitors C LP and C LN As shown, the load capacitor C LP The switch S7 is coupled to the node V x between, and capacitor C LN The switch S8 is coupled to the node V x The operation of load circuit 322 is similar to that of load circuit 112 described above.

[0036] Figure 3C 3. A nested FIDA system 330 is shown, which includes a nested FIDA core 202 coupled to a load circuit 332. The load circuit 332 is similar to Figure 3B The load circuit 322 shown in FIG. 1 includes a capacitor C coupled to the load circuit 322. LP With node V x The switch S13 is coupled between the capacitor C LN With node V x As shown, switches S13 and S14 are switched by the sampled switching signal Φ S Control, the same is true for switches S7 and S8.

[0037] Figure 3DA nested FIDA system 340 is shown, which includes a nested FIDA core 202 coupled to a load circuit 342, which includes a load circuit 342 that connects the output node V op and V om switchably coupled to the common-mode voltage node V cm The switches S5 and S6 are respectively coupled to V op and V om The two capacitors C between LP and C LM During operation, the reset switching signal Φ R is turned on, the common-mode voltage V cm is applied to the output node V op and V om . In the amplified switching signal Φ A When enabled, the outputs of converters 104A and 104B are applied to capacitor C LP and C LM . Output V op and V om Another sampling circuit (not shown) can be used to sample the switching signal Φ S Sampling is performed and / or may be coupled to a non-switching amplifier (not shown).

[0038] It should be appreciated that load circuits 112, 322, 332, and 342 are only four of many possible load circuit architectures that may interface with a nested FIDA core according to embodiments.

[0039] Figure 3E It shows that it can be used to implement Figure 2A 202 is shown in FIG. 20. As shown, the nested FIDA core 350 includes the nested FIDA core 202 described above. Figure 1A The same FIDA core 102 as described above. In an embodiment, each of these FIDA cores has the same size reservoir capacitor C1, converters 104A and 104B, and switches S1, S2, S3, and S4. The output of the nested FIDA core 350 can also be coupled to a load circuit, such as the load circuit 112 described above.

[0040] As shown, the first group of F FIDA cores 1021 to 102 F A single FIDA core 102 having its positive input connected to its negative output and its negative input coupled to its positive output L is coupled to F FIDA cores 1021 to 102 F In various embodiments, the output of the FIDA cores 1021 to 102 FThe gain of the FIDA core 350 is adjusted by the number of F FIDA cores used in the nested FIDA core 350. The resulting voltage gain of the nested FIDA core 350 is approximately F. In some embodiments, the FIDA core 102 may be connected by coupling its input to its output in parallel. L For example, when using two FIDA cores 102 coupled in parallel, L In an embodiment, the gain of the FIDA core 350 will be approximately two.

[0041] Figure 4 A method 400 of operating an embodiment nested FIDA amplifier is shown, the embodiment nested FIDA amplifier may include a first FIDA amplifier and a second FIDA amplifier, the first FIDA amplifier including a plurality of first converters switchably coupled to a first storage capacitor, the second FIDA amplifier including a plurality of second converters switchably coupled to a second storage capacitor. For example, the first FIDA amplifier and the second FIDA amplifier may each use the above-described method for Figure 3E The FIDA core circuit 102 described above can be implemented or can be implemented according to Figure 2A The outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters.

[0042] As shown, the method includes at least two phases: a charging phase (step 402) and an amplification phase (step 404). During the charging phase 402, the first storage capacitor C1 and the second storage capacitor C2 are charged to a predetermined voltage V cm .

[0043] Entering the amplification phase 404, the first storage capacitor C1 is connected to the plurality of first converters 104A and 104B, and the second storage capacitor C2 is connected to the plurality of second converters 206A and 206B. This configuration enables the amplification process to occur. In various embodiments, both the first FIDA amplifier 102 and the second FIDA amplifier are configured to float during the amplification phase.

[0044] Figure 5AA data converter 500 that can be configured to utilize a nested FIDA system according to an embodiment is shown. The data converter 500 can be implemented using a sigma-delta modulator or a noise-shaping successive approximation (SAR) analog-to-digital converter (ADC). As shown, the data converter 500 includes a loop filter 504, a quantizer 508, a digital-to-analog converter (DAC) 510, and two summing circuits 502 and 506. In various embodiments, the loop filter 504 includes at least one switched capacitor circuit, such as a switched capacitor amplifier or a switched capacitor integrator, utilizing a nested FIDA system according to an embodiment. During operation, the adder 502 subtracts the output of the DAC 510 from the input voltage to form a residual voltage V res , and then the residual voltage V is filtered by the loop filter 504 res The output of the loop filter 504 can be optionally coupled to the input voltage V in The DAC 510 generates an output based on the output of the quantizer 508 and then generates an output from the input voltage V in Subtract this output from the Figure 5A The feedback action of the loop depicted in is used to push the noise generated by the quantizer 508 (including quantization noise) to higher frequencies, thereby increasing the signal-to-noise ratio of lower frequency signals.

[0045] In a sigma delta modulator according to an embodiment, the quantizer 508 may be a one-bit quantizer implemented using, for example, a comparator circuit, or may be a multi-bit quantizer implemented using, for example, a flash ADC.

[0046] In a noise sampling SAR ADC, the quantizer 508 may be implemented using a comparator with a DAC in the feedback path. For example, Figure 5B A quantizer 530 is shown that can be used to implement the quantizer 508 in a noise sampling SAR ADC. As shown, the quantizer 530 includes an adder 502 having an output coupled to an input of a comparator 534. A DAC 536 is coupled between the output of the comparator 534 and the inverting input of the adder 532.

[0047] The loop filter 504 may include one or more nested FIDA systems according to embodiments. By using nested FIDA systems according to embodiments, active amplifiers may be advantageously used in a power efficient manner to provide power efficient data converter operation. For example, Figure 5C5 shows a schematic diagram of a noise shaping SAR ADC 550, which includes a comparator 554, a successive approximation register 552, a capacitor-based DAC array 560, and a loop filter 556. The loop filter 556 includes a FIDA amplifier 558, an integrating capacitor C according to an embodiment. int and capacitor C iir .

[0048] Figure 5D Shows the description Figure 5C The timing diagram of the operation of the noise shaping SAR ADC 550. T During this period, the capacitor C of the capacitor-based DAC array 560 DAC Upper input voltage V in+ and V in- Next, at phase Φ SH During this period, the capacitor C iir and C int During this phase, the comparator 554, the successive approximation register 552, and the capacitor-based DAC array 560 work together to charge the capacitors Cir and C int The upsampled voltage performs successive approximation. As shown, the phase signal Φ CMP In phase Φ SH The period is pulsed multiple times. Each phase Φ SH When activated, comparator 554 measures the iir and C int The upsampled voltage updates the value stored in the successive approximation register 552, which in turn updates the capacitor C applied to the capacitor-based DAC array 560. DAC Switching configuration.

[0049] Next, the phase signal Φ EX and Φ AMP is asserted to activate the FIDA amplifier 558 according to an embodiment and the capacitor C iir The output of the FIDA amplifier 558 according to the embodiment is sampled at φ. Then, the switching cycle is in the phase signal Φ T Repeat where effective.

[0050] It should be understood that FIG. 5A to FIG. 5D The data converter systems and subsystems described are only some examples of many possible systems in which nested FIDA amplifiers according to embodiments may be used.

[0051] Embodiments of the present invention are summarized here. Other embodiments can also be understood based on the entire specification and claims submitted.

[0052] Example 1. A nested floating converter dynamic amplifier (FIDA) comprising: a first FIDA amplifier comprising a plurality of first converters switchably coupled to a first storage capacitor; and a second FIDA amplifier comprising a plurality of second converters switchably coupled to a second storage capacitor, wherein outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters.

[0053] Example 2. The nested FIDA of Example 1, wherein: a ratio of a transconductance of the first FIDA amplifier to a transconductance of the second FIDA amplifier is a first factor; and a ratio of a capacitance of the first reservoir capacitor to a capacitance of the second reservoir capacitor is a first factor.

[0054] Example 3. A nested FIDA according to Example 2, wherein: each of the plurality of first converters includes a first PMOS transistor and a first NMOS transistor; each of the plurality of second converters includes a second PMOS transistor and a second NMOS transistor; a ratio of an aspect ratio of the first PMOS transistor to an aspect ratio of the second PMOS transistor is a first factor; and a ratio of an aspect ratio of the first NMOS transistor to an aspect ratio of the second NMOS transistor is a first factor.

[0055] Example 4. The nested FIDA of one of Examples 2 to 3, wherein the voltage gain of the nested FIDA is the first factor.

[0056] Example 5. The nested FIDA of one of Examples 1 to 4, further comprising a controller configured to: charge the first reservoir capacitor and the second reservoir capacitor to a first voltage during a charging phase; and connect the first reservoir capacitor to the plurality of first converters and connect the second reservoir capacitor to the plurality of second converters during an amplification phase, wherein the first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase.

[0057] Example 6. The nested FIDA of Example 5, wherein the controller is further configured to disconnect at least one output capacitor from the outputs of the plurality of first converters during the readout phase.

[0058] Example 7. The nested FIDA of one of Examples 1 to 6, wherein an input of each second transformer of the plurality of second transformers is coupled to its corresponding output.

[0059] Example 8. The nested FIDA of one of Examples 1 to 7, further comprising at least one output capacitor coupled to the outputs of the plurality of first converters.

[0060] Example 9. A method of operating a nested floating converter dynamic amplifier (FIDA), the FIDA comprising a first FIDA amplifier and a second FIDA amplifier, the first FIDA amplifier comprising a plurality of first converters switchably coupled to a first storage capacitor, the second FIDA amplifier comprising a plurality of second converters switchably coupled to a second storage capacitor, wherein outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters, the method comprising: during a charging phase, charging the first storage capacitor and the second storage capacitor to a first voltage; and during an amplification phase, connecting the first storage capacitor to the plurality of first converters and connecting the second storage capacitor to the plurality of second converters, wherein the first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase.

[0061] Example 10. The method of Example 9, further comprising disconnecting at least one output capacitor from the outputs of the plurality of first converters during the readout phase.

[0062] Example 11. The method of one of Examples 9 or 10, further comprising transferring charge from the at least one output capacitor to the switched capacitor circuit during the readout phase.

[0063] Example 12. The method of one of Examples 9 to 11, further comprising amplifying an input voltage applied to the input of the plurality of first converters during the amplification phase.

[0064] Example 13. A circuit comprising: a first converter having an input coupled to a first input node; a first load converter coupled to the output of the first converter, wherein the input of the first load converter is connected to the output of the first load converter; a second converter having an input coupled to a second input node; a second load converter coupled to the output of the first converter, wherein the input of the second load converter is connected to the output of the second load converter; a first storage capacitor switchably coupled to power supply nodes of the first converter and the second converter; and a second storage capacitor switchably coupled to power supply nodes of the first load converter and the second load converter.

[0065] Example 14. A circuit according to Example 13, wherein: the ratio of the strength of the first converter to the strength of the first load converter is a first factor; the ratio of the strength of the second converter to the strength of the second load converter is a first factor; and the ratio of the capacitance of the first storage capacitor to the capacitance of the second storage capacitor is a first factor.

[0066] Example 15. A circuit according to one of Examples 13 or 14, wherein: the first converter includes a first NMOS transistor and a first PMOS transistor; the first load converter includes a first NMOS load transistor and a first PMOS load transistor; the second converter includes a second NMOS transistor and a second PMOS transistor; and the second load converter includes a second NMOS load transistor and a second PMOS load transistor.

[0067] Example 16. A circuit according to one of Examples 13 to 15, further comprising a controller configured to: during a reset phase: disconnect the first storage capacitor from the power supply node of the first converter and the second converter, and connect the first storage capacitor to a power supply terminal configured to provide a power supply voltage across the terminals of the first storage capacitor, and disconnect the second storage capacitor from the power supply node of the first load converter and the second load converter, and connect the power supply terminal across the terminals of the second storage capacitor; and during an amplification phase, disconnect the first storage capacitor from the power supply terminal, and connect the terminals of the second storage capacitor to the power supply node of the first converter and the second converter, and disconnect the second storage capacitor from the power supply terminal, and connect the terminals of the second storage capacitor to the power supply nodes of the first load converter and the second load converter.

[0068] Example 17. A circuit according to Example 16, wherein the controller is further configured to: during a reset phase, couple at least one output capacitor and the outputs of the first converter and the second converter to a reference voltage node configured to provide a reference voltage; and during an amplification phase, disconnect at least one output capacitor and the outputs of the first converter and the second converter from the reference voltage node, and connect at least one output capacitor to the output of the first converter and the output of the second converter.

[0069] Example 18. The circuit of Example 17, wherein the controller is further configured to disconnect the at least one output capacitor from the first converter and from the second converter during the readout phase.

[0070] Example 19. The circuit according to one of Examples 13 to 18 further includes: a first switch coupled between the first terminal of the first storage capacitor and the first power supply terminal; a second switch coupled between the second terminal of the first storage capacitor and the second power supply terminal; a third switch coupled between the first terminal of the second storage capacitor and the first power supply terminal; a fourth switch coupled between the second terminal of the second storage capacitor and the second power supply terminal; a fifth switch coupled between the first terminal of the first storage capacitor and the first power supply node of the first converter and the second converter; a sixth switch coupled between the second terminal of the first storage capacitor and the second power supply node of the first converter and the second converter; a seventh switch coupled between the first terminal of the second storage capacitor and the first power supply node of the first load converter and the second load converter; an eighth switch coupled between the second terminal of the second storage capacitor and the second power supply node of the first load converter and the second load converter; a ninth switch coupled between the output of the first converter and the reference voltage node; and a tenth switch coupled between the output of the second converter and the reference voltage node.

[0071] Example 20. The circuit of Example 19, further comprising: an eleventh switch coupled between the output of the first converter and at least one output capacitor; and a twelfth switch coupled between the output of the second converter and at least one output capacitor.

[0072] Example 21. The circuit according to one of Examples 19 to 20 further includes a controller configured to: turn on the first switch, the second switch, the third switch, the fourth switch, the ninth switch and the tenth switch, and turn off the fifth switch, the sixth switch, the seventh switch and the eighth switch during a reset phase; and turn on the fifth switch, the sixth switch, the seventh switch and the eighth switch, and turn off the first switch, the second switch, the third switch, the fourth switch, the ninth switch and the tenth switch during an amplification phase.

[0073] Example 22. The circuit of Example 21, wherein the controller is further configured to turn off the eleventh switch and the twelfth switch during the readout phase.

[0074] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. After reference to this specification, various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A nested floating converter dynamic amplifier FIDA, comprising: a first FIDA amplifier comprising a plurality of first converters switchably coupled to a first reservoir capacitor; as well as A second FIDA amplifier includes a plurality of second converters switchably coupled to a second reservoir capacitor, wherein outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters.

2. The nested FIDA of claim 1, wherein: A transconductance ratio of the first FIDA amplifier to the second FIDA amplifier is a first factor; and A ratio of the capacitance of the first reservoir capacitor to the capacitance of the second reservoir capacitor is the first factor.

3. The nested FIDA of claim 2, wherein: Each of the plurality of first converters comprises a first PMOS transistor and a first NMOS transistor; Each of the plurality of second converters comprises a second PMOS transistor and a second NMOS transistor; A ratio of an aspect ratio of the first PMOS transistor to an aspect ratio of the second PMOS transistor is the first factor; and A ratio of an aspect ratio of the first NMOS transistor to an aspect ratio of the second NMOS transistor is the first factor.

4. The nested FIDA of claim 2, wherein: The voltage gain of the nested FIDA is the first factor.

5. The nested FIDA of claim 1 , further comprising a controller configured to: During a charging phase, charging the first reservoir capacitor and the second reservoir capacitor to a first voltage; and During the amplification phase, the first storage capacitor is connected to the plurality of first converters and the second storage capacitor is connected to the plurality of second converters, wherein, The first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase.

6. The nested FIDA of claim 5, wherein: The controller is also configured to disconnect at least one output capacitor from the outputs of the plurality of first converters during a readout phase.

7. The nested FIDA of claim 1, wherein: The input of each second converter of the plurality of second converters is coupled to its corresponding output.

8. The nested FIDA of claim 1, further comprising at least one output capacitor coupled to outputs of the plurality of first converters.

9. A method of operating a nested floating converter dynamic amplifier FIDA, the nested FIDA comprising a first FIDA amplifier comprising a plurality of first converters switchably coupled to a first reservoir capacitor and a second FIDA amplifier comprising a plurality of second converters switchably coupled to a second reservoir capacitor, wherein: The outputs of the plurality of first converters are coupled to corresponding inputs of the plurality of second converters, the method comprising: During a charging phase, charging the first reservoir capacitor and the second reservoir capacitor to a first voltage; and During an amplification phase, the first reservoir capacitor is connected to the plurality of first converters and the second reservoir capacitor is connected to the plurality of second converters, wherein the first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase.

10. The method of claim 9, further comprising disconnecting at least one output capacitor from the outputs of the plurality of first converters during a readout phase.

11. The method of claim 10, further comprising transferring charge from the at least one output capacitor to a switched capacitor circuit during the readout phase. 12 . The method of claim 9 , further comprising amplifying an input voltage applied to an input of the plurality of first converters during the amplifying phase.

13. A circuit comprising: a first converter having an input coupled to a first input node; a first load converter coupled to the output of the first converter, wherein the input of the first load converter is connected to the output of the first load converter; a second converter having an input coupled to the second input node; a second load converter coupled to the output of the first converter, wherein the input of the second load converter is connected to the output of the second load converter; a first storage capacitor switchably coupled to a power supply node of the first converter and a power supply node of the second converter; and A second reservoir capacitor is switchably coupled to a power supply node of the first load converter and a power supply node of the second load converter.

14. The circuit of claim 13, wherein: The ratio of the strength of the first transformer to the strength of the first load transformer is a first factor; The ratio of the strength of the second converter to the strength of the second load converter is the first factor; and A ratio of the capacitance of the first reservoir capacitor to the capacitance of the second reservoir capacitor is the first factor.

15. The circuit of claim 13, wherein: The first converter includes a first NMOS transistor and a first PMOS transistor; The first load converter includes a first NMOS load transistor and a first PMOS load transistor; The second converter includes a second NMOS transistor and a second PMOS transistor; and The second load converter includes a second NMOS load transistor and a second PMOS load transistor.

16. The circuit of claim 13, further comprising a controller configured to: During the reset phase: disconnecting the first reservoir capacitor from a power supply node of the first converter and a power supply node of the second converter and connecting the first reservoir capacitor to a power supply terminal configured to provide a supply voltage across terminals of the first reservoir capacitor, and disconnecting the second reservoir capacitor from a power supply node of the first load converter and a power supply node of the second load converter and connecting the second reservoir capacitor to a power supply terminal across terminals of the second reservoir capacitor; and During the scale-up phase: disconnecting the first reservoir capacitor from the power supply terminals and connecting the terminals of the first reservoir capacitor to the power supply node of the first converter and the power supply node of the second converter, and The second reservoir capacitor is disconnected from the power supply terminals, and terminals of the second reservoir capacitor are connected to a power supply node of the first load converter and a power supply node of the second load converter.

17. The circuit of claim 16, wherein: The controller is also configured to: During the reset phase, coupling at least one output capacitor and an output of the first converter and an output of the second converter to a reference voltage node configured to provide a reference voltage; as well as During the amplification phase, the at least one output capacitor and the output of the first converter and the output of the second converter are disconnected from the reference voltage node, and The at least one output capacitor is connected to the output of the first converter and to the output of the second converter.

18. The circuit of claim 17, wherein: The controller is also configured to disconnect the at least one output capacitor from the first converter and from the second converter during a readout phase.

19. The circuit of claim 13, further comprising: a first switch coupled between a first terminal of the first storage capacitor and a first power supply terminal; a second switch coupled between the second terminal of the first storage capacitor and a second power supply terminal; a third switch coupled between the first terminal of the second storage capacitor and the first power terminal; a fourth switch coupled between the second terminal of the second storage capacitor and the second power terminal; a fifth switch coupled between the first terminal of the first storage capacitor and the first power supply node of the first converter and the first power supply node of the second converter; a sixth switch coupled between the second terminal of the first storage capacitor and the second power supply node of the first converter and the second power supply node of the second converter; a seventh switch coupled between the first terminal of the second storage capacitor and the first power supply node of the first load converter and the first power supply node of the second load converter; an eighth switch coupled between the second terminal of the second storage capacitor and the second power supply node of the first load converter and the second power supply node of the second load converter; a ninth switch coupled between the output of the first converter and a reference voltage node; as well as A tenth switch is coupled between the output of the second converter and the reference voltage node.

20. The circuit of claim 19, further comprising: an eleventh switch coupled between the output of the first converter and at least one output capacitor; as well as A twelfth switch is coupled between the output of the second converter and the at least one output capacitor.

21. The circuit of claim 20, further comprising a controller configured to: During the reset phase, The first switch, the second switch, the third switch, the fourth switch, the ninth switch, and the tenth switch are turned on, and turning off the fifth switch, the sixth switch, the seventh switch, and the eighth switch; and During the scale-up phase, The fifth switch, the sixth switch, the seventh switch and the eighth switch are turned on, and The first switch, the second switch, the third switch, the fourth switch, the ninth switch, and the tenth switch are turned off.

22. The circuit of claim 21, wherein: The controller is also configured to turn off the eleventh switch and the twelfth switch during a readout phase.

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