Mirror image rejection filter structure, on-chip filter and radio frequency transceiver

Abstract

The invention provides a mirror image rejection filter structure, an on-chip filter and a radio frequency transceiver. The mirror image rejection filter structure comprises an inductance structure, a capacitance switch array, a compensation circuit, a differential amplifier basic circuit and an RC calibration circuit, the RC calibration circuit is respectively connected with the capacitor switch array and the compensation circuit; the inductor structure comprises a first inductor and a second inductor which are connected to the two ends of the capacitor switch array respectively, and the inductor structure and the capacitor switch array form a series resonance network. A compensation circuit is connected in parallel to one side of the series resonance network to form a parallel structure; the parallel structure is arranged in the middle of the symmetrical transistor structure in the differential amplifier basic circuit; according to the structure, the suppression of the mirror image frequency point can be realized, the influence on the Q value is reduced as much as possible on the premise that the mirror image frequency point is adjustable, and meanwhile, the influence of the resonance network on the working frequency band is reduced through the compensation circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an image suppression filter structure, an on-chip filter and a radio frequency transceiver. Background Art

[0002] For traditional superheterodyne transceivers, the classic image suppression mixer structure can be used to achieve suppression capability. Taking the transmitter as an example, the intermediate frequency signal and carrier signal are split into IQ orthogonal signals respectively, and then vector synthesized after up-conversion mixing by the mixer to achieve the function of image signal suppression. The core reason for the output of residual image components under this structure is due to the mismatch of the mixer differential pair tubes, the LO Buffer output IQ mismatch, and the intermediate frequency IQ mismatch. These mismatches cannot be completely avoided, so the image suppression capability of a reasonable image suppression mixer is about 30dB. If you want to provide higher image suppression capability, you need to make additional designs on the system.

[0003] The simplest idea is to achieve image suppression by relying on the natural frequency response of the RF link. The principle is to rely on the frequency response characteristics of the RF amplifier LC Tank to suppress and amplify the useful signal and suppress the image signal. This idea requires requirements for the frequency of the intermediate frequency signal. If the IF signal frequency is higher, the image signal frequency is farther away from the useful signal frequency, and the frequency response characteristics of the RF link can be enjoyed more. However, the higher the IF frequency is, the more difficult it is to design the intermediate frequency circuit. From a system perspective, the benefits are not high. Therefore, achieving high image suppression capability at a relatively low IF frequency becomes a problem, and it is necessary to consider integrating filters on the link.

[0004] There are three solutions for on-chip filters. The first is to use a transmission line on the substrate, the second is to seal other filter chips together, and the third is to design an on-chip filter, but all of them have certain problems. The existing mainstream design solution is to use a capacitor array to meet the frequency band coverage requirements. The fixed capacitors in the LC resonant network in the filter are designed as capacitor arrays, and different codewords are configured through the internal SPI to control the switching of the capacitor array to adjust the LC resonance point. This method can solve the frequency coverage problem, but its disadvantage is that the switching of the capacitor array will cause the equivalent Q value of the LC network to decrease, affecting the suppression capability and the flatness of the working frequency band, resulting in the inability to take into account both frequency band coverage and high suppression capability. Summary of the invention

[0005] The purpose of the present application is to provide an image suppression filter structure, an on-chip filter and a radio frequency transceiver, which can suppress the image frequency and minimize the impact on the Q value as much as possible while ensuring that the image frequency is adjustable, while reducing the impact of the resonant network on the working frequency band through a compensation circuit.

[0006] In a first aspect, the present application provides an image suppression filter structure, which includes: an inductor structure, a capacitor switch array, a compensation circuit, a differential amplifier basic circuit and an RC calibration circuit; the RC calibration circuit is respectively connected to the capacitor switch array and the compensation circuit; the inductor structure includes a first inductor and a second inductor respectively connected to both ends of the capacitor switch array, and forms a series resonant network with the capacitor switch array; the compensation circuit is connected in parallel on one side of the series resonant network to form a parallel structure; the parallel structure is arranged in the middle of the symmetrical transistor structure in the differential amplifier basic circuit; the RC calibration circuit is used to generate a first capacitor adjustment signal and a second capacitor adjustment signal based on a calibrated control codeword to respectively adjust the capacitor switch array and the compensation circuit The capacitance value in the series resonant network is used to adjust the first capacitance value in the series resonant network according to the first capacitance adjustment signal of the RC calibration circuit, so as to adjust the resonance point of the series resonant network so as to fall within the specified range of the image frequency, thereby discharging the signal of the image frequency through the low-resistance channel to achieve the suppression of the image frequency; the compensation circuit is used to adjust the second capacitance value in the compensation circuit according to the second capacitance adjustment signal of the RC calibration circuit, so that the capacitor resonates with the residual inductance of the filter at the operating frequency, so that the series resonant network presents a high impedance state at the operating frequency, thereby reducing the impact on the operating frequency.

[0007] Furthermore, the above-mentioned capacitor switch array includes: a first transistor switch, a first capacitor and a second capacitor; the gate of the first transistor switch is connected to the output end of the RC calibration circuit, and is used to receive the first capacitor adjustment signal output by the RC calibration circuit; the source of the first transistor switch is connected to one end of the first capacitor, and the drain is connected to one end of the second capacitor; the other end of the first capacitor is connected to one end of the first inductor, and the other end of the second capacitor is connected to one end of the second inductor; the other end of the first inductor and the other end of the second inductor are both connected to the compensation circuit and the differential amplifier basic circuit.

[0008] Furthermore, the above-mentioned compensation circuit includes: an adjustable capacitor; the first end of the adjustable capacitor is connected to the other end of the first inductor, the second end of the adjustable capacitor is connected to the other end of the second inductor, and the third end of the adjustable capacitor is connected to the RC calibration circuit, which is used to receive the second capacitor adjustment signal output by the RC calibration circuit.

[0009] Furthermore, the above-mentioned differential amplifier basic circuit includes: a second transistor switch, a third transistor switch, a fourth transistor switch, a fifth transistor switch, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third inductor and a fourth inductor; the second transistor switch and the third transistor switch are open-loop RF amplifier Cascode tubes; the fourth transistor switch and the fifth transistor switch are open-loop RF amplifier Gm tubes.

[0010] Furthermore, the parallel structure is arranged in the middle of the symmetrical structure composed of the second transistor switch, the third transistor switch, the fourth transistor switch and the fifth transistor switch.

[0011] Furthermore, the source of the second transistor switch is connected to the drain of the fourth transistor switch, and the source of the third transistor switch is connected to the drain of the fifth transistor switch; the source of the fourth transistor switch and the source of the fifth transistor switch are connected to the ground terminal, the gate of the fourth transistor switch is connected to one end of the third capacitor, and the gate of the fifth transistor switch is connected to one end of the fourth capacitor; the drain of the second transistor switch is respectively connected to one end of the fifth capacitor and one end of the third inductor; the drain of the third transistor switch is respectively connected to one end of the sixth capacitor and one end of the fourth inductor; the other ends of the third inductor and the fourth inductor are both connected to the high level end; the other end of the third capacitor and the other end of the fourth capacitor are used to receive the RF differential input signal; the other end of the fifth capacitor and the other end of the sixth capacitor are used to output the RF differential output signal; the gate of the second transistor switch and the gate of the third transistor switch are used to receive the bias voltage signal.

[0012] Furthermore, one end of the parallel structure is connected to the source of the second transistor switch and the drain of the fourth transistor switch; the other end of the parallel structure is connected to the source of the third transistor switch and the drain of the fifth transistor switch.

[0013] Furthermore, all transistor switches in the above-mentioned image rejection filter structure are PMOS field effect transistors.

[0014] In a second aspect, the present application further provides an on-chip filter, which includes the image suppression filter structure as described in the first aspect.

[0015] In a third aspect, the present application further provides a radio frequency transceiver, the radio frequency transceiver comprising the on-chip filter as described in the second aspect.

[0016] In the image suppression filter structure, on-chip filter and radio frequency transceiver provided by the present application, the image suppression filter structure includes: an inductor structure, a capacitor switch array, a compensation circuit, a differential amplifier basic circuit and an RC calibration circuit; the RC calibration circuit is respectively connected to the capacitor switch array and the compensation circuit; the inductor structure includes a first inductor and a second inductor respectively connected to both ends of the capacitor switch array, and the capacitor switch array forms a series resonant network; the compensation circuit is connected in parallel on one side of the series resonant network to form a parallel structure; the parallel structure is arranged in the middle of the symmetrical transistor structure in the differential amplifier basic circuit; the RC calibration circuit is used to generate a first capacitor adjustment signal and a second capacitor adjustment signal based on a calibrated control codeword to respectively adjust the capacitor switch array and The capacitance value in the compensation circuit makes the total capacitance of the two parts of the capacitor remain unchanged under the fluctuation of various factors such as different processes, temperatures, and voltages, so as to ensure that the resonance point of the entire network remains unchanged; the series resonant network is used to adjust the first capacitance value in the series resonant network according to the first capacitance adjustment signal of the RC calibration circuit, so as to adjust the resonance point of the series resonant network so that it falls within the specified range of the image frequency point, thereby discharging the signal of the image frequency through the low-resistance channel to achieve the suppression of the image frequency point; the compensation circuit is used to adjust the second capacitance value in the compensation circuit according to the second capacitance adjustment signal of the RC calibration circuit, so that the capacitor resonates with the residual inductance of the filter at the working frequency point, so that the series resonant network presents a high impedance state at the working frequency point, reducing the impact on the working frequency point. This structure splits the traditional LC resonant inductor into two sections, such as the first inductor and the second inductor mentioned above, and inserts a capacitor switch array between the inductors, which can reduce the number of switches in the resonant capacitor array. Each channel in the capacitor switch array only needs one switch transistor, which greatly improves the quality factor of the entire resonant network, can achieve the suppression of the image frequency point, and minimize the impact on the Q value as much as possible under the premise of satisfying the adjustable image frequency point, and at the same time reduces the impact of the resonant network on the working frequency band through the compensation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A structural block diagram of an image suppression filter structure provided in an embodiment of the present application;

[0019] Figure 2 A circuit diagram of an image suppression filter structure provided in an embodiment of the present application;

[0020] Figure 3A schematic diagram of residual inductance at an operating frequency point provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] There are currently three on-chip filter solutions:

[0023] The first method: the substrate is realized by transmission line:

[0024] After evaluation, the passband is in the millimeter wave frequency band (27GHz~31.2GHz). If the intermediate frequency signal is 1.9G, its stopband is 3.8GHz away from the passband. At this time, the transmission line filter size is too large. In addition, for the 27GHz signal, the stopband is at 23.2GHz; for the 31.2GHz signal, the stopband is at 27.4GHz. There is a conflict between the stopband and the passband at high and low frequencies, and it is impossible to take into account all frequency points at the same time, so this solution cannot be implemented.

[0025] The second method: sealing other filter chips:

[0026] Different connection methods between chips in this solution will cause different effects. If the filter chip is located after the output stage of this chip, due to the inherent insertion loss of the filter, in order to ensure that the total output linearity remains unchanged, the output linearity of the previous chip is required, which makes this method more expensive. The second interface method is inter-stage connection. In the RF path, a certain level is connected to the filter chip through the substrate and then connected back to the chip. This method has no requirements for OP1dB, but it has requirements for the inter-stage interface. An additional Balun is required to convert the on-chip RF interface to a single-ended 50 ohm interface, which makes the RF link complex and the flatness worse. And the most important point is that the closed filter has similar problems to the transmission line filter solution. It is also difficult to take into account all high and low frequency points (it is necessary to find a suitable adjustable millimeter wave filter).

[0027] The first two solutions significantly increase the cost of the entire chip and system complexity, which is very costly.

[0028] The third type: on-chip filter design:

[0029] That is, an adjustable notch image suppression filter module is added to the RF link to achieve image suppression capability. The traditional notch filter provides a low-impedance discharge channel for the target frequency through a series LC network, and presents inductive / capacitive properties for other frequencies to achieve filtering function. For the notch filter, the following problems in its design will affect its performance:

[0030] 1. Filter suppression capability: If you want the filter to have high suppression capability, you need to present an LC network with a high Q value.

[0031] 2. The impact of filter frequency response on the working frequency band: For lower-frequency intermediate frequency signals, the image frequency point is very close to the working frequency point, so the filter frequency response will affect the flatness of the working frequency band.

[0032] 3. Frequency band coverage: The notch filter can only achieve suppression capability at the resonance point and can only achieve narrow-band design, and cannot cover a wider frequency band.

[0033] 4. Process fluctuations: Since the LC network is a high-Q network, it is very sensitive to capacitance fluctuations. When the capacitance changes, the resonance point will also shift. At this time, not only will the suppression capability be increased, but it will even lower the gain of the operating frequency band.

[0034] The existing mainstream design scheme is to achieve the frequency band coverage requirement through capacitor arrays. The fixed capacitors in the LC resonant network of the filter are designed as capacitor arrays, and different codewords are configured through the internal SPI to control the switching of the capacitor array to adjust the LC resonance point. This method can solve the frequency coverage problem, but its disadvantage is that the switching of the capacitor array will cause the equivalent Q value of the LC network to decrease, affecting the suppression capability and the flatness of the working frequency band, resulting in the inability to take into account both frequency band coverage and high suppression capability.

[0035] Based on this, the embodiments of the present application provide an image suppression filter structure, an on-chip filter and a radio frequency transceiver, which can suppress the image frequency and minimize the impact on the Q value while ensuring that the image frequency is adjustable. At the same time, the impact of the resonant network on the working frequency band is reduced through a compensation circuit.

[0036] To facilitate understanding of this embodiment, an image suppression filter structure disclosed in an embodiment of the present application is first introduced in detail.

[0037] Figure 1A structural block diagram of an image suppression filter structure provided in an embodiment of the present application, the image suppression filter structure includes: an inductor structure 11, a capacitor switch array 12, a compensation circuit 13, a differential amplifier basic circuit 14 and an RC calibration circuit 15; the RC calibration circuit 15 is respectively connected to the capacitor switch array 12 and the compensation circuit 13; the inductor structure 11 includes a first inductor 111 and a second inductor 112 respectively connected to both ends of the capacitor switch array, and forms a series resonant network 16 with the capacitor switch array 12; the compensation circuit 13 is connected in parallel to one side of the series resonant network 16 to form a parallel structure 17; the parallel structure 17 is arranged in the middle of the symmetrical transistor structure in the differential amplifier basic circuit 14.

[0038] The RC calibration circuit 15 is used to generate a first capacitance adjustment signal and a second capacitance adjustment signal based on the calibrated control codeword to adjust the capacitance values ​​in the capacitance switch array and the compensation circuit respectively, so that the total capacitance value of the two parts of the capacitance remains unchanged under fluctuations of various factors such as different processes, temperatures, and voltages, so as to ensure that the resonance point of the entire network remains unchanged;

[0039] The series resonant network 16 is used to adjust the first capacitance value in the series resonant network 16 according to the first capacitance adjustment signal of the RC calibration circuit 15, so as to adjust the resonance point of the series resonant network 16 to fall within the specified range of the image frequency point, thereby discharging the signal of the image frequency through the low-resistance channel, thereby achieving suppression of the image frequency point;

[0040] The compensation circuit 13 is used to adjust the second capacitance value in the compensation circuit 13 according to the second capacitance adjustment signal of the RC calibration circuit 15, so that the capacitor resonates with the residual inductance of the filter at the operating frequency, so that the series resonant network presents a high impedance state at the operating frequency, reducing the impact on the operating frequency.

[0041] The embodiment of the present application provides an image suppression filter structure that can minimize the impact on the Q value while satisfying the frequency adjustment requirement, and at the same time reduce the impact of the resonant network on the working frequency band through the compensation circuit. Compared with the traditional notch filter structure in the industry, it has better suppression capability and frequency coverage, and the suppression capability is not sensitive to batch fluctuations, and the stability of mass production performance is better.

[0042] The embodiment of the present application also provides an image suppression filter structure, which is implemented on the basis of the previous embodiment. This embodiment specifically describes the specific circuit structure of the filter structure.

[0043] See also Figure 2As shown, the above-mentioned capacitor switch array 12 includes: a first transistor switch Q1, a first capacitor C1 and a second capacitor C2; the gate of the first transistor switch Q1 is connected to the output end of the RC calibration circuit 15, and is used to receive the first capacitor adjustment signal output by the RC calibration circuit 15; the source of the first transistor switch Q1 is connected to one end of the first capacitor C1, and the drain is connected to one end of the second capacitor C2; the other end of the first capacitor C1 is connected to one end of the first inductor L1, and the other end of the second capacitor C2 is connected to one end of the second inductor L2; the other end of the first inductor L1 and the other end of the second inductor L2 are both connected to the compensation circuit 13 and the differential amplifier basic circuit 14.

[0044] Furthermore, the above-mentioned compensation circuit 13 includes: an adjustable capacitor C7; a first end of the adjustable capacitor C7 is connected to the other end of the first inductor L1, a second end of the adjustable capacitor C7 is connected to the other end of the second inductor L2, and a third end of the adjustable capacitor C7 is connected to the RC calibration circuit 15, for receiving a second capacitance adjustment signal output by the RC calibration circuit 15.

[0045] Furthermore, the above-mentioned differential amplifier basic circuit 14 includes: a second transistor switch Q2, a third transistor switch Q3, a fourth transistor switch Q4, a fifth transistor switch Q5, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a third inductor L3 and a fourth inductor L4; the second transistor switch Q2 and the third transistor switch Q3 are open-loop RF amplifier Cascode tubes; the fourth transistor switch Q4 and the fifth transistor switch Q5 are open-loop RF amplifier Gm tubes.

[0046] Furthermore, the parallel structure 17 is disposed in the middle of the symmetrical structure formed by the second transistor switch Q2 , the third transistor switch Q3 , the fourth transistor switch Q4 and the fifth transistor switch Q5 .

[0047] Further, the source of the second transistor switch Q2 is connected to the drain of the fourth transistor switch Q4, and the source of the third transistor switch Q3 is connected to the drain of the fifth transistor switch Q5; the source of the fourth transistor switch Q4 and the source of the fifth transistor switch Q5 are connected to the ground terminal, the gate of the fourth transistor switch Q4 is connected to one end of the third capacitor C3, and the gate of the fifth transistor switch Q5 is connected to one end of the fourth capacitor C4; the drain of the second transistor switch Q2 is respectively connected to one end of the fifth capacitor C5 and one end of the third inductor L3; the drain of the third transistor switch Q3 is respectively connected to one end of the sixth capacitor C6 and one end of the fourth inductor L4; the other ends of the third inductor L3 and the fourth inductor L4 are both connected to the high level terminal; the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are used to receive the RF differential input signal; the other end of the fifth capacitor C5 and the other end of the sixth capacitor C6 are used to output the RF differential output signal; the gate of the second transistor switch Q2 and the gate of the third transistor switch Q3 are used to receive the bias voltage signal.

[0048] Furthermore, one end of the parallel structure 17 is connected to the source of the second transistor switch Q2 and the drain of the fourth transistor switch Q4 ; the other end of the parallel structure 17 is connected to the source of the third transistor switch Q3 and the drain of the fifth transistor switch Q5 .

[0049] Furthermore, all transistor switches Q1 - Q5 in the above-mentioned image rejection filter structure are PMOS field effect transistors.

[0050] like Figure 2 As shown, in this embodiment, the traditional inductor L is split into L1 / L2, connected between the amplifier cascode levels, and the capacitor switch array is formed between L1 / L2, and L1+C+L2 realizes a series resonant network to suppress the signal at the resonance point. The C value is adjusted by Q1 to adjust the capacitance value of C1\C2 to adjust the frequency point, which can cover the target frequency band range. This structure can reduce the number of switches in the capacitor array and reduce the impact on the network Q value. Further, the series resonant network is a low-resistance channel at the resonance point, and is equivalent to a residual inductance at the operating frequency point. The residual inductance will affect the performance of the operating frequency band. Therefore, in this embodiment, next to the existing series resonant network, an adjustable capacitor C7 is connected in parallel as a compensation circuit. By adjusting the capacitance value of C in the compensation circuit, the compensation circuit C resonates with the residual inductance of the filter at the operating frequency point, so that the entire network presents a high impedance state at the operating frequency point, reducing the impact on the operating frequency point.

[0051] The working principle of this circuit structure is as follows:

[0052] Through the LCL series resonant network, a low-impedance channel is presented to the signal at the required image frequency to achieve suppression capability. For upper sideband application scenarios, when the LCL series resonant is at the image point, the network is at the operating frequency (Frf>Fimg, such as Figure 3 As shown in FIG. 1 , a residual inductance is presented. At this time, the parallel adjustable capacitor C7 resonates with the residual inductance, presenting a high impedance to the signal of the operating frequency, reducing the leakage of the signal of the operating frequency from the filter network, thereby reducing the impact on the frequency response of the operating frequency. In another embodiment, both groups of capacitors can be implemented in the form of a capacitor array, and the resonance point of the series resonant network and the resonance point of the compensation network can be dynamically adjusted by configuring different code words to achieve the suppression capability of different frequency points.

[0053] For the entire LC series network, the on-resistance of the capacitor array switches will greatly reduce the network Q value, which reduces the suppression capability of the entire network and increases the impact on the passband. Therefore, the innovative way of LCL in this embodiment can greatly reduce the number of switches, thereby reducing the impact of the capacitor array on the network Q value, while taking into account the two requirements of high suppression capability and adjustable frequency.

[0054] This circuit structure can achieve suppression of different image frequencies by adjusting the capacitance value in the capacitor switch array. Compared with the common image suppression solutions in the industry, it has high suppression capability and little impact on the operating frequency. And through the correction of the RC calibration circuit, the suppression capability can be made less sensitive to fluctuations in process, temperature, voltage and other factors, and the mass production stability is better.

[0055] Based on the above structural embodiment, the embodiment of the present application further provides an on-chip filter, which includes the image suppression filter structure as described in the above embodiment.

[0056] Based on the above filter embodiment, an embodiment of the present application further provides a radio frequency transceiver, and the radio frequency transceiver includes the above on-chip filter.

[0057] The on-chip filter and RF transceiver provided in the embodiments of the present application have the same implementation principles and technical effects as those of the aforementioned structural embodiments. For the sake of brief description, for parts not mentioned in the embodiments of the on-chip filter and RF transceiver, reference may be made to the corresponding contents in the aforementioned structural embodiments.

[0058] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0059] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An image suppression filter structure, characterized in that: The image suppression filter structure includes: an inductor structure, a capacitor switch array, a compensation circuit, a differential amplifier basic circuit and an RC calibration circuit; the RC calibration circuit is connected to the capacitor switch array and the compensation circuit respectively; the inductor structure includes a first inductor and a second inductor respectively connected to two ends of the capacitor switch array, and forms a series resonant network with the capacitor switch array; the compensation circuit is connected in parallel to one side of the series resonant network to form a parallel structure; the parallel structure is arranged in the middle of the symmetrical transistor structure in the differential amplifier basic circuit; The RC calibration circuit is used to generate a first capacitance adjustment signal and a second capacitance adjustment signal based on the calibrated control codeword to adjust the capacitance values ​​in the capacitance switch array and the compensation circuit respectively, so that the total capacitance value of the two parts of the capacitance remains unchanged under fluctuations of various factors such as different processes, temperatures, and voltages, so as to ensure that the resonance point of the entire network remains unchanged; The series resonant network is used to adjust the first capacitance value in the series resonant network according to the first capacitance adjustment signal of the RC calibration circuit, so as to adjust the resonance point of the series resonant network so that it falls within the specified range of the image frequency point, thereby discharging the signal of the image frequency through the low-resistance channel to achieve suppression of the image frequency point; The compensation circuit is used to adjust the second capacitance value in the compensation circuit according to the second capacitance adjustment signal of the RC calibration circuit, so that the capacitance resonates with the residual inductance of the filter at the operating frequency, so that the series resonant network presents a high impedance state at the operating frequency, thereby reducing the impact on the operating frequency.

2. The image suppression filter structure according to claim 1, characterized in that: The capacitor switch array includes: a first transistor switch, a first capacitor and a second capacitor; the gate of the first transistor switch is connected to the output end of the RC calibration circuit, and is used to receive a first capacitor adjustment signal output by the RC calibration circuit; the source of the first transistor switch is connected to one end of the first capacitor, and the drain is connected to one end of the second capacitor; the other end of the first capacitor is connected to one end of the first inductor, and the other end of the second capacitor is connected to one end of the second inductor; the other end of the first inductor and the other end of the second inductor are both connected to the compensation circuit and the differential amplifier basic circuit.

3. The image suppression filter structure according to claim 1, characterized in that: The compensation circuit includes: an adjustable capacitor; a first end of the adjustable capacitor is connected to the other end of the first inductor, a second end of the adjustable capacitor is connected to the other end of the second inductor, and a third end of the adjustable capacitor is connected to the RC calibration circuit, for receiving a second capacitance adjustment signal output by the RC calibration circuit.

4. The image suppression filter structure according to claim 2, characterized in that: The basic circuit of the differential amplifier includes: a second transistor switch, a third transistor switch, a fourth transistor switch, a fifth transistor switch, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a third inductor and a fourth inductor; the second transistor switch and the third transistor switch are open-loop radio frequency amplifier Cascode tubes; the fourth transistor switch and the fifth transistor switch are open-loop radio frequency amplifier Gm tubes.

5. The image suppression filter structure according to claim 4, characterized in that: The parallel structure is arranged in the middle of a symmetrical structure consisting of the second transistor switch, the third transistor switch, the fourth transistor switch and the fifth transistor switch.

6. The image suppression filter structure according to claim 4, characterized in that: The source of the second transistor switch is connected to the drain of the fourth transistor switch, and the source of the third transistor switch is connected to the drain of the fifth transistor switch; the source of the fourth transistor switch and the source of the fifth transistor switch are connected to the ground terminal, the gate of the fourth transistor switch is connected to one end of the third capacitor, and the gate of the fifth transistor switch is connected to one end of the fourth capacitor; the drain of the second transistor switch is respectively connected to one end of the fifth capacitor and one end of the third inductor; the drain of the third transistor switch is respectively connected to one end of the sixth capacitor and one end of the fourth inductor; the other ends of the third inductor and the fourth inductor are both connected to the high level end; the other end of the third capacitor and the other end of the fourth capacitor are used to receive the RF differential input signal; the other end of the fifth capacitor and the other end of the sixth capacitor are used to output the RF differential output signal; the gate of the second transistor switch and the gate of the third transistor switch are used to receive the bias voltage signal.

7. The image suppression filter structure according to claim 6, characterized in that: One end of the parallel structure is connected to the source of the second transistor switch and the drain of the fourth transistor switch; the other end of the parallel structure is connected to the source of the third transistor switch and the drain of the fifth transistor switch.

8. The image suppression filter structure according to claim 4, characterized in that: All transistor switches in the image rejection filter structure are PMOS field effect transistors.

9. An on-chip filter, characterized in that: The on-chip filter comprises an image rejection filter structure as claimed in any one of claims 1-8.

10. A radio frequency transceiver, characterized in that: The radio frequency transceiver comprises the on-chip filter as claimed in claim 9.

Images