Quadrature phase-shifted clock generation with duty cycle correction

Abstract

A method for quadrature phase shift clock generation with duty cycle correction includes delaying a reference clock with a delay circuit to generate a delayed clock, where a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock includes a plurality of states, the plurality of states includes a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock, and the control value is driven to the second edge value during the first state of the delayed clock.

Description

Technical Field

[0001] The present disclosure relates generally to electronic circuits, and more particularly to generating quadrature phase-shifted clocks from a reference clock having an arbitrary input duty cycle. Background Art

[0002] In a switched crystal oscillator circuit, accurately timing the charging and discharging of the crystal nodes at their maximum and minimum values ​​is important for efficient operation and minimizing power consumption. Therefore, it is advantageous to delay the two edges of the delayed clock to be appropriately centered relative to the corresponding high or low phase of the reference clock from which the delayed clock is derived. In addition, the timing of the edges of the delayed clock should not be sensitive to changes in the duty cycle of the reference clock.

[0003] Many high-speed circuits and logic families use double data rate techniques, where both the rising and falling edges of a delayed clock can be used to trigger different events. Additionally, with the use of high-frequency clocks, symmetry between high and low times is desired to minimize constraints on setup and hold timing caused by non-ideal input duty cycles and to allow correct functioning at higher frequencies. Summary of the invention

[0004] As should be appreciated, at least some of the disclosed embodiments include at least the following. In one embodiment, a method for quadrature phase-shifted clock generation with duty cycle correction includes delaying a reference clock with a delay circuit to generate a delayed clock, wherein the delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock includes a plurality of states, the plurality of states including a first state and a second state. In response to a first combination of states of the reference clock and the delayed clock, a first edge value is increased. In response to a second combination of states of the reference clock and the delayed clock, the first edge value is decreased. In response to a third combination of states of the reference clock and the delayed clock, a second edge value is increased. In response to a fourth combination of states of the reference clock and the delayed clock, the second edge value is decreased. During the second state of the delayed clock, the control value is driven to the first edge value. During the first state of the delayed clock, the control value is driven to the second edge value.

[0005] An alternative embodiment of the method for quadrature phase-shifted clock generation with duty cycle correction includes one of the following features or any combination of the following features. In response to changing the corresponding charge on the corresponding capacitor of the first edge value and the second edge value, each of the first edge value and the second edge value is increased and / or decreased. Driving the control value includes multiplexing one of the first edge value and the second edge value, wherein the control value controls a voltage-controlled current source of the delay circuit, the voltage-controlled current source being configured to modify a bias current of a plurality of inverters cascaded between the reference clock and the delayed clock. Driving the control value to the first edge value further includes decoupling the first edge value from the control value during the first state of the reference clock, and driving the control value to the second edge value further includes decoupling the second edge value from the control value during the second state of the reference clock. The first combination of states includes a first state of the reference clock and a second state of the delayed clock. The second combination of states includes a first state of the reference clock and a first state of the delayed clock. The third combination of states includes the second state of the reference clock and the first state of the delayed clock. The fourth combination of states includes a second state of the reference clock and a second state of the delayed clock. The method for quadrature phase-shifted clock generation with duty cycle correction is applied to the delayed clock to generate a second delayed clock and to recover a radio frequency signal using a double data rate clock formed by the delayed clock and the second delayed clock.

[0006] In another embodiment, a device includes a delay circuit configured to generate a delayed clock from a reference clock, wherein a first edge of the delayed clock is delayed by a first delay in response to a first control value, and a second edge of the delayed clock is delayed by a second delay in response to a second control value, and wherein each of the reference clock and the delayed clock includes a plurality of states, the plurality of states including a first state and a second state. A first control circuit is configured to determine the first control value by increasing a first voltage in a first time interval spanning a first edge of the first state of the reference clock and the first edge of the delayed clock and decreasing the first voltage in a second time interval spanning a second edge of the first state of the reference clock and the first edge of the delayed clock. A second control circuit is configured to determine the second control value by increasing a second voltage in a third time interval spanning a first edge of the second state of the reference clock and the second edge of the delayed clock and decreasing the second voltage in a fourth time interval spanning a second edge of the second state of the reference clock and the second edge of the delayed clock.

[0007] Alternative embodiments of the device include one of the following features or any combination of the following features. A first capacitor is configured to store a first charge that can be changed by increasing and / or decreasing the first voltage, and a second capacitor is configured to store a second charge that can be changed by increasing and / or decreasing the second voltage. A multiplexer is configured to couple the first control value to the delay circuit in response to the second state of the delay clock, and to couple the second control value to the delay circuit in response to the first state of the delay clock. A first transmission gate is configured to decouple the first control value from the control input of the delay circuit during the first state of the reference clock, and to decouple the second control value from the control input of the delay circuit during the second state of the reference clock. The delay circuit includes a plurality of inverters cascaded between the reference clock and the delay clock, and at least two of the inverters include bias currents responsive to the first control value and the second control value. The bias current originates from an N-channel field effect transistor, and the first delay and the second delay are each inversely proportional to the control input of the delay circuit. The bias current is derived from a P-channel field effect transistor, and the first delay and the second delay are each proportional to the control input of the delay circuit. The delayed clock from the device is coupled to a second instance of the device to generate a second delayed clock, wherein the delayed clock and the second delayed clock are each duty cycle corrected and combined to form a double data rate clock having twice the frequency of the reference clock.

[0008] In another embodiment, a method for quadrature phase-shifted clock generation with an extended input duty range includes delaying a reference clock with a delay circuit to generate a delayed clock, wherein the delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock includes a plurality of states, the plurality of states including a first state and a second state. A first combination of the respective states of the reference clock and the delayed clock is latched. In response to the first combination of the respective states of the reference clock and the delayed clock, an edge value is decreased. A second combination of the respective states of the reference clock and the delayed clock is latched. In response to the second combination of the respective states of the reference clock and the delayed clock, the edge value is increased. The control value is driven to the edge value during the second state of the delayed clock to center the edge of the delayed clock during the first state of the reference clock.

[0009] An alternative embodiment of the method for quadrature phase-shifted clock generation with an extended input duty range includes one of the following features or any combination of the following features: Increasing the edge value in response to a first signal determined by a logical OR function of a transmission gating signal and an output of a latch, the latch being configured to latch the first combination and the second combination, wherein the transmission gating signal is used to couple the edge value to the control value during the second state of the delayed clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals indicate like elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0011] Figure 1 is a graphical view of timing signals generated by an embodiment of a clock delay circuit from an input reference clock having a 50% input duty cycle.

[0012] Figure 2 is a graphical view of timing signals generated by an embodiment of a clock delay circuit from an input reference clock having a 30% input duty cycle.

[0013] Figure 3 is a schematic diagram of a quadrature phase-shifted clock generation circuit using duty cycle correction according to an embodiment of the present disclosure.

[0014] Figure 4 is to use an input reference clock with a 50% input duty cycle from Figure 3 A graphical view of a timing signal generated by an embodiment.

[0015] Figure 5 is to use an input reference clock with a 50% input duty cycle at Figure 3 A graphical view of the timing signals generated during initialization of an embodiment.

[0016] Figure 6 is to use an input reference clock with a 25% input duty cycle from Figure 3 A graphical view of a timing signal generated by an embodiment.

[0017] Figure 7 is to use an input reference clock with a 75% input duty cycle from Figure 3 A graphical view of a timing signal generated by an embodiment.

[0018] Figure 8 is a schematic diagram of an orthogonal phase-shifted clock generation circuit using ripple masking according to an embodiment of the present disclosure.

[0019] Fig. 9is to use an input reference clock with a 50% input duty cycle from Figure 8 A graphical view of a timing signal generated by an embodiment.

[0020] Fig.10 is a method of utilizing a modified delay line according to an embodiment of the present disclosure Figure 3 Schematic diagram of a quadrature phase-shifted clock generation circuit.

[0021] Fig.11 is to use an input reference clock with a 50% input duty cycle from Fig.10 A graphical view of a timing signal generated by an embodiment.

[0022] Fig.12 is a schematic diagram of a quadrature phase-shifted clock generation circuit modified to control only one edge of a delayed clock according to an embodiment of the present disclosure.

[0023] Fig.13 is to use an input reference clock with a 50% input duty cycle from Fig.12 A graphical view of a timing signal generated by an embodiment.

[0024] Figure 14 to Figure 17 It is a modification of the embodiment according to the present disclosure Fig.12 Schematic diagram of an alternative embodiment of an embodiment of.

[0025] Fig.18 is a flow chart representation of a method for quadrature phase-shifted clock generation with duty cycle correction according to an embodiment of the present disclosure.

[0026] Fig.19 is a flow chart representation of another method for quadrature phase-shifted clock generation with extended input duty range according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Embodiments described herein provide for the centering and alignment of one or both edges of a delayed clock relative to a reference clock from which the delayed clock is derived. Edge alignment is achieved over the entire input duty range of a reference clock by using a feedback loop that adjusts the edge by determining a control value. The control value may be determined based on a combination of charging and discharging a capacitor, by integrating an induced current, or by other methods for determining a measure of the time elapsed between an edge of the delayed clock and the beginning and end of a high state or a low state of a reference clock, from which the delayed clock is derived. By further determining the difference between the elapsed time and the edge of the reference clock, the rising edge of the delayed clock may be adjusted to be centered between the logical high states of the reference clock (or similarly for the corresponding falling edges of the delayed clock and the reference clock). The centering of the edge may be achieved within the limits of the environment and manufacturing tolerances of the device used to achieve the centering of the edge.

[0028] Figure 1 The timing of signals used to control a crystal oscillator ("Xtal") in a switching oscillator topology is shown based on a reference clock having a 50% input duty cycle. At 10, the rising edge of the reference clock ("CLK") is delayed to produce a rising edge of a delayed clock ("CLK_dly") at 12. Similarly, at 14, the falling edge of the clock is delayed to produce a falling edge of the delayed clock at 16. The rising and falling edges of the delayed clock can be used to generate short timing signals "Pump_up" and "Pump_dwn" at the peaks and valleys of the crystal oscillator.

[0029] Compared to Figure 1 , Figure 2 The timing of signals used to control a switched crystal oscillator when the reference clock has a 30% input duty cycle is shown. At 20, the rising edge of the reference clock ("CLK") can be used to generate a delayed clock (CLK_dlyold or CLK_dlynew) at 22 having a rising edge properly centered within the high state of the reference clock. The delayed clock shown by "CLK_dlynew" has a falling edge at 24, compared to the delayed clock shown by "CLK_dlyold" having a falling edge at 26. Unlike the properly aligned edges centered at the valley and the low state of the reference clock "CLK" at 26, the falling edge at 24 is not properly centered at the valley of the crystal oscillator. Therefore, for crystal oscillator control as well as DDR applications and other non-limiting applications, it is advantageous to generate a delayed clock with both the rising and falling edges properly centered within the corresponding high and low states of the reference clock from which the delayed clock is derived.

[0030] Figure 3 An embodiment 30 of a quadrature phase-shifted clock generation circuit utilizing duty cycle correction according to the present disclosure is shown. A reference clock 32 is delayed by a delay circuit 34 to generate a delayed clock 36. An exclusive-NOR (XNOR) logic gate 38 generates a control "Cntrl" signal 40 from the reference clock 32 and the delayed clock 36. The "Cntrl" signal 40 is inverted by an inverter 42 to generate a "Cntrl_b" signal 44. The charging and discharging circuit is configured to modify a ripple voltage 46 and is formed between a power supply voltage 48 and a ground 50. When Cntrl 40 is in a high state, a current source 52 in series with a P-channel field effect transistor (PFET) will increase the ripple voltage 46. Conversely, when Cntrl 40 is in a low state, an N-channel field effect transistor (NFET) 56 in series with a current source 58 will discharge the ripple voltage 46.

[0031] The second branch is formed by a PFET 60 located between current source 52 and current source 62 and an NFET 66 located between current source 64 and current source 58. The purpose of this second branch is to transfer current from current source 52 to current source (e.g., sink) 62 when the ripple voltage 46 is not charged through PFET 54. Conversely, the second branch also transfers current from current source 64 to current source (e.g., sink) 58 when the ripple voltage 46 is not discharged through NFET 56. Embodiment 30 can be operated in ultra-low current applications where control of parasitic effects is important. An implementation based on a current mirror processing device would require a large transistor device size, which has a correspondingly large parasitic effect. Therefore, in order to reduce the non-ideality caused by the larger parasitic effects of the mirror current device, an AC path is provided instead of cutting off current sources 52 and 58.

[0032] The ripple voltage 46 may increase or decrease (e.g., charge or discharge) based on a first, second, third, or fourth combination of the states (e.g., high or low) of the reference clock 32 and the delayed clock 36. In one embodiment, the first combination (the reference clock 32 is high and the delayed clock 36 is low) and the third combination (the reference clock 32 is low and the delayed clock 36 is high) will be decoded by the XNOR gate 38 to drive the Cntrl signal 40 low, thereby activating the PFET 54 to charge the ripple voltage 46 from the current source 52. Conversely, the second combination (the reference clock 32 is high and the delayed clock 36 is high) and the fourth combination (the reference clock 32 is low and the delayed clock 36 is low) will cause the Cntrl signal 40 to be driven high and the ripple voltage 46 to discharge through the NFET 56 and the current source 58.

[0033] In one embodiment, the charging and discharging of the ripple voltage 46 during the high state of the reference clock 32 is used to adjust and center the rising edge of the delayed clock 36 within the high state of the reference clock 32. Therefore, during the high state of the reference clock 32, the ripple voltage 46 is allowed to pass through the transmission gate 70 to the node Vriph 72 and can be stored on the capacitor 74. The transmission gate is enabled to allow the ripple voltage 46 to be coupled to the node 72 through the reference clock 32 and the inverted reference clock ("Clk_"b) 76. Similarly, the charging and discharging of the ripple voltage 46 during the low state of the reference clock 32 is used to adjust and center the falling edge of the delayed clock 36 within the low state of the reference clock 32. Therefore, during the low state of the reference clock 32, the ripple voltage 46 is allowed to pass through the transmission gate 80 to the node Vripl 82 and can be stored on the capacitor 84. The transmission gate is enabled to allow the ripple voltage 46 to be coupled to the node 82 through the reference clock 32 and the inverted reference clock ("Clk_"b) 76. In some embodiments, the values ​​of the ripple voltage 46 (eg, Vriph 72 and Vripl 82 ) that are subsequently stored on the respective capacitors 74 and 84 may be referred to as respective edge values.

[0034] The ripple voltages on nodes Vriph 72 and Vripl 82 are alternately multiplexed and coupled to control voltage 94 through transmission gates 90 and 96. Specifically, when the delayed clock 36 is low (e.g., Clk_dly 36 is high and Clk_dly_b 92 is low), control voltage 94 is driven (by coupling) to the ripple voltage on Vriph node 72. When the delayed clock 36 is high, control voltage 94 is driven (by coupling) to the ripple voltage on Vripl node 82. In doing so, the falling edge of the reference clock 32 is delayed by the delay circuit 34 using the fully integrated (charged) ripple voltage 46 before the falling edge of the delayed clock 36 is generated. Similarly, the rising edge of the reference clock 32 is delayed by the delay circuit 34 using the fully integrated (charged) ripple voltage 46 before the rising edge of the delayed clock 36 is generated.

[0035] In one embodiment, the delay circuit 34 is initialized to provide a zero time delay using a PFET 98 controlled by an enable (“En”) signal 100. The delay circuit 34 may include a plurality of inverters 102 in cascade, the bias currents (e.g., IDS) of which may be derived from respective NFETs 104 connected to ground 50. For example, increasing the control voltage 94 will cause more current to be drawn from the NFETs 104 to ground 50, thereby increasing the transconductance of the transistors comprising each inverter 102 and reducing the transit delay therethrough. In one embodiment, the output of the delay circuit 34 may be further buffered by inverters 106 and 108 to produce the delayed clock 36.

[0036] Figure 4 In the case of a 50% input duty cycle of the reference clock 32, Figure 3 The timing signal generated by the embodiment 30 of the present invention. Specifically, a first combination of the states of the reference clock 32 and the delayed clock 36 is defined as being between a rising edge 110 of the reference clock 32 and a rising edge 112 of the delayed clock 36. A second combination of the states of the reference clock 32 and the delayed clock 36 is defined as being between a rising edge 112 of the delayed clock 36 and a falling edge 114 of the reference clock 32. A third combination of the states of the reference clock 32 and the delayed clock 36 is defined as being between a falling edge 114 of the reference clock 32 and a falling edge 116 of the delayed clock 36. A fourth combination of the states of the reference clock 32 and the delayed clock 36 is defined as being between a falling edge 116 of the delayed clock 36 and a rising edge 118 of the reference clock 32. As shown in FIG. Figure 3 As discussed, the ripple voltage 46 includes both voltage increases and decreases (e.g., charging and discharging) to center both the rising and falling edges of the delayed clock 36. The voltage control 94 is multiplexed between the voltages on the Vriph node 72 and the Vripl node 82 using the delayed clock 36 and the inverted delayed clock 92. For ease of illustration, the coincident traces of the ripple voltage 46 and the control voltage 94 are shown in FIG. Figure 4 and subsequent similar plots so that the behavior of these voltages can be more clearly visualized and understood.

[0037] Continue to refer Figure 3 of Figure 5 In the case of a 50% input duty cycle of the reference clock 32, Figure 3 The timing signal generated during the initialization of embodiment 30. Figure 5As shown in , a rising edge 120 of the reference clock 32 generates a corresponding rising edge 122 of the delayed clock 36 that is initially not fully centered within the high state of the reference clock 32. Similarly, a falling edge 124 of the reference clock 32 generates a corresponding rising edge 126 of the delayed clock 36 that is initially not fully centered within the low state of the reference clock 32. After several cycles, Figure 3 The closed-loop system converges, where the delayed clock 36 has a centered falling edge 130 and a centered rising edge 132. Similarly, Figure 6 and Figure 7 Convergence of the rising and falling edges of the aligned delayed clock 36 is shown for reference clock 32 having input duty cycles of 25% and 75%, respectively.

[0038] Figure 8 An embodiment 140 of a quadrature phase-shifted clock generation circuit with duty cycle correction and ripple masking according to the present disclosure is shown. Fig. 9 Shown from Figure 8 The timing signal generated by embodiment 140. Figure 8 , Fig. 9 , and with Figure 3 and Figure 4 In contrast, a ripple mask is formed in the negative feedback loop in embodiment 140. Specifically, the delivery of the ripple voltage 46 to the multiplexer formed by transmission gates 90 and 96 is buffered in two stages, so that more stability is provided to the delay circuit 34 controlled by the control voltage 94. Specifically, the ripple voltage 46 is delivered to the Vriph node 72 during the high state of the reference clock 32, and then delivered to the node 144 having the storage capacitor 146 through the transmission gate 142 during the low state of the reference clock 32. Similarly, the ripple voltage 46 is delivered to the Vripl node 82 during the low state of the reference clock 32, and then delivered to the node 154 having the storage capacitor 156 through the transmission gate 152 during the high state of the reference clock 32. While the closed-loop system of embodiment 140 ensures proper edge centering, changes in control voltage 94 are preferably masked to ensure predictable delays from rising edge 110 of reference clock 32 to rising edge 112 of delayed clock 36 and from falling edge 114 of reference clock 32 to falling edge 116 of delayed clock 36.

[0039] Fig.10 An embodiment 160 of a quadrature phase-shifted clock generation circuit utilizing duty cycle correction in conjunction with PFET-based delay control in accordance with the present disclosure is shown. Fig.11 Show Fig.10 The corresponding timing signal of embodiment 160 is generated.

[0040] refer to Fig.10 , Fig.11, and with Figure 3 and Figure 4 In contrast, delay circuit 162 is formed by a plurality of inverters 164 in cascade, the bias currents (e.g., IDS) of which may be provided by respective PFETs 166 connected to voltage source 48. For example, reducing control voltage 94 will produce more current from power source 48 to originate from PFETs 166, thereby increasing the transconductance of the transistors comprising each inverter 164 and reducing the propagation delay therethrough. The function of Cntrl signal 40 is also modified by generating an inverted signal Cntrl_b 44 with inverter 43. Inverted signal Cntrl_b 44 now drives the gates of PFET 54 and NFET 56, respectively. In one embodiment, delay circuit 162 is initialized to provide a zero time delay using NFET 168 controlled by inverted enable ("En_b") signal 170.

[0041] Fig.12 An embodiment 180 of a quadrature phase-shifted clock generation circuit modified to control the rising edge of the delayed clock without changing the duty cycle according to an embodiment of the present disclosure is shown. Relative to the previously described embodiments, embodiment 180 is simplified at the expense of controlling only one edge of the delayed clock 36 while still being able to operate within the full input duty cycle range of the reference clock 32. Fig.13 Shown from Fig.12 The timing signal generated by embodiment 180. Fig.12 and Fig.13 , a bi-stable device (e.g., a "flip-flop") 182 captures various combinations of the reference clock 32 and the delayed clock 36 to generate a discharge signal ("Out_Dwn") 184, an inverted discharge signal ("Out_Dwn_b") 186 from an inverter 185, an inverted charge signal ("Out_Up_b") 188 from a NOR gate 189, and a charge signal ("Out_Up") 190 from an inverter 191. Additionally, in one embodiment, the ripple voltage 46 may be stored on a capacitor 192 and initialized by a PFET 194 controlled by an enable signal ("En") 100.

[0042] In the steady state, when both the reference clock 32 and the delayed clock 36 are in a high state, the discharge signal ("Out_Dwn") 184 is in a high state, and the ripple voltage 46 is discharged at a constant current set by the current source 58. When the reference clock 32 transitions to low (at 199), the flip-flop 182 is reset, and the Out_Dwn signal 184 transitions to low. When the reference clock 32 is low and the delayed clock 36 is high, the Out_Up signal 190 goes low, and the ripple voltage 46 then charges at a constant current defined by the current source 52. When the delayed clock 36 is low (between edges 199 and 200), both charging and discharging are disabled, so the ripple voltage 46 is stable, and the transmission gate 195 is open (high value on tg_gate 196, and low value on tg_gate_b 197), thereby shorting the ripple voltage 46 to the control voltage 94. Therefore, the ripple voltage 46 is discharged from the rising edge 198 of the delayed clock 36 to the falling edge 199 of the reference clock 32 , and is charged from the falling edge 199 of the reference clock 32 to the falling edge 200 of the delayed clock 36 . Figure 14 to Figure 17 Alternative embodiments 210, 212, 214 and 216 are shown respectively, wherein embodiment 210 includes Fig.12 In Example 180. Fig.12 Embodiment 180 includes Fig.14 Embodiment 210. Therefore, tg_gate 196 may be driven by Clk_Dly_b 92, and tg_gate_b 197 may be driven by Clk_Dly 36.

[0043] Fig.18 An embodiment 220 of a method for quadrature phase-shifted clock generation with duty cycle correction is shown. Figure 3 , Figure 4 and Fig.18 At 222, the reference clock 32 is delayed (by the delay circuit 34) to produce the delayed clock 36, the delay being proportional to the control value 94. At 224, the first edge value (Vriph 72 associated with the rising edge at 112) is increased based on a first combination of states of the reference clock 32 and the delayed clock 36 (between edges 110 and 112). At 226, the first edge value is decreased based on a second combination of states (between edges 112 and 114). At 228, the second edge value (Vripl 82 associated with the falling edge at 114) is increased based on a third combination of states (between edges 114 and 116). At 230, the second edge value is decreased based on a fourth combination of states (between edges 116 and 118). At 232 , during the second (high) and first (low) respective states of the delayed clock 36 , the control value 94 is driven to the first edge value Vriph 72 and the second edge value Vripl 82 .

[0044] Fig.19 An embodiment 240 of a method for quadrature phase-shifted clock generation with an extended input duty range is shown. Fig.12 , Fig.13 and Fig.19 , at 242, the reference clock 32 is delayed by a delay to produce the delayed clock 36, wherein the delay is proportional to the control value 94. At 244, a first combination of states of the reference clock 32 and the delayed clock 36 is latched (using the flip-flop 182). At 246, the edge value 198 is decreased based on the first combination. At 248, a second combination of states of the reference clock 32 and the delayed clock 36 is latched (using the flip-flop 182). At 250, the edge value 198 is increased based on the second combination. At 252, the control value 94 is driven to the edge value 46 during the second state (low) state of the delayed clock 36 to center the edge 198 of the delayed clock 36 during the first state (high) of the reference clock 32.

[0045] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to a specific embodiment be construed as a key, essential, or requisite feature or element of any or all claims.

[0046] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A method for generating a quadrature phase-shifted clock using duty cycle correction, characterized in that: include: delaying a reference clock with a delay circuit to generate a delayed clock, wherein the delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock includes a plurality of states, the plurality of states including a first state and a second state; In response to a first combination of the states of the reference clock and the delayed clock, increasing a first edge value; decreasing the first edge value in response to a second combination of the states of the reference clock and the delayed clock; responsive to a third combination of the states of the reference clock and the delayed clock, increasing a second edge value; responsive to a fourth combination of the states of the reference clock and the delayed clock, decreasing the second edge value; driving the control value to the first edge value during the second state of the delayed clock; as well as The control value is driven to the second edge value during the first state of the delayed clock.

2. The method according to claim 1, characterized in that Each of the first edge value and the second edge value is increased and / or decreased in response to changing respective charges on respective capacitors of the first edge value and the second edge value.

3. The method according to claim 2, characterized in that Driving the control value includes multiplexing one of the first edge value and the second edge value, wherein the control value controls a voltage-controlled current source of the delay circuit, the voltage-controlled current source being configured to modify a bias current of a plurality of inverters cascaded between the reference clock and the delayed clock.

4. The method according to claim 1, characterized in that: Driving the control value to the first edge value further includes decoupling the first edge value from the control value during the first state of the reference clock, and driving the control value to the second edge value further includes decoupling the second edge value from the control value during the second state of the reference clock.

5. The method according to claim 1, characterized in that The first combination of the states includes the first state of the reference clock and the second state of the delayed clock.

6. The method according to claim 1, characterized in that The second combination of the states includes the first state of the reference clock and the first state of the delayed clock.

7. The method according to claim 1, characterized in that The third combination of the states includes the second state of the reference clock and the first state of the delayed clock.

8. The method according to claim 1, characterized in that: The fourth combination of the states includes the second state of the reference clock and the second state of the delayed clock.

9. A device, characterized in that: include: a delay circuit configured to generate a delayed clock from a reference clock, wherein a first edge of the delayed clock is delayed by a first delay in response to a first control value, and a second edge of the delayed clock is delayed by a second delay in response to a second control value, and wherein each of the reference clock and the delayed clock includes a plurality of states, the plurality of states including a first state and a second state; a first control circuit configured to determine the first control value by increasing a first voltage during a first time interval spanning a first edge of the first state of the reference clock and the first edge of the delayed clock and decreasing the first voltage during a second time interval spanning a second edge of the first state of the reference clock and the first edge of the delayed clock; as well as A second control circuit is configured to determine the second control value by increasing a second voltage during a third time period spanning a first edge of the second state of the reference clock and a second edge of the delayed clock and decreasing the second voltage during a fourth time period spanning a second edge of the second state of the reference clock and the second edge of the delayed clock.

10. A method for generating a quadrature phase-shifted clock using an extended input duty range, characterized in that: include: delaying a reference clock with a delay circuit to generate a delayed clock, wherein the delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock includes a plurality of states, the plurality of states including a first state and a second state; latching a first combination of respective states of the reference clock and the delayed clock; responsive to the first combination of the respective states of the reference clock and the delayed clock, decreasing an edge value; latching a second combination of the respective states of the reference clock and the delayed clock; responsive to the second combination of the respective states of the reference clock and the delayed clock, increasing the edge value; as well as The control value is driven to the edge value during the second state of the delayed clock to center the edge of the delayed clock during the first state of the reference clock.

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