A radio frequency switch

Abstract

The application discloses a radio frequency switch, and adds a parallel inductor in a traditional circuit for matching, can adopt a low Ron structure, realizes low insertion loss and high isolation of the radio frequency switch, and compared with traditional increase of the number of switch tubes, the added inductor reduces a switch area.

Description

TECHNICAL FIELD

[0001] The present application relates to a radio frequency switch, belonging to the field of microwave monolithic integrated circuit. BACKGROUND

[0002] Radio frequency switch is an important component unit of transceiver module in wireless communication system, and its main function is to turn off and switch signals, and it is widely used in phased array communication system, digital controlled attenuator and phase shifter. GaAs PHEMT is a kind of high electron mobility transistor, which is an important control element widely used in communication and measurement fields, and the design of circuit topology using multiple GaAs PHEMT can manufacture radio frequency switch with low loss, high isolation, small size, high reliability and simple control. In the traditional design of radio frequency switch, the number of parallel switch tubes is usually increased to improve the isolation of the switch, but such design method will cause the deterioration of the insertion loss and the increase of the switch area. SUMMARY

[0003] The present application provides a radio frequency switch, which solves the problems disclosed in the background art.

[0004] According to one aspect of the present disclosure, a radio frequency switch is provided, comprising a first transistor, a second transistor, a third transistor, a fourth transistor and an inductor.

[0005] The gate of the first transistor is connected to a first forward control signal, the drain of the first transistor is connected to a radio frequency common port, and the source of the first transistor is connected to a first radio frequency output port, the drain of the second transistor and one end of the inductor.

[0006] The gate of the second transistor is connected to a second forward control signal, and the source of the second transistor is connected to a power supply and ground.

[0007] The gate of the third transistor is connected to the second forward control signal, the drain of the third transistor is connected to the radio frequency common port, and the source of the third transistor is connected to a second radio frequency output port, the drain of the fourth transistor and the other end of the inductor.

[0008] The gate of the fourth transistor is connected to the first forward control signal, and the source of the fourth transistor is connected to the power supply and ground.

[0009] In some embodiments of the present disclosure, a logic circuit is further included, which outputs the second forward control signal and the first forward control signal; the logic circuit comprises a first inverter, a second inverter and a third inverter, the input ends of the first inverter and the second inverter are both externally connected to an initial control signal, the output end of the first inverter outputs the second forward control signal, the output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter outputs the first forward control signal, and the power supply ends of all inverters are connected to a power supply.

[0010] In some embodiments of the present disclosure, the inverter comprises a first PHEMT tube, a second PHEMT tube, a third PHEMT tube, a first adjusting resistor and a second adjusting resistor, the drain of the first PHEMT tube is the input terminal of the inverter, the gate of the first PHEMT tube is connected with the gate of the second PHEMT tube, the source of the first PHEMT tube is connected with the gate of the second PHEMT tube through the first adjusting resistor, the source of the second PHEMT tube is grounded, the drain of the second PHEMT tube is the output terminal of the inverter, the drain of the third PHEMT tube is the power terminal of the inverter, the gate of the third PHEMT tube is connected with the drain of the second PHEMT tube, and the source of the third PHEMT tube is connected with the drain of the second PHEMT tube through the second adjusting resistor.

[0011] In some embodiments of the present disclosure, the second forward control signal and the first forward control signal are a pair of complementary forward control signals.

[0012] In some embodiments of the present disclosure, the gate of the first transistor is connected with the first forward control signal through a first gate resistor, the gate of the second transistor is connected with the second forward control signal through a second gate resistor, the gate of the third transistor is connected with the second forward control signal through a third gate resistor, and the gate of the fourth transistor is connected with the first forward control signal through a fourth gate resistor.

[0013] In some embodiments of the present disclosure, the drain of the first transistor and the drain of the third transistor are both connected with the radio frequency common port through a first direct-current isolation capacitor, the source of the first transistor is connected with the first radio frequency output port through a second direct-current isolation capacitor, the source of the second transistor is connected with the ground through a third direct-current isolation capacitor, the source of the third transistor is connected with the second radio frequency output port through a fourth direct-current isolation capacitor, and the source of the fourth transistor is connected with the ground through a fifth direct-current isolation capacitor.

[0014] In some embodiments of the present disclosure, the source of the second transistor is connected with the power supply through a first bias resistor, and the source of the fourth transistor is connected with the power supply through a second bias resistor.

[0015] In some embodiments of the present disclosure, the transistor is a PHEMT tube.

[0016] The present application has the advantages that: the present application adds a parallel inductor in the traditional circuit for matching, can adopt a low Ron structure, realizes low insertion loss and high isolation of the radio frequency switch, and compared with the traditional method of increasing the number of switch tubes, the increase of the inductor reduces the switch area. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 FIG. 1 is a schematic diagram of a first structure of a radio frequency switch;

[0018] Figure 2 Second structure diagram of the radio frequency switch

[0019] Figure 3 Echo curve diagram; S11 in the figure is input echo loss, and S22 is output echo loss.

[0020] Figure 4 Insertion loss simulation curve diagram; S21 in the figure is insertion loss.

[0021] Figure 5 Isolation simulation curve diagram; S31 and S32 in the figure are isolation. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present disclosure and its application or use. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present disclosure.

[0023] Unless otherwise specified, the relative arrangement, numerical expressions and values of the components and steps set forth in the embodiments do not limit the scope of the present disclosure.

[0024] Meanwhile, it should be understood that the sizes of the various parts shown in the drawings are not drawn in accordance with the actual proportional relationship for the convenience of description.

[0025] The technology, methods and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered as part of the specification when appropriate.

[0026] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0027] It should be noted that similar symbols and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0028] In order to solve the problems existing in the traditional way of improving the isolation of the switch, the present disclosure provides a radio frequency switch, which specifically adds a parallel inductor for matching in the traditional circuit to realize a radio frequency switch with low insertion loss, high isolation and small area.

[0029] Figure 1A schematic diagram of an embodiment of the radio frequency switch of the present disclosure mainly comprises a first transistor SW1, a second transistor SW2, a third transistor SW3, a fourth transistor SW4 and an inductor L.

[0030] The gate of the first transistor SW1 is connected with a first forward control signal V1, the drain of the first transistor SW1 is connected with a radio frequency common port P0, and the source of the first transistor SW1 is connected with a first radio frequency output port P1, the drain of the second transistor SW2 and one end of the inductor L respectively; the gate of the second transistor SW2 is connected with a second forward control signal V2, the source of the second transistor SW2 is connected with a power supply (+5V) and ground respectively; the gate of the third transistor SW3 is connected with the second forward control signal V2, the drain of the third transistor SW3 is connected with the radio frequency common port P0, and the source of the third transistor SW3 is connected with a second radio frequency output port P2, the drain of the fourth transistor SW4 and the other end of the inductor L respectively; the gate of the fourth transistor SW4 is connected with the first forward control signal V1, and the source of the fourth transistor SW4 is connected with the power supply (+5V) and ground respectively.

[0031] It should be noted that the first forward control signal V1 and the second forward control signal V2 can be directly input externally, or can be controlled by using a logic circuit, that is, the switch is controlled by the logic circuit.

[0032] See Figure 2 , the logic circuit comprises a first inverter S1, a second inverter S2 and a third inverter S3, the input ends of the first inverter S1 and the second inverter S2 are both externally connected with an initial control signal VIN, the output end of the first inverter S1 outputs the second forward control signal V2, the output end of the second inverter S2 is connected with the input end of the third inverter S3, the output end of the third inverter S3 outputs the first forward control signal V1, and the power supply ends of all inverters are connected with a power supply (+5V).

[0033] It should be noted that the results of all inverters are consistent, and the inverters include the first PHEMT tube P1, the second PHEMT tube P2, the third PHEMT tube P3, the first adjusting resistor R7 and the second adjusting resistor R8, the drain of the first PHEMT tube P1 is used as the input end of the inverter, the gate of the first PHEMT tube P1 is connected with the gate of the second PHEMT tube P2, the source of the first PHEMT tube P1 is connected with the gate of the second PHEMT tube P2 through the first adjusting resistor R7, the source of the second PHEMT tube P2 is grounded, the drain of the second PHEMT tube P2 is used as the output end of the inverter, the drain of the third PHEMT tube P3 is used as the power supply end of the inverter, the gate of the third PHEMT tube P3 is connected with the drain of the second PHEMT tube P2, and the source of the third PHEMT tube P3 is connected with the drain of the second PHEMT tube P2 through the second adjusting resistor R8; wherein the first adjusting resistor R7 and the second adjusting resistor R8 are used to adjust the static working point.

[0034] It should be noted that the second forward control signal and the first forward control signal are a pair of complementary forward control signals, when the VIN is 0-1V, the first PHEMT tube P1 of the inverter is not conductive, and the output voltage is high level; when the VIN is 3.3-5V, the transistor works in the saturation region, and the output voltage is low level.

[0035] It should be noted that the initial control signal VIN voltage can fluctuate, and can adapt to different input voltage requirements; for example: the initial control signal is a voltage signal of 0-1V, then the first forward control signal V1 is a voltage signal of 0V, and the second forward control signal V2 is a voltage signal of 5V; the initial control signal is a voltage signal of 3.3-5V, then the first forward control signal V1 is a voltage signal of 5V, and the second forward control signal V2 is a voltage signal of 0V.

[0036] It should be noted that in some embodiments, the gate of the first transistor SW1 is connected with the first forward control signal V1 through the first gate resistor R1, the gate of the second transistor SW2 is connected with the second forward control signal V2 through the second gate resistor R2, the gate of the third transistor SW3 is connected with the second forward control signal V2 through the third gate resistor R3, and the gate of the fourth transistor SW4 is connected with the first forward control signal V1 through the fourth gate resistor R4; wherein the gate resistor can adjust the current and voltage in the circuit, protect the circuit and suppress noise.

[0037] It should be noted that in some embodiments, the drains of the first transistor SW1 and the third transistor SW3 are both connected to the RF common port P0 through the first DC blocking capacitor C1, the source of the first transistor SW1 is connected to the first RF output port P1 through the second DC blocking capacitor C2, the source of the second transistor SW2 is connected to ground through the third DC blocking capacitor C3, the source of the third transistor SW3 is connected to the second RF output port P2 through the fourth DC blocking capacitor C4, and the source of the fourth transistor SW4 is connected to ground through the fifth DC blocking capacitor C5. Since a capacitor has a high impedance for RF signals and a low impedance for DC signals, the DC blocking capacitor can prevent DC signals from passing through and only allow RF signals to be transmitted. By blocking DC, the stability and reliability of the RF circuit can be guaranteed.

[0038] It should be noted that DC blocking capacitors generally have a large capacitance value. Therefore, other components in the circuit, except for the DC blocking capacitor, can be integrated inside the chip, while the DC blocking capacitor is distributed separately on the outside.

[0039] It should be noted that in some embodiments, the source of the second transistor SW2 is connected to the power supply (+5V) through the first bias resistor R5, and the source of the fourth transistor SW4 is connected to the power supply (+5V) through the second bias resistor R6; wherein, the bias resistor can adjust the base bias current so that the transistor has a suitable operating point.

[0040] It should be noted that the transistors mentioned above can be PMOS, NMOS, PHEMT, or LDMOS transistors, but here all transistors are PHEMT transistors.

[0041] by Figure 2 For example, when the first positive control signal V1 is at a high potential and the second positive control signal V2 is at a low potential, the first transistor SW1 is in the on state and the second transistor SW2 is in the off state; similarly, the fourth transistor SW4 is in the on state and the third transistor SW3 is in the off state. Therefore, the microwave signal passes through the channel input to the first RF output port P1, while the microwave signal is cut off the channel input to the second RF output port P2, and the switching circuit completes the switching of the signal channel.

[0042] When the first positive control signal V1 is low and the second positive control signal V2 is high, the first transistor SW1 is off and the second transistor SW2 is on; similarly, the fourth transistor SW4 is off and the third transistor SW3 is on. Therefore, microwave signals pass through the channel input to the second RF output port P2, while microwave signals are cut off through the channel input to the first RF output port P1, thus completing the switching of signal channels by the switching circuit.

[0043] It should be noted that in the above-mentioned radio frequency switch, the off-state capacitance and on-state resistance of the transistor itself and the inductance form a switch resonant cavity, and the insertion loss of the switch is only related to the on-state resistance Ron of the series transistor and the resonance network formed by the inductance L and the off-state capacitance. Selecting a large-size transistor can effectively reduce the on-state impedance of the transistor and increase the off-state capacitance, which not only helps to reduce the insertion loss, but also reduces the isolation inductance value and thus reduces the chip area.

[0044] In order to verify the above-mentioned switch, simulation is performed:

[0045] As shown in Figure 3 , a return loss simulation curve of the switch is given, in which the abscissa is the frequency and the ordinate is the return loss value at the frequency. The size of the return value reflects the reflection loss of the signal, and the smaller the value is, the lower the reflection loss is. In 3-6GHz, the return loss of the radio frequency switch is less than-15dB.

[0046] As shown in Figure 4 , an insertion loss simulation curve of the switch circuit is given, in which the abscissa is the frequency and the ordinate is the insertion loss value at the frequency. The size of the insertion loss can reflect the transmission efficiency of the signal, and the larger the value is, the higher the signal transmission efficiency is. The insertion loss of the switch circuit is greater than-0.48dB in 3-6GHz.

[0047] As shown in Figure 5 , a simulation curve of the isolation degree of the switch circuit is given, in which the abscissa is the frequency and the ordinate is the isolation degree value at the frequency. The isolation degree of the switch circuit is less than-30dB.

[0048] From the above simulation, it can be seen that the above-mentioned radio frequency switch adds a parallel inductance for matching, can use a low Ron structure, realizes low insertion loss, high isolation and small area of the radio frequency switch. On the one hand, the radio frequency switch meets the high-power working condition of the communication system, ensures the normal work of the system, on the other hand, only uses positive voltage power supply, is convenient to use, that is, only a set of complementary positive control signals can complete the switching of the signal path.

[0049] The above-mentioned is only the preferred embodiment of the present application, and it should be noted that for ordinary skilled in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should be regarded as the protection scope of the present application.

Claims

1. A radio frequency switch, characterized by The application relates to a power amplifier circuit, which comprises a first transistor, a second transistor, a third transistor, a fourth transistor and an inductor; wherein the transistors are PHEMT tubes. The gate of the first transistor is connected with a first forward control signal, the drain of the first transistor is connected with a radio frequency common port, and the source of the first transistor is connected with a first radio frequency output port, the drain of the second transistor and one end of the inductor respectively. The gate of the second transistor is connected with a second forward control signal, and the source of the second transistor is connected with a power supply and the ground respectively. The gate of the third transistor is connected with the second forward control signal, the drain of the third transistor is connected with the radio frequency common port, and the source of the third transistor is connected with a second radio frequency output port, the drain of the fourth transistor and the other end of the inductor respectively. The gate of the fourth transistor is connected with the first forward control signal, and the source of the fourth transistor is connected with the power supply and the ground respectively. The application further comprises a logic circuit, which outputs the second forward control signal and the first forward control signal; the logic circuit comprises a first inverter, a second inverter and a third inverter, the input ends of the first inverter and the second inverter are externally connected with an initial control signal, the output end of the first inverter outputs the second forward control signal, the output end of the second inverter is connected with the input end of the third inverter, the output end of the third inverter outputs the first forward control signal, and the power supply ends of all the inverters are connected with the power supply. The inverter comprises a first PHEMT tube, a second PHEMT tube, a third PHEMT tube, a first adjusting resistor and a second adjusting resistor, the drain of the first PHEMT tube is used as the input end of the inverter, the gate of the first PHEMT tube is connected with the gate of the second PHEMT tube, the source of the first PHEMT tube is connected with the gate of the second PHEMT tube through the first adjusting resistor, the source of the second PHEMT tube is grounded, the drain of the second PHEMT tube is used as the output end of the inverter, the drain of the third PHEMT tube is used as the power supply end of the inverter, the gate of the third PHEMT tube is connected with the drain of the second PHEMT tube, and the source of the third PHEMT tube is connected with the drain of the second PHEMT tube through the second adjusting resistor.

2. The radio frequency switch of claim 1, wherein, The second forward control signal and the first forward control signal are a pair of complementary forward control signals.

3. The radio frequency switch of claim 1, wherein, The gate of the first transistor is connected with the first forward control signal through a first gate resistor, the gate of the second transistor is connected with the second forward control signal through a second gate resistor, the gate of the third transistor is connected with the second forward control signal through a third gate resistor, and the gate of the fourth transistor is connected with the first forward control signal through a fourth gate resistor.

4. The radio frequency switch of claim 1, wherein, The drain of the first transistor and the drain of the third transistor are connected with the radio frequency common port through a first direct-current isolation capacitor, the source of the first transistor is connected with the first radio frequency output port through a second direct-current isolation capacitor, the source of the second transistor is connected with the ground through a third direct-current isolation capacitor, the source of the third transistor is connected with the second radio frequency output port through a fourth direct-current isolation capacitor, and the source of the fourth transistor is connected with the ground through a fifth direct-current isolation capacitor.

5. The radio frequency switch of claim 1, wherein, The source of the second transistor is connected with the power supply through a first bias resistor, and the source of the fourth transistor is connected with the power supply through a second bias resistor.

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