Digital phase-locked loop and video signal sampling method

Abstract

The invention discloses a digital phase-locked loop and a video signal sampling method, and belongs to the technical field of microelectronics. The digital phase-locked loop comprises: a phase discriminator, a first input end of which inputs a video signal, a second input end of which inputs a feedback signal, and which obtains a phase error signal based on the video signal and the feedback signal; the first input end of the analysis module is electrically connected with the output end of the phase discriminator, and the analysis module is used for analyzing the phase error signal to obtain a pixel clock signal; the self-adaptive parameter controller is electrically connected with the second input end of the analysis module, and self-adaptively adjusts the configuration parameters of the analysis module based on the error range of the phase error signal; the input end of the feedback frequency dividing circuit is electrically connected with the output end of the analysis module, the output end of the feedback frequency dividing circuit is electrically connected with the second input end of the phase discriminator, and the feedback frequency dividing circuit is used for performing frequency dividing processing on the pixel clock signal to obtain a feedback signal. The digital phase-locked loop has good phase following performance and can improve the accuracy of video signal acquisition.

Description

Technical Field

[0001] The invention relates to the field of microelectronic technology, and in particular to a digital phase-locked loop and a video signal sampling method. Background Art

[0002] In video signal transmission, the video receiver uses a phase-locked loop to track and lock the line frequency of the video signal according to the synchronization information in the video signal, and then samples the video signal with the locked clock. However, jitter is introduced into the video signal during transmission. In order to ensure accurate sampling of pixel data, the pixel clock recovered from the video signal is required to quickly follow the changes in the signal.

[0003] At present, the line frequency of the video signal is tracked and locked by a phase-locked loop, which includes an analog phase-locked loop and a digital phase-locked loop. Since the frequency of the phase-locked loop reference clock (horizontal synchronization signal) is very low, usually in the range of 10KHz to 100KHz, the multiplication factor is large, and the cost of tracking and locking by the analog phase-locked loop is high, so digital phase-locked loops are widely used in related fields. However, the current digital phase-locked loop will not start pixel sampling until it is locked, and during the sampling process, the clock frequency remains basically unchanged, so it is impossible to accurately sample the pixel data. Summary of the invention

[0004] To this end, the present invention provides a digital phase-locked loop and a video signal sampling method to solve the problem in the prior art that inaccurate pixel data sampling is caused by keeping the clock frequency unchanged during the sampling process.

[0005] In order to achieve the above object, the first aspect of the present invention provides a digital phase-locked loop, comprising:

[0006] A phase detector, wherein a first input terminal is used to input a video signal, and a second input terminal is used to input a feedback signal, and the phase detector obtains a phase error signal based on the video signal and the feedback signal;

[0007] An analysis module, a first input end of which is electrically connected to the output end of the phase detector, and is used to analyze the phase error signal to obtain a pixel clock signal;

[0008] an adaptive parameter controller, electrically connected to the second input terminal of the analysis module, and adaptively adjusting the configuration parameters of the analysis module based on the error range of the phase error signal;

[0009] A feedback frequency dividing circuit, wherein the input end of the feedback frequency dividing circuit is electrically connected to the output end of the analysis module, the output end of the feedback frequency dividing circuit is electrically connected to the second input end of the phase detector, and the feedback frequency dividing circuit performs frequency division processing on the pixel clock signal to obtain a feedback signal.

[0010] Wherein, the analysis module includes:

[0011] An error expander, wherein a first input terminal is electrically connected to the output terminal of the phase detector, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal and a pixel clock signal, and the error expander expands the phase error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain an expanded error signal;

[0012] A digital converter, wherein a first input terminal is electrically connected to the output terminal of the error expander, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal and a pixel clock signal, and the digital converter converts the expanded error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain a digital error signal;

[0013] A digital filter, wherein a first input terminal is electrically connected to an output terminal of the digital converter, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal and a pixel clock signal, wherein the digital filter performs filtering processing on the digital error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain a frequency control code;

[0014] A digitally controlled oscillator, wherein a first input terminal is electrically connected to an output terminal of the digital filter, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal, wherein the digitally controlled oscillator generates the pixel clock signal based on the frequency control code, the configuration parameter and the low-frequency reference clock signal;

[0015] The configuration parameters of the adaptive parameter controller include the error expander configuration parameters, the digital converter configuration parameters, the digital filter configuration parameters, and the digitally controlled oscillator configuration parameters.

[0016] Wherein, the error expander comprises:

[0017] A delay unit, used for extending the width of the phase error signal;

[0018] The expansion unit is used to expand the frequency width of the phase error signal to obtain a first expanded error signal corresponding to a low-frequency clock domain and a second expanded error signal corresponding to a high-frequency clock domain.

[0019] Wherein, the digital converter comprises:

[0020] A coarse time-to-digital converter, used for converting the length information of the first extended error signal into a first sequence;

[0021] A fine-tuning time-to-digital converter is used to convert the length information of the second extended error signal into a second sequence.

[0022] Wherein, the phase error signal includes the phase error width and the phase error sign;

[0023] When the phase error width is lower than a first threshold, the digital converter performs exponential amplification;

[0024] When the phase error width is higher than a second threshold, the digital converter amplifies at a fixed ratio.

[0025] Wherein, the digital filter comprises:

[0026] a coarse adjustment integrator, used for integrating the first sequence to obtain a first integrated sequence;

[0027] A coarse tuning filter, used for filtering the first sequence and the first integrated sequence to obtain a first filtered signal;

[0028] A fine tuning integrator, used for integrating the second sequence to obtain a second integrated sequence;

[0029] A fine tuning filter is used to obtain a second filtered signal from the second sequence and the second integrated sequence;

[0030] A loop filter is used for the first filtered signal and the second filtered signal to obtain a total filtered signal and the frequency control code corresponding to the total filtered signal.

[0031] Wherein, the phase detector comprises:

[0032] A first synchronous shift rising edge detection module, whose input end serves as a first input end of the phase detector and is used to detect a rising edge of the video signal;

[0033] A second synchronous shift rising edge detection module, whose input end serves as a second input end of the phase detector and is used to detect the rising edge of the feedback signal;

[0034] A phase detection state transfer module, wherein a first input end is electrically connected to the first synchronous shift rising edge detection module, and a second input end is electrically connected to the second synchronous shift rising edge detection module, and is used to determine the phase error width and phase state of the video signal and the feedback signal according to the rising edge of the video signal and the rising edge of the feedback signal, wherein the phase state includes an advanced state and a lagging state.

[0035] In a second aspect, the present invention provides a video signal sampling method, comprising:

[0036] Receive a current frame video signal and a feedback signal; wherein the feedback signal is a signal obtained by frequency division processing of a pixel clock signal analyzed from a previous frame video signal;

[0037] Using the digital phase-locked loop provided by the embodiment of the present invention, determining the current frame pixel clock signal based on the current frame video signal and the feedback signal, and tracking and locking the current frame pixel clock signal;

[0038] Pixel data in the video signal is collected according to the current frame pixel clock signal.

[0039] Wherein, the configuration parameters include multiple groups of configuration parameters, and each group of configuration parameters corresponds to a phase error range;

[0040] The configuration parameters are determined by the following steps:

[0041] Based on the horizontal synchronization signal in the video signal and the reference clock signal, the phase error data is evaluated to determine the jitter range of the video signal;

[0042] Based on the jitter range of the video signal, a plurality of groups of the configuration parameters are set accordingly.

[0043] The configuration parameters include first configuration parameters and multiple groups of second configuration parameters. The first configuration parameters are used to set the parameters of the analysis module before tracking and locking; the second configuration parameters are used to set the parameters of the analysis module after tracking and locking.

[0044] The present invention has the following advantages:

[0045] The digital phase-locked loop provided by the present invention has a phase detector that obtains a phase error signal based on the video signal and the feedback signal, and an analysis module analyzes the phase error signal to obtain a pixel clock signal; moreover, when the analysis module analyzes the phase error signal, an adaptive parameter controller adaptively adjusts configuration parameters, thereby accurately analyzing the pixel clock signal from the video signal, and a feedback frequency division circuit performs frequency division processing on the pixel clock signal to obtain a feedback signal, thereby allowing the pixel clock signal to quickly follow the phase change of the video signal, that is, to have good phase followability, and therefore, the video signal collected based on the pixel clock signal is more accurate, and moreover, the adaptive parameter controller adaptively adjusts the configuration parameters, and the parameter setting is flexible and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0047] Figure 1 A schematic diagram of the structure of a digital phase-locked loop provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of the structure of a phase detector provided by an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of the structure of a digital converter provided by an embodiment of the present invention;

[0050] Figure 4 A schematic diagram of the structure of a digital filter provided by an embodiment of the present invention;

[0051] Figure 5 The present invention provides a flowchart of a video signal sampling method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0053] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0054] The terms used in the present invention are only used to describe specific embodiments and are not intended to limit the present invention. As used in the present invention, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0055] When the terms “comprising” and / or “made of…” are used in the present invention, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used in the present invention have the same meaning as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as having an idealized or overly formal meaning unless the present invention clearly defines it as such.

[0057] In a first aspect, an embodiment of the present invention provides a digital phase-locked loop.

[0058] Figure 1 A schematic diagram of the structure of a digital phase-locked loop provided by an embodiment of the present invention.

[0059] like Figure 1As shown, an embodiment of the present invention provides a digital phase-locked loop comprising:

[0060] Phase detector 1 has a first input terminal for inputting a video signal HSYNC, and a second input terminal for inputting a feedback signal HSYNC_FB. Phase detector 1 obtains a phase error signal based on the video signal and the feedback signal.

[0061] The video signal includes a line synchronization signal, and the feedback signal is used as a reference signal. By comparing the line synchronization signal and the reference signal, a phase error signal of the line synchronization signal relative to the reference signal can be determined. The phase error signal includes a phase error signal width and a phase error state SIGN. The phase error state includes an advance state and a lag state. The advance state refers to the phase advance of the input video signal relative to the feedback signal, and the lag state refers to the phase lag of the input video signal relative to the feedback signal.

[0062] In some embodiments, the feedback signal is a signal recovered from the video signal, and the feedback signal recovered from the video signal is used as a reference signal to determine the phase error of the video signal.

[0063] The analysis module 2 has a first input terminal electrically connected to the output terminal of the phase detector 1 and is used to analyze the phase error signal to obtain a pixel clock signal.

[0064] The analysis module 2 analyzes the phase error signal output by the phase detector 1 to obtain the pixel clock signal CLK_PIXEL.

[0065] The adaptive parameter controller (ADAPTIVE_CFG) 3 is electrically connected to the second input terminal of the analysis module 2, and adaptively adjusts the configuration parameters of the analysis module based on the error range of the phase error signal.

[0066] The embodiment of the present invention adjusts the configuration parameters of the analysis module according to the phase error range.

[0067] Feedback frequency dividing circuit (CLKDIV) 4, the input end of the feedback frequency dividing circuit is electrically connected to the output end of the analysis module 2, the output end of the feedback frequency dividing circuit is electrically connected to the second input end of the phase detector 1, and the feedback frequency dividing circuit 4 performs frequency division processing on the pixel clock signal to obtain a feedback signal.

[0068] In the embodiment of the present invention, the pixel clock signal is a high-speed clock signal. The feedback frequency division circuit 4 performs frequency division processing on the pixel clock signal to obtain a reference signal having a frequency consistent with the horizontal synchronization signal.

[0069] In some embodiments, the feedback frequency division circuit uses the number of row pixels as a frequency division coefficient to perform frequency division processing on the pixel clock signal to obtain a feedback signal.

[0070] In some embodiments, the analysis module 2 includes:

[0071] The error expander (DPERRP) 21 has a first input terminal electrically connected to the output terminal of the phase detector 1, a second input terminal electrically connected to the adaptive parameter controller 3, and a third input terminal inputting a low-frequency reference clock signal and a pixel clock signal. The error expander 21 expands the phase error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain an expanded error signal PHASE_ERR.

[0072] In this embodiment, the error expander 21 can expand the phase error signal in the low-frequency clock domain and the high-frequency clock domain respectively, and the expansion ratio is determined by the configuration parameters of the adaptive parameter controller 3 .

[0073] A digital converter (TDC) 22 has a first input terminal electrically connected to the output terminal of the error expander 21, a second input terminal electrically connected to the adaptive parameter controller 3, and a third input terminal inputting a low-frequency reference clock signal and a pixel clock signal. The digital converter 22 converts the expanded error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain a digital error signal.

[0074] In the embodiment of the present invention, the digital converter 22 converts the error width signal of the low-frequency clock domain and the error width signal of the high-frequency clock domain respectively to obtain a digital signal.

[0075] In some embodiments, the phase error signal includes a phase error width and a phase error sign. When the digital converter 22 converts the error width into a digital signal, if the phase error width is lower than a first threshold, the digital converter performs exponential amplification; if the phase error width is higher than a second threshold, the digital converter amplifies at a fixed ratio. The first threshold is smaller than the second threshold.

[0076] In the embodiment of the present invention, the first threshold, the second threshold and the amplification level can be configured by the adaptive parameter controller 3. This embodiment does not limit the specific values ​​of the first threshold, the second threshold and the fixed ratio.

[0077] A digital filter (DFILTER) 23 has a first input terminal electrically connected to the output terminal of the digital converter 22, a second input terminal electrically connected to the adaptive parameter controller 3, and a third input terminal inputting a low-frequency reference clock signal and a pixel clock signal. The digital filter 23 performs filtering processing on the digital error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain a frequency control code. The filtering parameters of the digital filter 23 are adaptively configured by the adaptive parameter controller 3.

[0078] In the embodiment of the present invention, the digital filter 23 includes a coarse adjustment filter and a fine adjustment filter, wherein the coarse adjustment filter integrates and filters the error digital signal of the low-frequency clock to obtain a first filtered signal, and the fine adjustment filter integrates and filters the error digital signal of the high-frequency clock domain to obtain a second filtered signal, and then the first filtered signal and the second filtered signal are combined to obtain a frequency control code. The frequency control code includes an integer and a decimal part.

[0079] A digital controlled oscillator (DCO) 24 has a first input terminal electrically connected to the output terminal of the digital filter 23, a second input terminal electrically connected to the adaptive parameter controller 3, and a third input terminal inputting a low-frequency reference clock signal. The digital controlled oscillator 24 generates a pixel clock signal based on the frequency control code, the configuration parameters and the low-frequency reference clock signal. The configuration parameters are adaptively configured by the adaptive parameter controller 3.

[0080] The configuration parameters of the adaptive parameter controller 3 include error expander configuration parameters, digitizer configuration parameters, digital filter configuration parameters, and digital controlled oscillator configuration parameters. The adaptive parameter controller 3 sets different configuration parameters according to the error range of the phase error signal, and then adaptively adjusts the expander configuration parameters, digitizer configuration parameters, digital filter configuration parameters, and digital controlled oscillator configuration parameters in real time according to the phase error range, so that the sampling phase follows the phase of the input video signal.

[0081] It should be noted that, in the embodiment of the present invention, the low-frequency reference clock may be provided by a clock unit of an external device.

[0082] Figure 2 Schematic diagram of the structure of a phase detector provided by an embodiment of the present invention. Figure 2 As shown, the phase detector is a digital phase detector, which includes:

[0083] The first synchronous shift rising edge detection module 11 has an input end which is a first input end of a phase detector and is used to detect a rising edge of a video signal.

[0084] The second synchronous shift rising edge detection module 12 has an input terminal which is the second input terminal of the phase detector and is used to detect the rising edge of the feedback signal.

[0085] The phase detection state transfer module 13 has a first input end electrically connected to the first synchronous shift rising edge detection module 11, and a second input end electrically connected to the second synchronous shift rising edge detection module 12, and is used to determine the phase error width and state between the video signal and the feedback signal according to the rising edge of the video signal and the rising edge of the feedback signal, wherein the state includes an advanced state and a lagging state.

[0086] In the embodiment of the present invention, the phase detection state transfer module 13 obtains the phase error signal of the current cycle according to the rising edge of the video signal obtained by the first synchronous shift rising edge detection module 11 and the rising edge of the feedback signal () obtained by the second synchronous shift rising edge detection module 12. The first synchronous shift rising edge detection module 11, the second synchronous shift rising edge detection module 12 and the phase detection state transfer module 13 in the phase detector work synchronously under the high-frequency clock of the system, which greatly improves the accuracy of the phase detector output and can effectively eliminate the phenomenon of phase detection burrs.

[0087] In some embodiments, the error expander 21 adopts two-stage expansion, that is, the error expander 21 includes:

[0088] The delay unit 211 is used to expand the width of the phase error signal. The number of the delay units 211 can be configured by the adaptive parameter controller 3 .

[0089] The expansion unit 212 is used to expand the frequency width of the phase error signal to obtain a first expanded error signal ERR_CKL corresponding to the low-frequency clock domain and a second expanded error signal ERR_CKH corresponding to the high-frequency clock domain.

[0090] In the embodiment of the present invention, the expansion unit 212 uses the low-frequency clock domain and the high-frequency clock domain for expansion respectively, the error signal after expansion output by the low-frequency clock domain is ERR_CKL, and the error signal after expansion output by the high-frequency clock domain is ERR_CKH. The number of extended clock cycles can be configured by the adaptive parameter controller 3.

[0091] Figure 3 FIG. 1 is a schematic diagram of a digital converter provided by an embodiment of the present invention. Figure 3 As shown, the digital converter includes a multi-stage shift register 221 cascaded in sequence, and the multi-stage shift register 221 is used to adaptively exponentially amplify the phase error information, and the maximum amplification level can be configured by the adaptive parameter controller 3.

[0092] In some embodiments, the digital converter 22 includes a coarse time digital converter and a fine time digital converter, wherein the phase error signal input to the coarse time digital converter is a first extended error signal PHASE_ERR in the low-frequency clock domain, which is used to convert the length information of the first extended error signal into the first sequence X ckl The phase error signal input by the fine-tuning time digital converter is a second extended error signal in the high-frequency clock domain, which is used to convert the length information of the second extended error signal into a second sequence X ckh .

[0093] The maximum values ​​of the first sequence and the second sequence can be configured by the adaptive parameter controller 3 .

[0094] The coarse time digital converter is used to convert the length information of the first extended error signal into a first sequence X ckl The following takes the maximum value of 15 as an example.

[0095] When the sign signal is 0, the first sequence X ckl is a sequence of positive integers.

[0096]

[0097] When the sign signal is 1, the first sequence X ckl is a sequence of negative integers.

[0098]

[0099] The structure of the fine time digital converter is similar to that of the coarse time digital converter, except that when ERR_CKL is at a high level, the shift register 221 in the fine time digital converter is reset. The fine time digital converter converts the high frequency clock domain ERR_CKH length information into the second sequence X ckh . Second sequence X ck The maximum value of can be configured by adaptive parameter controller 3.

[0100] The following takes the maximum value of 15 as an example for description.

[0101] When the sign signal is 0, the second sequence X ckh is a sequence of positive integers.

[0102]

[0103] When the sign signal is 1, the second sequence X ckh is a sequence of negative integers.

[0104]

[0105] The PHASE_ERR output by the error expander 21 is converted by the digital converter 22 to obtain a digital error signal. The digital error signal ERR_VALUE includes a first sequence X ckl and the second sequence X ck , and then sent to the digital filter 23 for coarse adjustment integration and fine adjustment integration respectively.

[0106] Figure 4 A schematic diagram of the structure of a digital filter provided by an embodiment of the present invention. Figure 4 As shown, the digital filter 23 provided in the embodiment of the present invention includes:

[0107] The coarse adjustment integrator 231 is used to adjust the first sequence Xckl The first integral sequence is obtained by integrating. ckl (n), output the first integral sequence Y ckl , the first integral sequence Y ckl The time domain expression of is:

[0108] Y ckl (n) = X ckl (n)+Y ckl (n-1)

[0109] The coarse tuning filter 232 is used to filter the first sequence and the first integrated sequence to obtain a first filtered signal.

[0110] The output of the coarse filter 232 is:

[0111] Sum ckl (n) = (X ckl (n)+Y ckl (n-1))*Gain2+X ckl (n)*Gain1

[0112] The fine tuning integrator 233 is used to adjust the second sequence X ckh Perform integration to obtain a second integral sequence.

[0113] The input of the fine integrator is the second sequence X ckh (n), output the second integral sequence Y ckh , the second integral sequence Y ckh The time domain expression of is:

[0114] Y ckh (n) = X ckh (n)+Y ckl (n-1)

[0115] The fine tuning filter 234 is used to obtain a second filtered signal for the second sequence and the second integrated sequence.

[0116] The output of the fine tuning filter 234 is:

[0117] Sum ckh (n) = (X ckh (n)+Y ckl (n-1))*Gain4+X ckh (n)*Gain3

[0118] The loop filter 235 is used for the first filtered signal and the second filtered signal to obtain a total filtered signal and a frequency control code corresponding to the total filtered signal.

[0119] The total output DCO_CTRL of the loop filter 235 includes a total filtered signal and a corresponding frequency control code. The total filtered signal can be expressed as:

[0120] Sum(n)=Sum ckl (n)+Sum ckh (n)

[0121] The frequency control code corresponding to the total filtered signal can be expressed as:

[0122] G(n)=Sum(n)*2 -n +DM

[0123] Among them, DM and 2 -n A configurable constant.

[0124] When X ckl When (n) is a non-zero sequence, X ckh (n) is 0, the output of the fine-tuning part is:

[0125] Sum ckh (n) = Y ckh (n-1)*Gain4

[0126] Y ckh (n) = Y ckl (n-1)

[0127] Integrator Y ckh (n-1) remains unchanged, Sum ckh (n) is a constant, and the output of the filter only changes with X ckl (n) changes. Similarly, when X ckl When (n) is 0, Sum ckl (n) remains unchanged, the output of the filter only changes with X ckh (n)Change.

[0128] In this embodiment, the gain of each of the feed-forward path of the coarse adjustment sequence and the feed-forward path of the fine adjustment sequence is configurable.

[0129] like Figure 2 As shown, the digital phase-locked loop also includes:

[0130] The selector (MUX) 5 has a first input terminal for receiving the feedback signal HSYNC_FB and a second input terminal for receiving the reference clock signal CLK_REF. The selector is used to select the feedback signal and the reference clock signal.

[0131] The digital phase-locked loop provided by the embodiment of the present invention is implemented in a digital manner, has a small size and low cost.

[0132] In the digital phase-locked loop provided by the embodiment of the present invention, the phase detector obtains a phase error signal based on a video signal and a feedback signal, and the analysis module analyzes the phase error signal to obtain a pixel clock signal; moreover, when the analysis module analyzes the phase error signal, the adaptive parameter controller adaptively adjusts the configuration parameters, thereby accurately analyzing the pixel clock signal from the video signal, and the feedback frequency division circuit performs frequency division processing on the pixel clock signal to obtain a feedback signal, thereby allowing the pixel clock signal to quickly follow the phase change of the video signal, that is, the pixel clock signal has better phase tracking performance, and therefore, the video signal collected based on the pixel clock signal is more accurate, and moreover, the adaptive parameter controller adaptively adjusts the configuration parameters, and the parameter setting is flexible and easy to implement.

[0133] In a second aspect, an embodiment of the present invention further provides a video signal sampling method.

[0134] Figure 5 A flowchart of a video signal sampling method provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the video signal sampling method provided by the embodiment of the present invention includes:

[0135] Step S501, receiving a current frame video signal and a feedback signal; wherein the feedback signal is a signal obtained by frequency division processing of a pixel clock signal analyzed from a previous frame video signal.

[0136] Step S502: using the digital phase-locked loop provided by the embodiment of the present invention, determine the pixel clock signal of the current frame based on the video signal of the current frame and the feedback signal, and track and lock the pixel clock signal of the current frame.

[0137] Step S503: collecting pixel data in the video signal according to the current frame pixel clock signal.

[0138] In some embodiments, the configuration parameters include multiple groups of configuration parameters, and each group of configuration parameters corresponds to a phase error range.

[0139] The configuration parameters are determined by the following steps: based on the line synchronization signal and the reference clock signal in the video signal, the phase error data is evaluated to determine the jitter range of the video signal; based on the jitter range of the video signal, a plurality of groups of configuration parameters are correspondingly set.

[0140] In some embodiments, the configuration parameters include first configuration parameters and multiple groups of second configuration parameters, the first configuration parameters are used to set the parameters of the analysis module before tracking and locking; the second configuration parameters are used to set the parameters of the analysis module after tracking and locking.

[0141] In this embodiment, the operation of the phase-locked loop includes two major stages, the first stage is the initialization stage to the (frequency) tracking and locking stage, and the second stage is the normal working stage after tracking and locking. In the initialization stage, the error digital signal generated by the digital converter has a large fluctuation range, and the first configuration parameter is set to achieve rapid locking of the phase-locked loop. In the normal working stage, the phase error range is small, and one or more second configuration parameters are set to fine-tune the configuration parameters to improve the phase tracking performance.

[0142] For example, in the initialization stage, the horizontal synchronization signal and the reference clock signal are input into the phase detector; the parameters of the error expander, the digital converter, the digital filter and the digitally controlled oscillator are configured in the adaptive parameter controller; the phase error data output by the digital converter is counted, the jitter range of the video signal is evaluated, and the first configuration parameter is set based on the jitter range.

[0143] In the normal working stage, the horizontal synchronization signal and the reference clock signal are input into the phase detector; the parameters of the error expander, the digital converter, the digital filter and the digital control oscillator are configured in the adaptive parameter controller; the phase error data output by the digital converter is counted, the jitter range of the video signal is evaluated, and the second configuration parameter is set based on the jitter range. In order to further optimize the phase tracking performance, the error range is subdivided into several segments, each of which corresponds to a set of second configuration parameters.

[0144] When sampling the video signal, the video signal and the feedback signal are input into the phase detector, and the parameters in the analysis module are configured using the first configuration parameters before the latch is tracked and locked. After the latch is locked, a set of second configuration parameters are selected according to the phase error to configure the parameters in the analysis module.

[0145] The video signal sampling method provided in an embodiment of the present invention uses the phase-locked loop provided in this embodiment to track and lock the line frequency of the video signal, and then samples the video signal with the locked pixel clock, and adjusts (optimizes) the parameters of the latch in real time according to the jitter of the input video signal, so that the pixel clock can quickly follow the phase change of the video signal, thereby making the video signal acquisition more accurate.

[0146] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0147] It should be noted that all modules involved in this embodiment are logic modules. In practical applications, a logic unit may be a physical unit, or a part of a physical unit, or may be implemented as a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0148] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the invented method described above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0149] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0150] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.

[0151] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A digital phase-locked loop, characterized in that: include: A phase detector, wherein a first input terminal is used to input a video signal, and a second input terminal is used to input a feedback signal, and the phase detector obtains a phase error signal based on the video signal and the feedback signal; An analysis module, a first input end of which is electrically connected to the output end of the phase detector, and is used to analyze the phase error signal to obtain a pixel clock signal; an adaptive parameter controller, electrically connected to the second input terminal of the analysis module, and adaptively adjusting the configuration parameters of the analysis module based on the error range of the phase error signal; A feedback frequency dividing circuit, wherein the input end of the feedback frequency dividing circuit is electrically connected to the output end of the analysis module, the output end of the feedback frequency dividing circuit is electrically connected to the second input end of the phase detector, and the feedback frequency dividing circuit performs frequency division processing on the pixel clock signal to obtain a feedback signal.

2. The digital phase-locked loop according to claim 1, characterized in that: The analysis module comprises: An error expander, wherein a first input terminal is electrically connected to the output terminal of the phase detector, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal and a pixel clock signal, and the error expander expands the phase error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain an expanded error signal; A digital converter, wherein a first input terminal is electrically connected to the output terminal of the error expander, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal and a pixel clock signal, and the digital converter converts the expanded error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain a digital error signal; A digital filter, wherein a first input terminal is electrically connected to an output terminal of the digital converter, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal and a pixel clock signal, wherein the digital filter performs filtering processing on the digital error signal based on the low-frequency reference clock signal, the pixel clock signal and the configuration parameters to obtain a frequency control code; A digitally controlled oscillator, wherein a first input terminal is electrically connected to an output terminal of the digital filter, a second input terminal is electrically connected to the adaptive parameter controller, and a third input terminal is input with a low-frequency reference clock signal, wherein the digitally controlled oscillator generates the pixel clock signal based on the frequency control code, the configuration parameter and the low-frequency reference clock signal; The configuration parameters of the adaptive parameter controller include the error expander configuration parameters, the digital converter configuration parameters, the digital filter configuration parameters, and the digitally controlled oscillator configuration parameters.

3. The digital phase-locked loop according to claim 2, characterized in that: The error expander comprises: A delay unit, used for extending the width of the phase error signal; The expansion unit is used to expand the frequency width of the phase error signal to obtain a first expanded error signal corresponding to a low-frequency clock domain and a second expanded error signal corresponding to a high-frequency clock domain.

4. The digital phase-locked loop according to claim 3, characterized in that: The digital converter comprises: A coarse time-to-digital converter, configured to convert the length information of the first extended error signal into a first sequence; A fine-tuning time-to-digital converter is used to convert the length information of the second extended error signal into a second sequence.

5. The digital phase-locked loop according to claim 4, characterized in that: The phase error signal includes the phase error width and the phase error sign; When the phase error width is lower than a first threshold, the digital converter performs exponential amplification; When the phase error width is higher than a second threshold, the digital converter amplifies at a fixed ratio.

6. The digital phase-locked loop according to claim 4, characterized in that: The digital filter comprises: a coarse adjustment integrator, used for integrating the first sequence to obtain a first integrated sequence; A coarse tuning filter, used for filtering the first sequence and the first integrated sequence to obtain a first filtered signal; A fine tuning integrator, used for integrating the second sequence to obtain a second integrated sequence; A fine tuning filter is used to obtain a second filtered signal from the second sequence and the second integrated sequence; A loop filter is used for the first filtered signal and the second filtered signal to obtain a total filtered signal and the frequency control code corresponding to the total filtered signal.

7. The digital phase-locked loop according to claim 1, characterized in that: The phase detector comprises: A first synchronous shift rising edge detection module, whose input end serves as a first input end of the phase detector and is used to detect a rising edge of the video signal; A second synchronous shift rising edge detection module, whose input end serves as a second input end of the phase detector and is used to detect the rising edge of the feedback signal; A phase detection state transfer module, wherein a first input end is electrically connected to the first synchronous shift rising edge detection module, and a second input end is electrically connected to the second synchronous shift rising edge detection module, and is used to determine the phase error width and phase state of the video signal and the feedback signal according to the rising edge of the video signal and the rising edge of the feedback signal, wherein the phase state includes an advanced state and a lagging state.

8. A video signal sampling method, characterized in that: include: Receive a current frame video signal and a feedback signal; wherein the feedback signal is a signal obtained by frequency division processing of a pixel clock signal analyzed from a previous frame video signal; Using the digital phase-locked loop according to any one of claims 1 to 7, determining a current frame pixel clock signal based on the current frame video signal and the feedback signal, and tracking and locking the current frame pixel clock signal; Pixel data in the video signal is collected according to the current frame pixel clock signal.

9. The method according to claim 8, characterized in that The configuration parameters include multiple groups of configuration parameters, each group of configuration parameters corresponds to a phase error range; The configuration parameters are determined by the following steps: Based on the horizontal synchronization signal and the reference clock signal in the video signal, the phase error data is evaluated to determine the jitter range of the video signal; Based on the jitter range of the video signal, a plurality of groups of the configuration parameters are set accordingly.

10. The method according to claim 9, characterized in that The configuration parameters include first configuration parameters and multiple groups of second configuration parameters, the first configuration parameters are used to set the parameters of the analysis module before tracking and locking; the second configuration parameters are used to set the parameters of the analysis module after tracking and locking.

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