Clock synchronization circuit and clock synchronization method

Abstract

The invention provides a clock synchronization circuit and a clock synchronization method. The circuit comprises a voltage-controlled oscillation module, an input equal-pulse-width module, an output equal-pulse-width module, a synchronous feedback module and a phase discrimination module, the input equal-pulse-width module is used for converting a first input signal into a first equal-width pulse signal; the output equal-pulse-width module is used for converting the output signal into a second equal-pulse-width pulse signal; the synchronous feedback module is used for performing frequency comparison on the second equal-width pulse signal and a preset signal and sending a comparison result to the voltage-controlled oscillation module; the voltage-controlled oscillation module is used for performing frequency adjustment on the second equal-width pulse signal according to the frequency comparison result, and sending the adjusted first output signal to the phase discrimination module and the output equal-pulse-width module; and the phase discrimination module performs frequency and phase locking based on a frequency comparison result of the first output signal and the first input signal. According to the invention, the high-frequency stability and fast adaptability of the clock synchronization circuit can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a clock synchronization circuit and a clock synchronization method. Background Art

[0002] A clock synchronization circuit is a circuit used to coordinate the clock signals of multiple circuits or systems to the same frequency and phase. Its main function is to ensure synchronization between different components to avoid data loss or errors caused by asynchronous clock signals. It plays a vital role in modern electronic systems and is the basis for ensuring the normal operation of multiple applications. When the frequency of the output signal is equal to the frequency of the input signal, and the intervals between the rising and falling edges of the output signal are the same, the clock synchronization circuit can output a relatively stable 50% duty cycle clock signal of the same frequency. The same frequency clock signal has the same frequency as the reference clock signal, and there may be a certain offset in phase.

[0003] When the reference clock signal changes significantly or suddenly, the divider and phase lock switch cannot adapt to fast or large-scale frequency changes because the phase-locked loop in the clock synchronization circuit needs some time to adjust its output to match the new input frequency. The synchronous clock circuit may lose synchronization with the reference clock, resulting in inaccurate output of the same frequency clock, and the phase of the output clock may have a large deviation, thus affecting the integrity of the signal. How to achieve high frequency stability and fast adaptability is a major challenge in designing clock synchronization circuits. Summary of the invention

[0004] The present invention aims to provide a clock synchronization circuit and a clock synchronization method to solve the above technical problems and improve the high frequency stability and rapid adaptability of the clock synchronization circuit.

[0005] In order to solve the above technical problems, the present invention provides a clock synchronization circuit, including: a voltage-controlled oscillation module, an input equal pulse width module, an output equal pulse width module, a synchronous feedback module and a phase detection module;

[0006] The output end of the voltage-controlled oscillation module and the output end of the input equal pulse width module are connected to the input end of the phase detection module;

[0007] The output end of the voltage-controlled oscillation module is also connected to the input end of the output equal pulse width module;

[0008] The output end of the output equal pulse width module, the output end of the phase detection module and the output end of the input equal pulse width module are also connected to the input end of the synchronous feedback module;

[0009] The output end of the synchronous feedback module is connected to the input end of the voltage-controlled oscillation module;

[0010] The input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal;

[0011] The output equal-width pulse module is used to convert the output signal into a second equal-width pulse signal;

[0012] The synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with a preset signal, and send the frequency comparison result to the voltage-controlled oscillation module; wherein the preset signal includes the first equal-width pulse signal and a preset reference signal;

[0013] The voltage-controlled oscillation module is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module and the output equal-width pulse module;

[0014] The phase detection module performs frequency and phase locking based on a frequency comparison result of the first output signal and the first input signal.

[0015] In the above scheme, the input signal is converted into a standardized first equal-width pulse signal through the input equal-width module, and this signal is output to the phase detector module to achieve comparison with the output signal of the voltage-controlled oscillation module. The output signal of the voltage-controlled oscillation module is sent to the output equal-width module at the same time, and is input into the synchronous feedback module as a feedback signal. The synchronous feedback module compares the frequency of the received second equal-width pulse signal with the preset signal. According to the result of the frequency comparison, the input of the voltage-controlled oscillation module is quickly adjusted to change its output frequency so that it matches the first input signal as soon as possible. The phase detector module compares the frequency based on the first output signal and the first input signal, and realizes frequency locking and phase locking according to the frequency comparison result, and then quickly corrects the output signal to ensure that it is stably output at the new frequency. The input equal-width module converts the received first input signal into a first equal-width pulse signal with a uniform pulse width, which can eliminate the pulse width unevenness of the input signal and improve the accuracy of subsequent processing. The output equal-width module converts the signal output by the circuit into a second equal-width pulse signal with a uniform pulse width, ensuring that the entire circuit can maintain consistency in the output clock. The synchronous feedback module compares the frequency of the second equal-width pulse signal with the preset signal, and feeds back the comparison result to the voltage-controlled oscillation module to achieve frequency adjustment and stabilization. Frequency locking and phase locking are achieved based on the frequency comparison result of the first output signal and the first input signal, which can ensure that the system can quickly adjust to a new frequency state. The clock synchronization circuit enhances the synergy between the modules through real-time feedback and dynamic adjustment mechanisms, thereby improving the stability and rapid adaptability of the overall frequency. Due to the optimized design of each module, the efficiency of the signal interaction process is improved and the error recognition rate is reduced, so that the entire circuit can not only adjust quickly when facing large frequency changes, but also maintain the integrity and accuracy of the signal. These improvements make the clock synchronization circuit more competitive and practical in high-frequency signal applications.

[0016] In one implementation, the input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal, specifically including:

[0017] The input equal pulse width module includes a first capacitor, a first resistor, a first NOT gate and a second NOT gate;

[0018] The first input signal is connected to the positive electrode of the first capacitor and the input end of the phase detection module;

[0019] The negative electrode of the first capacitor is connected to the first end of the first resistor and the input end of the first NOT gate;

[0020] The output end of the first NOT gate is connected to the input end of the second NOT gate;

[0021] The output end of the second NOT gate is connected to the input end of the synchronous feedback module.

[0022] In one implementation, the output equal-width pulse module is used to convert the output signal into a second equal-width pulse signal, specifically including:

[0023] The output constant pulse width module includes a second capacitor, a second resistor, a third NOT gate and a fourth NOT gate;

[0024] The input end of the third NOT gate is connected to the output end of the voltage-controlled oscillation module and the input end of the phase detection module;

[0025] The output end of the third NOT gate is connected to the positive electrode of the second capacitor;

[0026] The negative electrode of the second capacitor is connected to the first end of the second resistor and the input end of the fourth NOT gate;

[0027] The second end of the second resistor is grounded;

[0028] The output end of the fourth NOT gate is connected to the input end of the synchronous feedback module.

[0029] In one implementation, the synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with a preset signal and send the frequency comparison result to the voltage-controlled oscillation module, specifically including:

[0030] The synchronous feedback module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, an operational amplifier and a voltage source;

[0031] The first end of the third resistor is connected to the output end of the output equal pulse width module;

[0032] The first end of the fourth resistor is connected to the output end of the phase detection module;

[0033] The first end of the fifth resistor is connected to the output end of the input equal pulse width module;

[0034] The second end of the third resistor, the second end of the fourth resistor and the second end of the fifth resistor are connected to the positive electrode of the third capacitor, the positive electrode of the fourth capacitor, the first end of the sixth resistor and the negative input terminal of the operational amplifier;

[0035] The negative electrode of the third capacitor is connected to the second end of the sixth resistor, the positive electrode of the voltage source, and the positive input terminal of the operational amplifier;

[0036] The negative electrode of the voltage source is connected to the preset reference signal.

[0037] In one implementation, the voltage-controlled oscillation module is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, specifically including:

[0038] The voltage-controlled oscillation module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, a first switch, a first voltage comparator and a second voltage comparator;

[0039] The first end of the seventh resistor is connected to the output end of the synchronous feedback module and the negative input end of the second voltage comparator;

[0040] The second end of the seventh resistor is connected to the first end of the eighth resistor and the negative input end of the first voltage comparator;

[0041] The output end of the first voltage comparator is connected to the input end of the output equal pulse width module and the input end of the phase detection module;

[0042] The first end of the ninth resistor is connected to the power supply end;

[0043] The second end of the ninth resistor is connected to the first end of the first switch, the positive input end of the first voltage comparator, the positive input end of the second voltage comparator, and the positive electrode of the fifth capacitor; wherein, when the first switch is closed, the second end of the first switch is connected to the negative electrode of the fifth capacitor or the positive electrode of the sixth capacitor;

[0044] The positive electrode of the sixth capacitor is connected to the first end of the tenth resistor and the output end of the second voltage comparator;

[0045] The second end of the eighth resistor, the negative electrode of the fifth capacitor, the negative electrode of the sixth capacitor and the second end of the tenth resistor are grounded.

[0046] In one implementation, the phase detection module performs frequency and phase locking based on a frequency comparison result between the first output signal and the first input signal, specifically including:

[0047] The phase detection module includes a seventh capacitor, an eighth capacitor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a trigger;

[0048] The positive electrode of the seventh capacitor is connected to the output end of the voltage-controlled oscillation module;

[0049] The negative electrode of the seventh capacitor is connected to the first end of the eleventh resistor, the first end of the twelfth resistor, and the reset input end of the trigger;

[0050] The positive electrode of the eighth capacitor is connected to the first input signal;

[0051] The negative electrode of the eighth capacitor is connected to the first end of the thirteenth resistor, the first end of the fourteenth resistor, and the setting input end of the trigger;

[0052] The second end of the eleventh resistor and the second end of the thirteenth resistor are connected to the power supply end;

[0053] A second end of the twelfth resistor and a second end of the fourteenth resistor are grounded.

[0054] In one implementation, the seventh capacitor and the eighth capacitor are electrolytic capacitors, and the trigger is an RS trigger.

[0055] In a second aspect, the present application further provides a clock synchronization method applicable to the clock synchronization circuit as described above, comprising:

[0056] Sending the received first input signal to the phase detection module and controlling the input equal-width pulse module to convert the first input signal into a first equal-width pulse signal, and sending the first equal-width pulse signal to the synchronous feedback module;

[0057] Controlling the output equal-width pulse module to convert the generated output signal into a second equal-width pulse signal and sending the second equal-width pulse signal to the phase detection module;

[0058] Control the phase detection module to frequency-lock and phase-lock the first input signal and the second equal-width pulse signal based on a trigger, and send the second output result of the concurrent trigger to the synchronous feedback module;

[0059] Control the synchronous feedback module to perform frequency comparison on the second equal-width pulse signal, the first equal-width pulse signal, and a preset reference signal, and send the frequency comparison result to the voltage-controlled oscillation module;

[0060] The voltage-controlled oscillation module is controlled to adjust the frequency of the second equal-width pulse signal based on the frequency comparison result, and the second equal-width pulse signal after the frequency adjustment is sent to the output equal-width pulse module and the phase detection module.

[0061] In the above scheme, the received first input signal is converted into a first equal-width pulse signal by the input equal-width module, and is quickly output to the synchronous feedback module and the phase detector module. The phase detector module receives the second equal-width pulse signal (output from the output equal-width module) and the first input signal, performs phase lock based on the frequency difference, and quickly feeds back the frequency comparison result to the synchronous feedback module. The synchronous feedback module also compares the frequency of the second equal-width pulse signal with the preset signal (the first equal-width pulse signal and the reference signal), and adjusts the input of the voltage-controlled oscillation module to maintain synchronization according to the frequency change. When the reference signal is detected to have a large change, the system quickly performs frequency adjustment and output update to ensure that the output signal is of the same frequency and stable, thereby reducing the phase deviation of the output signal. Adaptive adjustment is implemented in the synchronous feedback module, and the control voltage of the voltage-controlled oscillation module is adjusted according to the real-time information of the frequency comparison to ensure that it can quickly respond to the frequency change of the input signal and reduce the frequency lock time. By dynamically adjusting the feedback gain, the gain of the output signal generated is adjusted according to the rate and amplitude of the input signal change, which helps to quickly adapt to sudden frequency changes. The dynamic pulse width adjustment mechanism is introduced in the output pulse width module, which can adjust the pulse width according to the actual changes of the input signal during circuit operation, thereby ensuring that an accurate clock signal is always provided in a rapidly changing environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of the connection relationship of a clock synchronization circuit provided in one embodiment of the present invention;

[0063] Figure 2 A schematic diagram of the connection relationship of an input equal pulse width module provided in one embodiment of the present invention;

[0064] Figure 3 A schematic diagram of the connection relationship of an output equal pulse width module provided in one embodiment of the present invention;

[0065] Figure 4 A schematic diagram of the connection relationship of a synchronous feedback module provided in one embodiment of the present invention;

[0066] Figure 5 A schematic diagram of the connection relationship of a voltage-controlled oscillation module provided in one embodiment of the present invention;

[0067] Figure 6 A schematic diagram of the connection relationship of a phase detection module provided in one embodiment of the present invention;

[0068] Figure 7 The figure is a flow chart of a clock synchronization method provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0069] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0070] The terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0071] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0072] Example 1

[0073] See also Figure 1 , Figure 1 A clock synchronization circuit according to an embodiment of the present invention is provided. A clock synchronization circuit includes: a voltage-controlled oscillation module 101, an input pulse width equalization module 102, an output pulse width equalization module 103, a synchronous feedback module 104 and a phase detection module 105;

[0074] The output end of the voltage-controlled oscillation module 101 and the output end of the input equal pulse width module 102 are connected to the input end of the phase detection module;

[0075] The output end of the voltage-controlled oscillation module 101 is also connected to the input end of the output equal pulse width module 103;

[0076] The output end of the output equal pulse width module 103, the output end of the phase detection module 105 and the output end of the input equal pulse width module 102 are also connected to the input end of the synchronous feedback module 104;

[0077] The output end of the synchronous feedback module 104 is connected to the input end of the voltage-controlled oscillation module 101;

[0078] The input equal pulse width module 102 is used to convert the received first input signal into a first equal width pulse signal;

[0079] The output equal-width pulse module 103 is used to convert the output signal into a second equal-width pulse signal;

[0080] The synchronous feedback module 104 is used to compare the frequency of the second equal-width pulse signal with a preset signal, and send the frequency comparison result to the voltage-controlled oscillation module 101; wherein the preset signal includes the first equal-width pulse signal and a preset reference signal Vref;

[0081] The voltage-controlled oscillation module 101 is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module 105 and the output equal-width pulse module 103;

[0082] The phase detection module 105 performs frequency and phase locking based on a frequency comparison result of the first output signal and the first input signal.

[0083] Figure 2 The figure is a schematic diagram of the connection relationship of an input equal pulse width module provided in one embodiment of the present invention.

[0084] In one embodiment, the input equal pulse width module 102 is used to convert the received first input signal into a first equal width pulse signal, specifically including: the input equal pulse width module includes a first capacitor C3, a first resistor R5, a first NOT gate NOR1 and a second NOT gate NOR2; the first input signal Vi is connected to the positive electrode of the first capacitor C3 and the input end of the phase detection module; the negative electrode of the first capacitor C3 is connected to the first end of the first resistor R5 and the input end of the first NOT gate NOR1; the output end of the first NOT gate NOR1 is connected to the input end of the second NOT gate NOR2; the output end of the second NOT gate NOR2 is connected to the input end of the synchronous feedback module.

[0085] In an input equal pulse width module 102 provided by an embodiment of the present invention, an RC differential network is constructed by a first capacitor C3 and a first resistor R5, and the RC differential network can be used as a differentiator. At the moment when the input signal changes, the capacitor C3 will charge or discharge quickly to generate an output voltage proportional to the rate of change of the input signal. This means that when the input signal rises or falls, a spike will appear in the output signal to help identify the edge of the signal. By adjusting the values ​​of the first resistor R5 and the first capacitor C3, the width and shape of the output pulse can be changed. If the duty cycle of the input signal is 20%, the RC network can extend the pulse width through the discharge process, thereby outputting a signal with a duty cycle close to 50%. The input equal pulse width module can convert the input unequal width pulse signal into a first equal width pulse signal through the RC differential network and the phase remains unchanged through the design of the first resistor R5 and the first capacitor C3. The characteristic of the NOT gate is that the output is high only when all inputs are low. Furthermore, the first NOT gate NOR1 will perform logic processing according to the input signal and the output of the RC network. The output of the first NOT gate NOR1 will remain high for a period of time after the input signal becomes low, thereby lengthening the width of the output pulse and further adjusting the shape of the output pulse (the first equal-width pulse signal). The input of the second NOT gate NOR2 comes from the output of NOR1. This gate inverts the output signal of the first NOT gate to form a suitable clock signal output. And the output of the second NOT gate NOR2 is connected to the synchronous feedback module, which can enable the circuit to dynamically adjust the parameters according to the actual output situation to better adapt to input signals with different duty cycles.

[0086] See also Figure 3 , Figure 3 The figure is a connection diagram of an output equal pulse width module provided in one embodiment of the present invention. In one embodiment, the output equal pulse width module 103 is used to convert the output signal into a second equal width pulse signal, specifically including: the output equal pulse width module includes a second capacitor C4, a second resistor R6, a third NOT gate NOR3 and a fourth NOT gate NOR4; the input end of the third NOT gate NOR3 is connected to the output end of the voltage controlled oscillation module 101 and the input end of the phase detection module 105; the output end of the third NOT gate NOR3 is connected to the positive electrode of the second capacitor C4; the negative electrode of the second capacitor C4 is connected to the first end of the second resistor R6 and the input end of the fourth NOT gate NOR4; the second end of the second resistor R6 is grounded; the output end of the fourth NOT gate NOR4 is connected to the input end of the synchronous feedback module.

[0087] In an output equal pulse width module 103 provided by an embodiment of the present invention, the second capacitor C4 is used to store charge to form a delay and pulse shaping function. It can adjust the width of the output pulse according to the change of the input signal. The charging and discharging characteristics of the second capacitor C4 can affect the duration of the output signal, so that it remains at the required pulse width. The second resistor R6 and the second capacitor C4 form an RC network, and the resistance value of the second resistor R6 determines the charging and discharging speed of the second capacitor C4, thereby affecting the width and shape of the output pulse. The third NOT gate NOR3 is used for logic integration, and its input end is connected to the output signal of the voltage-controlled oscillation module 101 and the phase-comparison module 105. By performing logical processing on the input signal, the third NOT gate NOR3 can identify the state change of the input signal and output a high-level signal at an appropriate time. The fourth NOT gate NOR4 is used to further process the output signal of the third NOT gate NOR3, and invert the output signal of NOR3 to ensure that an appropriate output pulse is generated. At the same time, the output of the fourth NOT gate NOR4 will also be transmitted to the synchronous feedback module to provide feedback information for adjusting the circuit working state. Through the coordinated work of the second capacitor C4, the second resistor R6, the third NOT gate NOR3 and the fourth NOT gate NOR4, the output equal pulse width module can effectively convert the input signal into an equal pulse width pulse signal, thereby meeting the pulse width requirement of the clock synchronization circuit.

[0088] See also Figure 4 , Figure 4 The figure is a schematic diagram of the connection relationship of a synchronous feedback module provided in one embodiment of the present invention. In one embodiment, the synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with the preset signal, and send the frequency comparison result to the voltage-controlled oscillation module, specifically including: the synchronous feedback module includes a third resistor R11, a fourth resistor R12, a fifth resistor R13, a sixth resistor R14, a third capacitor C9, a fourth capacitor C10, an operational amplifier OPA1 and a voltage source; the first end of the third resistor R11 is connected to the output end of the output equal-width pulse module; the first end of the fourth resistor R12 is connected to the output end of the phase-detection module; the fifth resistor R The first end of 13 is connected to the output end of the input equal pulse width module; the second end of the third resistor R11, the second end of the fourth resistor R12 and the second end of the fifth resistor R13 are connected to the positive electrode of the third capacitor C9, the positive electrode of the fourth capacitor C10, the first end of the sixth resistor R14, and the negative input end of the operational amplifier OPA1; the negative electrode of the third capacitor C9 is connected to the second end of the sixth resistor R14, the positive electrode of the voltage source, and the positive input end of the operational amplifier OPA1; the negative electrode of the voltage source is connected to the preset reference signal Vref.

[0089] In a synchronous feedback module 104 provided in an embodiment of the present invention, the third resistor R11 is connected to the second equal-width pulse signal (from the output equal-width module), the fourth resistor R12 is connected to the output signal of the phase-comparison module, and the fifth resistor R13 is connected to the first equal-width pulse signal (the output signal of the input equal-width module). These resistors, the third capacitor C9, the fourth capacitor C10 and the sixth resistor R14 together form a weighted average network to combine different signals together. Among them, the third capacitor C9 and the fourth capacitor C10 are used to filter and smooth the signal, eliminate high-frequency noise, and ensure that the input signal of the operational amplifier OPA1 is stable. The signals connected to each resistor of R11, R12, and R13 are connected to the negative input terminal of OPA1 after filtering through C9 and C10. The positive input terminal of OPA1 is connected to a voltage source, and the negative pole of the voltage source provides a preset reference signal Vref. The function of the operational amplifier OPA1 is to compare the voltage difference between the signal filtered by C9 and C10 and the preset reference signal Vref. The operational amplifier OPA1 will generate an error signal representing the difference between the frequency of the output equal-width signal and the frequency of the reference signal. The voltage value of this error signal is proportional to the frequency difference. Specifically, the operational amplifier OPA1 compares the filtered signal with the preset reference signal Vref, the negative input of OPA1 is connected to the weighted signal, and the positive input is connected to the preset reference signal Vref. If the output signal frequency is lower than the preset reference signal Vref, the output of OPA1 will be positive; if it is higher than the preset reference signal Vref, the output will be negative. The error signal will be transmitted to the voltage-controlled oscillation module through the feedback path (i.e., the loop between the feedback module and the voltage-controlled oscillation module), which will affect the control voltage of the voltage-controlled oscillator, thereby adjusting its output frequency. Specifically, when the output signal frequency is lower than the reference signal frequency: the feedback signal will cause the control voltage of the voltage-controlled oscillator to increase, thereby increasing the oscillation frequency, until the output signal frequency matches the reference signal frequency. When the output signal frequency is higher than the reference signal frequency: the feedback signal will cause the control voltage of the voltage-controlled oscillator to decrease, thereby reducing the oscillation frequency, until the output signal frequency matches the reference signal frequency. Through the configuration of the above-mentioned synchronous feedback module, a synchronous feedback system that automatically adjusts the output signal frequency can be realized. This system automatically adjusts the frequency by comparing the frequency of the output signal with the frequency of a preset reference signal, generating an error signal and feeding it back to the voltage-controlled oscillator.

[0090] See also Figure 5 , Figure 5A schematic diagram of the connection relationship of a voltage-controlled oscillation module provided in one embodiment of the present invention. In one embodiment, the voltage-controlled oscillation module 101 is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, specifically including: the voltage-controlled oscillation module 101 includes a seventh resistor R1, an eighth resistor R2, a ninth resistor R3, a tenth resistor R4, a fifth capacitor C1, a sixth capacitor C2, a first switch K1, a first voltage comparator COMP1 and a second voltage comparator COMP2; the first end of the seventh resistor R1 is connected to the output end of the synchronous feedback module and the negative input end of the second voltage comparator; the second end of the seventh resistor R1 is connected to the first end of the eighth resistor R2 and the negative input end of the first voltage comparator COMP1; the output end of the first voltage comparator COMP1 is connected to the input end of the output equal-width pulse module, The input end of the phase detection module is connected; the first end of the ninth resistor R3 is connected to the power supply end; the second end of the ninth resistor R3 is connected to the first end of the first switch K1, the positive input end of the first voltage comparator COMP1, the positive input end of the second voltage comparator COMP2, and the positive electrode of the fifth capacitor C1; wherein, when the first switch K1 is closed, the second end of the first switch K1 is connected to the negative electrode of the fifth capacitor C1 or the positive electrode of the sixth capacitor C2; the positive electrode of the sixth capacitor C2 is connected to the first end of the tenth resistor R4 and the output end of the second voltage comparator COMP2; the second end of the eighth resistor R2, the negative electrode of the fifth capacitor C1, the negative electrode of the sixth capacitor C2 and the second end of the tenth resistor R4 are grounded.

[0091] In a voltage-controlled oscillation module 101 provided in an embodiment of the present invention, the seventh resistor R1, the eighth resistor R2, the tenth resistor R4, the fifth capacitor C1 and the sixth capacitor C2 constitute an RC circuit to form a sawtooth wave generator. When the sawtooth wave is charged, the capacitor is charged through the resistor according to a fixed time constant to form a rising slope. Preferably, the resistor can also be changed to a constant current source to obtain a more ideal linear slope, thereby accurately controlling the frequency. The negative input terminal of the first voltage comparator is connected to the output terminal of the seventh resistor and the synchronous feedback module, and the positive input terminal is connected to the charged sawtooth wave signal. When the sawtooth wave reaches V_{control} (determined by the feedback signal), the first voltage comparator COMP1 will flip the output and provide a switch control signal. The second voltage comparator COMP2 is used to set the duty cycle of the sawtooth wave so that the final output signal has a duty cycle of 50% to ensure the stability of the output signal. Driven by the output signal of COMP1, the reset of the sawtooth wave is controlled. When the output voltage of the sawtooth wave is higher than V_{control}, the first voltage comparator COMP1 outputs a high level, opens the first switch K1 and connects to the negative electrode of the fifth capacitor C1 or the positive electrode of the sixth capacitor C2, so that the sawtooth wave capacitor discharges quickly and completes a sawtooth wave cycle. By adjusting the output (error signal) from the synchronous feedback module, that is, how to affect the size of the V_{control} voltage, this voltage value determines the trigger point of the sawtooth wave. Increasing V_{control} will cause the sawtooth wave to rise to this voltage at the same RC time constant, thereby reducing the frequency; conversely, reducing V_{control} will increase the output frequency. When V_{control} increases, the time required for the sawtooth wave to reach this voltage increases, resulting in a decrease in the output frequency; once the sawtooth wave voltage exceeds V_{control}, the first voltage comparator COMP1 flips, the first switch K1 opens to discharge the fifth capacitor C1, and the sawtooth wave begins to descend. When V_{control} decreases, the time to reach the comparison level is shortened and the output frequency increases.

[0092] See also Figure 6 , Figure 6The diagram is a connection relationship diagram of a phase detection module provided in an embodiment of the present invention. In one embodiment, the phase detection module 105 performs frequency and phase locking based on the frequency comparison result of the first output signal and the first input signal, specifically including: the phase detection module includes a seventh capacitor C7, an eighth capacitor C8, an eleventh resistor R7, a twelfth resistor R8, a thirteenth resistor R9, a fourteenth resistor R10 and a trigger; the positive electrode of the seventh capacitor C7 is connected to the output end of the voltage-controlled oscillation module; the negative electrode of the seventh capacitor C7 is connected to the first end of the eleventh resistor R7, the first end of the twelfth resistor R8, and the reset input end of the trigger; the positive electrode of the eighth capacitor C8 is connected to the first input signal Vin; the negative electrode of the eighth capacitor C8 is connected to the first end of the thirteenth resistor R9, the first end of the fourteenth resistor R10, and the set input end of the trigger; the second end of the eleventh resistor R7 and the second end of the thirteenth resistor R9 are connected to the power supply end Vcc; the second end of the twelfth resistor R8 and the second end of the fourteenth resistor R10 are grounded.

[0093] In a phase detection module provided by an embodiment of the present invention, the seventh capacitor C7 is used to couple the first output signal of the voltage-controlled oscillation module and filter the signal, the eighth capacitor C8 is used to couple the first input signal Vin, the eleventh resistor R7, the twelfth resistor R8, the thirteenth resistor R9 and the fourteenth resistor R10 are used to set the time constant of the circuit and the gain of the signal, and the trigger is used to process the digital signal and the logic control of the frequency lock. The trigger includes two control input terminals, namely the reset input terminal and the setting input terminal. The reset input terminal is connected to the combination of the seventh capacitor C7, the eleventh resistor R7 and the twelfth resistor R8. When the first output signal output by the voltage-controlled oscillation module is higher than a certain threshold, the reset will be triggered and the output of the trigger will be cleared. The setting input terminal is connected to the combination of the eighth capacitor C8, the thirteenth resistor R9 and the fourteenth resistor R10. When the first input signal Vin is offset to the setting input terminal of the trigger through the eighth capacitor C8, the trigger will be set to a high level state. When the first output signal output by the voltage-controlled oscillation module 101 is higher than the first input signal Vin, the trigger will be frequently reset, thereby maintaining the output low level, causing the phase-locked state to be fed back to the output frequency to decrease; on the contrary, if the first input signal Vin is higher than the first output signal output by the voltage-controlled oscillation module 101, the trigger will enter the setting state more often, maintaining the output high level, thereby causing the output frequency to increase. When the frequencies of the first input signal Vin and the first output signal gradually approach each other, the state of the trigger will become more stable, and the frequency of the output signal will be fine-tuned to accurately match the frequency of the input signal. At this time, the phase-locked module 105 is in a phase-locked state, which improves the stability and anti-interference of the system. The phase-locked module uses capacitors for signal coupling and resistors to adjust circuit parameters, and uses triggers for logic control to achieve the locking of the output signal frequency and the input signal frequency. By comparing the frequencies of the output and input signals in real time, the module can adaptively adjust the output frequency, so that the system can maintain the required accurate frequency under different conditions, and achieve an effective frequency-locked phase-locked function.

[0094] Preferably, the seventh capacitor C7 and the eighth capacitor C8 are electrolytic capacitors, and the trigger is an RS trigger. Electrolytic capacitors are suitable for coupling and filtering of low-frequency signals, and can achieve smoothing and delay processing of specific stages. In the phase-detection module, electrolytic capacitors help to filter out high-frequency noise and smooth input signals, thereby providing more stable comparison conditions. The RS trigger can respond quickly when the signal state changes (such as from reset to set or vice versa), is suitable for immediate response to frequency changes, and can maintain the stability of the output. Compared with complex timing circuits with multiple inputs and outputs, the simple logic structure of the RS trigger is easy to design and implement, reduces circuit complexity, and enhances reliability. The two are used in combination to achieve higher phase-locked accuracy and stability. The RS trigger can quickly respond to changes in frequency, while the electrolytic capacitor can smooth the signal and reduce the impact of noise on the trigger.

[0095] The embodiment of the present invention provides a clock synchronization circuit, wherein the input signal is converted into a standardized first equal-width pulse signal through an input equal-width module, and the signal is output to a phase detector module to realize comparison with the output signal of a voltage-controlled oscillation module. The output signal of the voltage-controlled oscillation module is simultaneously sent to an output equal-width module and input to a synchronous feedback module as a feedback signal. The synchronous feedback module compares the frequency of the received second equal-width pulse signal with the preset signal. According to the result of the frequency comparison, the input of the voltage-controlled oscillation module is rapidly adjusted to change its output frequency so that it matches the first input signal as soon as possible. The phase detector module compares the frequency based on the first output signal with the first input signal, realizes frequency locking and phase locking according to the result of the frequency comparison, and then rapidly corrects the output signal to ensure that it is stably output at the new frequency. The input equal-width module converts the received first input signal into a first equal-width pulse signal of uniform pulse width, which can eliminate the pulse width non-uniformity of the input signal and improve the accuracy of subsequent processing. The output equal-width module converts the signal output by the circuit into a second equal-width pulse signal of uniform pulse width, ensuring that the entire circuit can maintain consistency in the output clock. The synchronous feedback module compares the frequency of the second equal-width pulse signal with the preset signal, and feeds back the comparison result to the voltage-controlled oscillation module to achieve frequency adjustment and stabilization. Frequency locking and phase locking are achieved based on the frequency comparison result of the first output signal and the first input signal, which can ensure that the system can quickly adjust to a new frequency state. The clock synchronization circuit enhances the synergy between the modules through real-time feedback and dynamic adjustment mechanisms, thereby improving the stability and rapid adaptability of the overall frequency. Due to the optimized design of each module, the efficiency of the signal interaction process is improved and the error recognition rate is reduced, so that the entire circuit can not only adjust quickly when facing large frequency changes, but also maintain the integrity and accuracy of the signal. These improvements make the clock synchronization circuit more competitive and practical in high-frequency signal applications.

[0096] Example 2

[0097] See also Figure 7 , Figure 7 The present invention provides a clock synchronization method according to an embodiment of the present invention. The present invention provides a clock synchronization method, which is applicable to the clock synchronization circuit according to embodiment 1, and includes:

[0098] Step 201: sending a received first input signal to a phase detection module and controlling an input equal-width pulse module to convert the first input signal into a first equal-width pulse signal, and sending the first equal-width pulse signal to a synchronous feedback module;

[0099] Step 202: Control the output equal-width pulse module to convert the generated output signal into a second equal-width pulse signal and send the second equal-width pulse signal to the phase detection module;

[0100] Step 203: Control the phase detection module to frequency-lock and phase-lock the first input signal and the second equal-width pulse signal based on a trigger, and send the second output result of the concurrent trigger to the synchronous feedback module;

[0101] Step 204: Control the synchronous feedback module to perform frequency comparison on the second equal-width pulse signal, the first equal-width pulse signal, and a preset reference signal, and send the frequency comparison result to the voltage-controlled oscillation module;

[0102] Step 205: Control the voltage-controlled oscillation module to adjust the frequency of the second equal-width pulse signal based on the frequency comparison result, and send the frequency-adjusted second equal-width pulse signal to the output equal-width pulse module and the phase detection module.

[0103] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the clock synchronization method described above can refer to the corresponding process of the clock synchronization circuit in the aforementioned embodiment, and will not be repeated here.

[0104] The embodiment of the present invention provides a clock synchronization method, in which the received first input signal is converted into a first equal-width pulse signal through an input equal-width module, and is quickly output to a synchronous feedback module and a phase detection module. The phase detection module receives a second equal-width pulse signal (output from an output equal-width module) and a first input signal, performs phase locking based on a frequency difference, and quickly feeds back the frequency comparison result to the synchronous feedback module. The synchronous feedback module simultaneously compares the frequency of the second equal-width pulse signal with a preset signal (a first equal-width pulse signal and a reference signal), and adjusts the input of a voltage-controlled oscillation module accordingly, and actively adjusts the control signal according to the frequency change to maintain synchronization. When a large change in the reference signal is detected, the system quickly performs frequency adjustment and output update to ensure that the output signal is of the same frequency and stable, thereby reducing the phase deviation effect of the output signal. Adaptive adjustment is implemented in the synchronous feedback module, and the control voltage of the voltage-controlled oscillation module is adjusted according to the real-time information of the frequency comparison, ensuring that the frequency change of the input signal can be quickly responded to, and the frequency locking time is reduced. By dynamically adjusting the feedback gain, the gain of the output signal generated is adjusted according to the rate and amplitude of the input signal change, which helps to quickly adapt to sudden frequency changes. The dynamic pulse width adjustment mechanism is introduced in the output pulse width module, which can adjust the pulse width according to the actual changes of the input signal during circuit operation, thereby ensuring that an accurate clock signal is always provided in a rapidly changing environment.

[0105] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention. These improvements and substitutions should also be regarded as the scope of protection of the present invention.

Claims

1. A clock synchronization circuit, characterized in that: include: Voltage controlled oscillation module, input equal pulse width module, output equal pulse width module, synchronous feedback module and phase detection module; The output end of the voltage-controlled oscillation module and the output end of the input equal pulse width module are connected to the input end of the phase detection module; The output end of the voltage-controlled oscillation module is also connected to the input end of the output equal pulse width module; The output end of the output equal pulse width module, the output end of the phase detection module and the output end of the input equal pulse width module are also connected to the input end of the synchronous feedback module; The output end of the synchronous feedback module is connected to the input end of the voltage-controlled oscillation module; The input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal; The output equal-width pulse module is used to convert the output signal into a second equal-width pulse signal; The synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with a preset signal, and send the frequency comparison result to the voltage-controlled oscillation module; wherein the preset signal includes the first equal-width pulse signal and a preset reference signal; The voltage-controlled oscillation module is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, and send the adjusted first output signal to the phase detection module and the output equal-width pulse module; The phase detection module performs frequency and phase locking based on a frequency comparison result of the first output signal and the first input signal.

2. A clock synchronization circuit as claimed in claim 1, characterized in that: The input equal-width pulse module is used to convert the received first input signal into a first equal-width pulse signal, specifically including: The input equal pulse width module includes a first capacitor, a first resistor, a first NOT gate and a second NOT gate; The first input signal is connected to the positive electrode of the first capacitor and the input end of the phase detection module; The negative electrode of the first capacitor is connected to the first end of the first resistor and the input end of the first NOT gate; The output end of the first NOT gate is connected to the input end of the second NOT gate; The output end of the second NOT gate is connected to the input end of the synchronous feedback module.

3. A clock synchronization circuit as claimed in claim 1, characterized in that: The output equal-width pulse module is used to convert the output signal into a second equal-width pulse signal, specifically comprising: The output constant pulse width module includes a second capacitor, a second resistor, a third NOT gate and a fourth NOT gate; The input end of the third NOT gate is connected to the output end of the voltage-controlled oscillation module and the input end of the phase detection module; The output end of the third NOT gate is connected to the positive electrode of the second capacitor; The negative electrode of the second capacitor is connected to the first end of the second resistor and the input end of the fourth NOT gate; The second end of the second resistor is grounded; The output end of the fourth NOT gate is connected to the input end of the synchronous feedback module.

4. A clock synchronization circuit as claimed in claim 1, characterized in that: The synchronous feedback module is used to compare the frequency of the second equal-width pulse signal with the preset signal, and send the frequency comparison result to the voltage-controlled oscillation module, specifically including: The synchronous feedback module includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a third capacitor, a fourth capacitor, an operational amplifier and a voltage source; The first end of the third resistor is connected to the output end of the output equal pulse width module; The first end of the fourth resistor is connected to the output end of the phase detection module; The first end of the fifth resistor is connected to the output end of the input equal pulse width module; The second end of the third resistor, the second end of the fourth resistor and the second end of the fifth resistor are connected to the positive electrode of the third capacitor, the positive electrode of the fourth capacitor, the first end of the sixth resistor and the negative input terminal of the operational amplifier; The negative electrode of the third capacitor is connected to the second end of the sixth resistor, the positive electrode of the voltage source, and the positive input terminal of the operational amplifier; The negative electrode of the voltage source is connected to the preset reference signal.

5. A clock synchronization circuit as claimed in claim 1, characterized in that: The voltage-controlled oscillation module is used to adjust the frequency of the second equal-width pulse signal according to the frequency comparison result, specifically including: The voltage-controlled oscillation module includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, a first switch, a first voltage comparator and a second voltage comparator; The first end of the seventh resistor is connected to the output end of the synchronous feedback module and the negative input end of the second voltage comparator; The second end of the seventh resistor is connected to the first end of the eighth resistor and the negative input end of the first voltage comparator; The output end of the first voltage comparator is connected to the input end of the output equal pulse width module and the input end of the phase detection module; The first end of the ninth resistor is connected to the power supply end; The second end of the ninth resistor is connected to the first end of the first switch, the positive input end of the first voltage comparator, the positive input end of the second voltage comparator, and the positive electrode of the fifth capacitor; wherein, when the first switch is closed, the second end of the first switch is connected to the negative electrode of the fifth capacitor or the positive electrode of the sixth capacitor; The positive electrode of the sixth capacitor is connected to the first end of the tenth resistor and the output end of the second voltage comparator; The second end of the eighth resistor, the negative electrode of the fifth capacitor, the negative electrode of the sixth capacitor and the second end of the tenth resistor are grounded.

6. A clock synchronization circuit as claimed in claim 1, characterized in that: The phase detection module performs frequency and phase locking based on a frequency comparison result of the first output signal and the first input signal, specifically comprising: The phase detection module includes a seventh capacitor, an eighth capacitor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a trigger; The positive electrode of the seventh capacitor is connected to the output end of the voltage-controlled oscillation module; The negative electrode of the seventh capacitor is connected to the first end of the eleventh resistor, the first end of the twelfth resistor, and the reset input end of the trigger; The positive electrode of the eighth capacitor is connected to the first input signal; The negative electrode of the eighth capacitor is connected to the first end of the thirteenth resistor, the first end of the fourteenth resistor, and the setting input end of the trigger; The second end of the eleventh resistor and the second end of the thirteenth resistor are connected to the power supply end; A second end of the twelfth resistor and a second end of the fourteenth resistor are grounded.

7. A clock synchronization circuit as claimed in claim 6, characterized in that: The seventh capacitor and the eighth capacitor are electrolytic capacitors, and the trigger is an RS trigger.

8. A clock synchronization method, characterized in that: A clock synchronization circuit applicable to any one of claims 1 to 7, comprising: Sending the received first input signal to the phase detection module and controlling the input equal-width pulse module to convert the first input signal into a first equal-width pulse signal, and sending the first equal-width pulse signal to the synchronous feedback module; Controlling the output equal-width pulse module to convert the generated output signal into a second equal-width pulse signal and sending the second equal-width pulse signal to the phase detection module; Control the phase detection module to frequency-lock and phase-lock the first input signal and the second equal-width pulse signal based on a trigger, and send the second output result of the concurrent trigger to the synchronous feedback module; Control the synchronous feedback module to perform frequency comparison on the second equal-width pulse signal, the first equal-width pulse signal, and a preset reference signal, and send the frequency comparison result to the voltage-controlled oscillation module; The voltage-controlled oscillation module is controlled to adjust the frequency of the second equal-width pulse signal based on the frequency comparison result, and the second equal-width pulse signal after the frequency adjustment is sent to the output equal-width pulse module and the phase detection module.

Images