Method and system for correcting IQ signal imbalance of zero intermediate frequency receiver

Abstract

The invention discloses a method and a system for correcting IQ signal imbalance of a zero intermediate frequency receiver. The method comprises the following steps of: 1, inputting a radio frequency signal subjected to quadrature modulation to the zero intermediate frequency receiver; 2, performing frequency mixing on the radio frequency signals; 3, filtering and amplifying the signal; 4, performing analog-to-digital conversion on the signals; 5, transmitting the signal into a baseband processing unit, and respectively squaring to obtain power; 6, setting an average power threshold value of signals which can be received by the zero intermediate frequency receiver; 7, calculating first average power; 8, judging the first average power and the average power threshold value, and executing the step 9 or 7; 9, solving second average power; 10, judging the second average power and the average power threshold value, and executing the step 11 or 9; 11, multiplying the two analog-to-digital conversion signals after amplitude correction to obtain a product; 12, averaging the product in sections to obtain an average value; and 13, determining to end the correction process or execute the step 12 according to the average value.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal processing, and in particular relates to a method and system for correcting IQ signal imbalance of a zero intermediate frequency receiver. Background Art

[0002] With the rise of software radio technology, zero-IF receivers have attracted widespread attention in recent years due to their small size, high integration and low power consumption. The commonly used structural block diagrams are as follows: Figure 1 As shown. The RF signal is received by the antenna, filtered and amplified by the bandpass filter (BPF) and the low noise amplifier (LNA), and then the RF signal is divided into two paths and enters the mixer. At the same time, the oscillator generates a local oscillator signal, one of which directly enters the mixer I, and the other local oscillator signal enters the mixer Q after passing through the phase shifter. The function of the phase shifter is to make the local oscillator signal passing through the phase shifter shift by 90 degrees, so as to achieve the orthogonality of the two local oscillator signals. Then, the RF signal and the local oscillator signal are down-converted in the mixer. The down-converted signals are filtered and amplified by the low-pass filter (LPF) and the amplifier (AMP) to obtain the I and Q baseband signals. Then, the baseband signals are respectively transmitted to the analog-to-digital converter (ADC) for digital processing, and finally the digitized signals are processed in the baseband processing unit. However, the zero intermediate frequency receiver also has some inherent defects, such as local oscillator leakage and IQ signal imbalance. Among them, IQ signal imbalance refers to the amplitude imbalance and phase imbalance of the demodulated I and Q signals in the direct frequency conversion structure. These imbalances mainly come from two aspects: on the one hand, the amplitude imbalance caused by the inconsistent frequency conversion gains of the two channels; on the other hand, the phase imbalance caused by the inability of the phase shifter to accurately orthogonalize the local oscillator signal.

[0003] The current solutions to the IQ signal imbalance problem of zero intermediate frequency receivers mainly include hardware circuit optimization and software algorithm correction. Hardware circuit optimization is achieved by improving the consistency of devices and optimizing PCB circuits. Although hardware circuit optimization can correct IQ signal imbalance to a certain extent, it is relatively costly and requires the use of high-performance devices, so the cost performance is low. In addition, hardware circuit optimization is uncontrollable, and its correction performance is limited by the inherent characteristics of device and circuit design. Software algorithm correction can be roughly divided into two types: one is a blind estimation software correction algorithm that compensates for the imbalance by analyzing the impact of IQ signal imbalance on signal statistical characteristics, and the other is a non-blind estimation software correction algorithm that estimates IQ signal imbalance parameters by sending a known sequence. Software algorithm correction only needs to compensate the sampled signal through a specific signal processing process in the digital domain. The algorithm used is more flexible and effective, and is the mainstream technical direction of IQ signal imbalance correction. However, the blind estimation software correction algorithm has high implementation complexity, and the non-blind estimation software correction algorithm requires a specific training sequence to assist, which will reduce signal transmission efficiency. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention proposes a method and system for correcting IQ signal imbalance in a zero intermediate frequency receiver. The present invention does not require the assistance of a training sequence, takes into account the advantages of both software and hardware methods, and has a low implementation complexity of the overall solution.

[0005] In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical scheme:

[0006] A method for correcting IQ signal imbalance of a zero intermediate frequency receiver comprises the following steps:

[0007] Step 1: inputting a quadrature modulated RF signal into a zero intermediate frequency receiver;

[0008] Step 2: The radio frequency signal is mixed with two local oscillator signals respectively;

[0009] Step 3: The two signals output by the mixing are respectively passed through a low-pass filter and a variable gain amplifier to output a filtered and amplified signal;

[0010] Step 4: The two filtered and amplified signals are respectively passed through analog-to-digital converters to output analog-to-digital conversion signals;

[0011] Step 5: The two analog-to-digital conversion signals are transmitted to the baseband processing unit, and the power is obtained by square calculation respectively;

[0012] Step 6: Setting the average power threshold of the signal that can be received by the zero intermediate frequency receiver;

[0013] Step 7: Select several sampling points as the calculation interval to obtain the first average power;

[0014] Step 8: Determine the first average power and the average power threshold, and execute step 9 or step 7 according to the determination result;

[0015] Step 9: Select several sampling points as the calculation interval to obtain the second average power;

[0016] Step 10: Determine the magnitude of the second average power and the average power threshold, and execute step 11 or step 9 according to the determination result;

[0017] Step 11, multiplying the two amplitude-corrected analog-to-digital conversion signals to obtain a product;

[0018] Step 12: Select several sampling points as the calculation interval and calculate the average value of the multiplied interval;

[0019] Step 13: Based on the average value, decide to end the calibration process or execute step 12.

[0020] Preferably, in step 1, an orthogonally modulated radio frequency signal r(t) is input to a zero intermediate frequency receiver, as shown in the following formula:

[0021] r(t)=z I (t)cos(2πf c t)-z Q (t)sin(2πf c t) (1)

[0022] In formula (1), z I (t) and z Q (t) represent the real and imaginary parts of the baseband signal respectively, and have the following properties; f c is the carrier frequency; t represents time.

[0023]

[0024] In formula (2), E[·] represents the expectation.

[0025] Preferably, in step 2, the radio frequency signal r(t) is mixed with two local oscillator signals respectively; wherein the two local oscillator signals are respectively represented by x LO_I (t) and x LO_Q (t):

[0026]

[0027] In formula (3), A LO and θ 0 They represent the amplitude and initial phase of the local oscillator signal respectively, θ represents the phase deviation caused by the phase shifter's inability to perform orthogonal phase shift, and │θ│<<πf / 2.

[0028] I channel mixer output M I (t)Signal:

[0029]

[0030] Q mixer output M Q (t)Signal:

[0031]

[0032] Preferably, in step 3, the mixed output signal is respectively passed through a low-pass filter and a variable gain amplifier and then outputted to F I (t) and F Q (t) signal, as shown below:

[0033]

[0034] In formula (6), A I and A Q Represent the cascade gains of the low-pass filters and variable gain amplifiers of the I and Q paths respectively.

[0035] Preferably, in step 4, the filtered and amplified signals are respectively outputted through an analog-to-digital converter D I (n) and D Q (n) signal, as shown below:

[0036]

[0037] In formula (7), n = 1, 2, 3, ...

[0038] Preferably, in step 5, the analog-to-digital converted signal is transmitted to the baseband processing unit, and the power S is obtained by square the signal. I (n) and S Q (n):

[0039]

[0040] Preferably, in step 6, the threshold of the average power of the signal that can be received by the zero intermediate frequency receiver is set to P T , the threshold should ensure that the maximum amplitude of the signal that the analog-to-digital converter can convert is large, and the sampled signal will not overflow; the number of quantization bits of the analog-to-digital converter is set to W, so P T It can be suggested as shown below; Set parameter k I , k Q , The initial value of is 1.

[0041] P T =(2 W-2 -1) 2 (9)

[0042] Preferably, in step 7, L sampling points are taken as the calculation interval, from the current n=(k I -1)L+1, for S in formula (8) I (n) The average power P can be obtained by averaging the segments I (k I ):

[0043]

[0044] Preferably, step eight, if P I (k I )=P T , then execute step nine.

[0045] If P I (k I )≠P T , it is divided into the following situations:

[0046] When k I =1, and P I (k I )>P T When , the baseband processing unit controls the gain of I-channel VGA to decrease by Δ, so that A I =A I -Δ, and k I =k I +1, go back to step 7.

[0047] When k I =1, and P I (k I )<P T When , the baseband processing unit controls the gain of I-channel VGA to increase by Δ, so that A I =A I +Δ, and k I =k I +1, go back to step 7.

[0048] When k I >1, and P I (k I -1)>P T >P I (k I ) or P I (k I -1)<P T <P I (k I ), then execute step nine.

[0049] When k I >1, and P I (k I -1)>PT With P I (k I )>P T When , the baseband processing unit controls the gain of I-channel VGA to decrease by Δ, so that A I =A I -Δ, and k I =k I +1, go back to step 7.

[0050] When k I >1, and P I (k I -1)<P T With P I (k I )<P T When , the baseband processing unit controls the gain of I-channel VGA to increase by Δ, so that A I =A I +Δ, and k I =k I +1, go back to step 7.

[0051] Preferably, in step nine, L sampling points are taken as the calculation interval, from the current n=k I L+(k Q -1)L+1, for S in formula (8) Q (n) The average power P can be obtained by averaging the segments Q (k Q ):

[0052]

[0053] Preferably, step ten, if P Q (k Q )=P T , then execute step eleven.

[0054] If P Q (k Q )≠P T , it is divided into the following situations:

[0055] When k Q =1, and P Q (k Q )>P T When , the baseband processing unit controls the gain of the Q-path VGA to decrease by Δ, so that A Q =A Q -Δ, and k Q =k Q +1, back to step 9.

[0056] When k Q =1, and PQ (k Q )<P T When , the baseband processing unit controls the gain of the Q-path VGA to increase by Δ, so that A Q =A Q +Δ, and k Q =k Q +1, back to step 9.

[0057] When k Q >1, and P Q (k Q -1)>P T >P Q (k Q ) or P Q (k Q -1)<P T <P Q (k Q ), then execute step eleven.

[0058] When k Q >1, and P Q (k Q -1)>P T With P Q (k Q )>P T When , the baseband processing unit controls the gain of the Q-path VGA to decrease by Δ, so that A Q =A Q -Δ, and k Q =k Q +1, back to step 9.

[0059] When k Q >1, and P Q (k Q -1)<P T With P Q (k Q )<P T When , the baseband processing unit controls the gain of the Q-path VGA to increase by Δ, so that A Q =A Q +Δ, and k Q =k Q +1, back to step 9.

[0060] Preferably, in step 11, the amplitude-corrected D I (n) and D Q (n) and we get G(n):

[0061]

[0062] Preferably, in step twelve, take λ sampling points as the calculation interval, from the current First, we calculate the average value of G(n) in equation (12) in sections to obtain

[0063]

[0064] According to the existence of formula (2), when λ is large, the average value It is close to the expectation, so the above formula can be simplified as follows:

[0065]

[0066] Preferably, step 13, if It can be seen that θ=0, and the calibration process ends.

[0067] if The following situations are handled:

[0068] when and When θ>0, the baseband processing unit controls the phase shift of the phase shifter through DAC to reduce Make and Return to step twelve.

[0069] when and When θ < 0, the baseband processing unit controls the phase shift of the phase shifter through the DAC to increase Make and Return to step twelve.

[0070] when and or , the calibration process ends.

[0071] when and and When θ>0, the baseband processing unit controls the phase shift of the phase shifter through DAC to reduce Make and Return to step twelve.

[0072] when and and When θ < 0, the baseband processing unit controls the phase shift of the phase shifter through the DAC to increase Make and Return to step twelve.

[0073] The present invention also discloses a correction system for IQ signal imbalance of a zero intermediate frequency receiver, which is used to execute the above method and includes the following modules:

[0074] RF signal input module: inputs orthogonal modulated RF signal to zero intermediate frequency receiver;

[0075] Mixing module: The RF signal is mixed with two local oscillator signals respectively;

[0076] Filtering and amplifying module: The two signals output by the mixer are respectively passed through a low-pass filter and a variable gain amplifier and then output as filtered and amplified signals;

[0077] Analog-to-digital conversion module: The two filtered and amplified signals are respectively passed through the analog-to-digital converter and then output analog-to-digital conversion signals;

[0078] Power calculation module: The two analog-to-digital conversion signals are transmitted to the baseband processing unit, and the squares are calculated to obtain the power;

[0079] Average power threshold setting module: sets the average power threshold of the signal that the zero intermediate frequency receiver can receive;

[0080] The first average power obtaining module: selects several sampling points as the calculation interval to obtain the first average power;

[0081] A first judging module: judging the first average power and the average power threshold, and executing the judgment by the first average power obtaining module or the second average power obtaining module according to the judgment result;

[0082] Second average power obtaining module: selects several sampling points as calculation intervals to obtain the second average power;

[0083] A second judgment module: judging the second average power and the average power threshold, and executing the second average power obtaining module or the product module according to the judgment result;

[0084] Product module: multiply the two amplitude-corrected analog-to-digital conversion signals to obtain the product;

[0085] Average value calculation module: select several sampling points as the calculation interval and calculate the average value of the multiplied interval;

[0086] The third judgment module: decides to end the correction process or execute it by the average value obtaining module according to the average value.

[0087] Compared with the prior art, the present invention has the following beneficial effects:

[0088] Compared with the existing IQ signal imbalance correction method, the present invention adopts a hardware plus software joint correction method to achieve the correction of IQ signal imbalance through a controllable amplifier and phase shifter. The present invention has low computational complexity and a simple implementation structure; because no training sequence is required for assistance, the signal transmission efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Figure 1 It is a block diagram of the structure of a zero intermediate frequency receiver in the prior art.

[0090] Figure 2 A method for correcting IQ signal imbalance of a zero intermediate frequency receiver according to a preferred embodiment of the present invention involves a circuit block diagram.

[0091] Figure 3 The present invention is a block diagram of a correction system for IQ signal imbalance of a zero intermediate frequency receiver according to a preferred embodiment of the present invention.

[0092] Figure 4 This is the correction simulation diagram under single-tone signal excitation. DETAILED DESCRIPTION

[0093] The specific implementation modes of the present invention are further described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention.

[0094] like Figure 2As shown, it shows the circuit system structure involved in a correction method for IQ signal imbalance of a zero intermediate frequency receiver proposed in a preferred embodiment of the present invention. The radio frequency signal enters the mixer in two ways, and the local oscillator signal is generated by the oscillator at the same time, one local oscillator signal directly enters the mixer I, and the other local oscillator signal enters the mixer Q after passing through the phase shifter. The function of the phase shifter is to make the local oscillator signal passing through the phase shifter shift by 90 degrees, so as to realize the orthogonalization of the two local oscillator signals, and then the radio frequency signal and the local oscillator signal are down-converted in the mixer. The down-converted signals are filtered and amplified by a low-pass filter (LPF) and a variable gain amplifier (VGA) respectively to obtain the I-way and Q-way baseband signals, and then the baseband signals are respectively transmitted to the analog-to-digital converter (ADC) for digital processing, and finally the digitized signals are further processed in the baseband processing unit. Among them, the VGA adopts a programmable gain mode to realize different gain switching, and its control end is connected to the output of the baseband processing unit. The baseband processing unit outputs a gain control word, which is used to adjust the gain of the VGA. The gain step adjusted by the gain control word is ±Δ. The phase shifter consists of two parts: a control voltage and a phase shift network. The control voltage is an adjustable voltage used to control the phase shift, and its voltage is controlled by the baseband processing unit. The baseband processing unit outputs the phase shift control word to the digital-to-analog converter (DAC), which converts it into an analog voltage signal of the corresponding size. The analog voltage signal is input to the varactor diode of the phase shift network, thereby changing the phase shift. The phase shift step adjusted by the phase shift control word is

[0095] Specifically, the present embodiment provides a method for correcting an IQ signal imbalance of a zero intermediate frequency receiver, comprising the following steps:

[0096] Step 1: Input an orthogonally modulated RF signal r(t) to the zero intermediate frequency receiver, as shown in the following equation:

[0097] r(t)=z I (t)cos(2πf c t)-z Q (t)sin(2πf c t) (1)

[0098] In formula (1), z I (t) and z Q (t) represent the real and imaginary parts of the baseband signal respectively, and have the following properties; f c is the carrier frequency; t represents time.

[0099]

[0100] In formula (2), E[·] represents the expectation.

[0101] Step 2: The RF signal r(t) is mixed with two local oscillator signals respectively; wherein the two local oscillator signals are represented as x LO_I (t) and x LO_Q (t):

[0102]

[0103] In formula (3), A LO and θ 0 They represent the amplitude and initial phase of the local oscillator signal respectively, θ represents the phase deviation caused by the phase shifter's inability to perform orthogonal phase shift, and │θ│<<πf / 2.

[0104] I channel mixer output M I (t)Signal:

[0105]

[0106] Q mixer output M Q (t)Signal:

[0107]

[0108] Step 3: The mixed output signal is output through a low-pass filter and a variable gain amplifier. I (t) and F Q (t) signal, as shown below:

[0109]

[0110] In formula (6), A I and A Q Represent the cascade gains of the low-pass filters and variable gain amplifiers of the I and Q paths respectively.

[0111] Step 4: The filtered and amplified signals are outputted through analog-to-digital converters I (n) and D Q (n) signal, as shown below:

[0112]

[0113] In formula (7), n = 1, 2, 3, ...

[0114] Step 5: The analog-to-digital converted signal is transmitted to the baseband processing unit, and the power S is obtained by squaring the signal. I (n) and S Q (n):

[0115]

[0116] Step 6: Set the threshold of the average power of the signal that the zero intermediate frequency receiver can receive to PT , the threshold should ensure that the maximum amplitude of the signal that the analog-to-digital converter can convert is large, and the sampled signal will not overflow; the number of quantization bits of the analog-to-digital converter is set to W, so P T It can be suggested as shown below; Set parameter k I , k Q , The initial value of is 1.

[0117] P T =(2 W-2 -1) 2 (9)

[0118] Step 7: Take L sampling points as the calculation interval, starting from the current n=(k I -1)L+1, for S in formula (8) I (n) The average power P can be obtained by averaging the segments I (k I ):

[0119]

[0120] Step 8: If P I (k I )=P T , then execute step nine.

[0121] If P I (k I )≠P T , it is divided into the following situations:

[0122] When k I =1, and P I (k I )>P T When , the baseband processing unit controls the gain of I-channel VGA to decrease by Δ, so that A I =A I -Δ, and k I =k I +1, go back to step 7.

[0123] When k I =1, and P I (k I )<P T When , the baseband processing unit controls the gain of I-channel VGA to increase by Δ, so that A I =A I +Δ, and k I =k I +1, go back to step 7.

[0124] When k I >1, and PI (k I -1)>P T >P I (k I ) or P I (k I -1)<P T <P I (k I ), then execute step nine.

[0125] When k I >1, and P I (k I -1)>P T With P I (k I )>P T When , the baseband processing unit controls the gain of I-channel VGA to decrease by Δ, so that A I =A I -Δ, and k I =k I +1, go back to step 7.

[0126] When k I >1, and P I (k I -1)<P T With P I (k I )<P T When , the baseband processing unit controls the gain of I-channel VGA to increase by Δ, so that A I =A I +Δ, and k I =k I +1, go back to step 7.

[0127] Step 9: Take L sampling points as the calculation interval, starting from the current n=k I L+(k Q -1)L+1, for S in formula (8) Q (n) The average power P can be obtained by averaging the segments Q (k Q ):

[0128]

[0129] Step 10: If P Q (k Q )=P T , then execute step eleven.

[0130] If P Q (k Q )≠P T , it is divided into the following situations:

[0131] When k Q =1, and P Q (k Q )>P T When , the baseband processing unit controls the gain of the Q-path VGA to decrease by Δ, so that A Q =A Q -Δ, and k Q =k Q +1, back to step 9.

[0132] When k Q =1, and P Q (k Q )<P T When , the baseband processing unit controls the gain of the Q-path VGA to increase by Δ, so that A Q =A Q +Δ, and k Q =k Q +1, back to step 9.

[0133] When k Q >1, and P Q (k Q -1)>P T >P Q (k Q ) or P Q (k Q -1)<P T <P Q (k Q ), then execute step eleven.

[0134] When k Q >1, and P Q (k Q -1)>P T With P Q (k Q )>P T When , the baseband processing unit controls the gain of the Q-path VGA to decrease by Δ, so that A Q =A Q -Δ, and k Q =k Q +1, back to step 9.

[0135] When k Q >1, and P Q (k Q -1)<P T With P Q (k Q )<P T When , the baseband processing unit controls the gain of the Q-path VGA to increase by Δ, so that A Q=A Q +Δ, and k Q =k Q +1, back to step 9.

[0136] Step 11: D after amplitude correction I (n) and D Q (n) and we get G(n):

[0137]

[0138] Step 12: Take λ sampling points as the calculation interval, from the current First, we calculate the average value of G(n) in equation (12) in sections to obtain

[0139]

[0140] According to the existence of formula (2), when λ is large, the average value It is close to the expectation, so the above formula can be simplified as follows:

[0141]

[0142] Step 13: If It can be seen that θ=0, and the calibration process ends.

[0143] if The following situations are handled:

[0144] when and When θ>0, the baseband processing unit controls the phase shift of the phase shifter through DAC to reduce Make and Return to step twelve.

[0145] when and When θ < 0, the baseband processing unit controls the phase shift of the phase shifter through the DAC to increase Make and Return to step twelve.

[0146] when and or , the calibration process ends.

[0147] when and and When θ>0, the baseband processing unit controls the phase shift of the phase shifter through DAC to reduce Make and Return to step twelve.

[0148] when and and When θ < 0, the baseband processing unit controls the phase shift of the phase shifter through the DAC to increase Make and Return to step twelve.

[0149] like Figure 3 As shown, this embodiment discloses a correction system for IQ signal imbalance of a zero intermediate frequency receiver, which is used to execute the above method embodiment and includes the following modules:

[0150] RF signal input module: inputs orthogonal modulated RF signal to zero intermediate frequency receiver;

[0151] Mixing module: The RF signal is mixed with two local oscillator signals respectively;

[0152] Filtering and amplifying module: The two signals output by the mixer are respectively passed through a low-pass filter and a variable gain amplifier and then output as filtered and amplified signals;

[0153] Analog-to-digital conversion module: The two filtered and amplified signals are respectively passed through the analog-to-digital converter and then output analog-to-digital conversion signals;

[0154] Power calculation module: The two analog-to-digital conversion signals are transmitted to the baseband processing unit, and the squares are calculated to obtain the power;

[0155] Average power threshold setting module: sets the average power threshold of the signal that the zero intermediate frequency receiver can receive;

[0156] The first average power obtaining module: selects several sampling points as the calculation interval to obtain the first average power;

[0157] A first judging module: judging the first average power and the average power threshold, and executing the judgment by the first average power obtaining module or the second average power obtaining module according to the judgment result;

[0158] Second average power obtaining module: selects several sampling points as calculation intervals to obtain the second average power;

[0159] A second judgment module: judging the second average power and the average power threshold, and executing the second average power obtaining module or the product module according to the judgment result;

[0160] Product module: multiply the two amplitude-corrected analog-to-digital conversion signals to obtain the product;

[0161] Average value calculation module: select several sampling points as the calculation interval and calculate the average value of the multiplied interval;

[0162] The third judgment module: decides to end the correction process or execute it by the average value obtaining module according to the average value.

[0163] For other contents of this embodiment, please refer to the above method embodiment.

[0164] In summary, the present invention relates to a correction method and system for IQ signal imbalance of a zero intermediate frequency receiver. In order to overcome the problem of IQ signal amplitude and phase imbalance caused by inconsistent two-way frequency conversion gain and inability of phase shifter to orthogonal phase shift in a zero intermediate frequency receiver, the present invention adopts the idea of ​​joint correction of software and hardware, outputs gain and phase shift control words after software algorithm processing in the baseband processing unit, adjusts I-way and Q-way amplifiers in turn through gain control words for amplitude correction, and then adjusts the phase shifter for phase correction after converting the phase shift control words into analog signals. The present invention first performs orthogonal mixing on the radio frequency signal and the local oscillator signal; then filters and amplifies the mixed signals respectively to obtain I-way and Q-way baseband signals; then discretely digitizes the baseband signals respectively; finally, processes the digitized signals in the baseband processing unit, outputs gain control words to complete amplitude correction, and then outputs phase shift control words to complete phase correction. The present invention takes into account the advantages of both software and hardware correction methods, has low computational complexity, simple implementation structure, does not require training sequence assistance, and has high signal transmission efficiency.

[0165] The following takes a single tone signal as an example to demonstrate the method proposed by the present invention through Matlab simulation software.

[0166] The simulation process consists of three parts: signal source generation, IQ signal imbalance setting, and correction algorithm processing. The relevant parameters are set as follows: First, the I and Q baseband signals are randomly constructed; second, the cascade gain of the IQ two channels and the phase deviation of the phase shifter are set to [A I ,A Q ,θ]=[1.2,0.7,2], set the normalized average power threshold to P T =1; Finally, set the gain step and phase shift step to Set the calculation interval of amplitude and phase correction to [L,λ]=[100,1000]. The correction algorithm is used to obtain Figure 4 As shown, (a) is the normalized power diagram of the I-channel baseband signal after correction, (b) is the normalized power diagram of the Q-channel baseband signal after correction, and (c) is the phase deviation diagram of the phase shifter after correction.

[0167] It can be seen from the above simulation results that the proposed correction method can correct the amplitude imbalance caused by the inconsistent IQ two-way frequency conversion gain, and can also correct the phase imbalance caused by the phase shifter's inability to accurately orthogonalize the local oscillator signal.

[0168] The above describes the illustrative specific implementation modes of the present invention to facilitate the understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

Claims

1. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver, characterized in that: The following steps are involved: Step 1: inputting a quadrature modulated RF signal into a zero intermediate frequency receiver; Step 2: The radio frequency signal is mixed with two local oscillator signals respectively; Step 3: The two signals output by the mixing are respectively passed through a low-pass filter and a variable gain amplifier to output a filtered and amplified signal; Step 4: The two filtered and amplified signals are respectively passed through analog-to-digital converters to output analog-to-digital conversion signals; Step 5: The two analog-to-digital conversion signals are transmitted to the baseband processing unit, and the power is obtained by square calculation respectively; Step 6: Setting the average power threshold of the signal that can be received by the zero intermediate frequency receiver; Step 7: Select several sampling points as the calculation interval to obtain the first average power; Step 8: Determine the first average power and the average power threshold, and execute step 9 or step 7 according to the determination result; Step 9: Select several sampling points as the calculation interval to obtain the second average power; Step 10: Determine the magnitude of the second average power and the average power threshold, and execute step 11 or step 9 according to the determination result; Step 11, multiplying the two amplitude-corrected analog-to-digital conversion signals to obtain a product; Step 12: Select several sampling points as the calculation interval and calculate the average value of the multiplied interval; Step 13: Based on the average value, decide to end the calibration process or execute step 12.

2. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 1, characterized in that: Step 1 is as follows: Input an orthogonally modulated RF signal r(t) to the zero intermediate frequency receiver, as shown in the following formula: r(t)=z I (t)cos(2πf c t)-z Q (t)sin(2πf c t) (1) In formula (1), z I (t) and z Q (t) represent the real and imaginary parts of the baseband signal respectively, and have the following properties; f c is the carrier frequency; t represents time; In formula (2), E[·] means to find the expectation; Step 2 is as follows: The RF signal r(t) is mixed with two local oscillator signals respectively; wherein the two local oscillator signals are represented as x LO_I (t) and x LO_Q (t): In formula (3), A LO and θ0 represent the amplitude and initial phase of the local oscillator signal respectively, θ represents the phase deviation caused by the inability of the phase shifter to perform orthogonal phase shift, and │θ│<<πf / 2; I channel mixer output M I (t)Signal: Q mixer output M Q (t)Signal: Step 3 is as follows: The mixed output signal passes through a low-pass filter and a variable gain amplifier to output the signal F I (t) and F Q (t), as shown in the following formula: In formula (6), A I and A Q Represent the cascade gains of the low-pass filters and variable gain amplifiers of the I and Q paths respectively.

3. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 2, characterized in that: Step 4 is as follows: The filtered and amplified signals are respectively passed through the analog-to-digital converter and the output signal D I (n) and D Q (n), as shown in the following formula: In formula (7), n is a natural number; Step 5 is as follows: The analog-to-digital converted signal is transmitted to the baseband processing unit, and the signal is squared to obtain the power S I (n) and S Q (n): Step 6 is as follows: Set the threshold of the average power of the signal that the zero intermediate frequency receiver can receive to P T ; Set the quantization bit number of the analog-to-digital converter to W, P T As shown in the following formula; Set parameter k I , k Q , The initial value of is 1; P T ＝(2 W-2 -1) 2 (9)。 4. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 3, characterized in that: Step 7 is as follows: Take L sampling points as the calculation interval, from the current n = (k I -1)L+1, for S in formula (8) I (n) Segment average to obtain the first average power P I (k I ):

5. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 4, characterized in that: Step 8 is as follows: If P I (k I )=P T , then execute step nine; If P I (k I )≠P T , then the following situations are handled: When k I =1, and P I (k I )>P T When , the baseband processing unit controls the gain of I-channel VGA to decrease by Δ, so that A I =A I -Δ, and k I =k I +1, return to step 7; When k I =1, and P I (k I )<P T When , the baseband processing unit controls the gain of I-channel VGA to increase by Δ, so that A I =A I +Δ, and k I =k I +1, return to step 7; When k I >1, and P I (k I -1)>P T >P I (k I ) or P I (k I -1)<P T <P I (k I ), then execute step nine; When k I >1, and P I (k I -1)>P T With P I (k I )>P T When , the baseband processing unit controls the gain of I-channel VGA to decrease by Δ, so that A I =A I -Δ, and k I =k I +1, return to step 7; When k I >1, and P I (k I -1)<P T With P I (k I )<P T When , the baseband processing unit controls the gain of I-channel VGA to increase by Δ, so that A I =A I +Δ, and k I =k I +1, return to step 7.

6. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 5, characterized in that: Step 9 is as follows: Take L sampling points as the calculation interval, from the current n = k I L+(k Q -1)L+1, for S in formula (8) Q (n) The second average power P is obtained by averaging the segments Q (k Q ):

7. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 6, characterized in that: Step 10 is as follows: If P Q (k Q )=P T , then execute step 11; If P Q (k Q )≠P T , then the following situations are handled: When k Q =1, and P Q (k Q )>P T When , the baseband processing unit controls the gain of the Q-path VGA to decrease by Δ, so that A Q =A Q -Δ, and k Q =k Q +1, return to step 9; When k Q =1, and P Q (k Q )<P T When , the baseband processing unit controls the gain of the Q-path VGA to increase by Δ, so that A Q =A Q +Δ, and k Q =k Q +1, return to step 9; When k Q >1, and P Q (k Q -1)>P T >P Q (k Q ) or P Q (k Q -1)<P T <P Q (k Q ), then execute step 11; When k Q >1, and P Q (k Q -1)>P T With P Q (k Q )>P T When , the baseband processing unit controls the gain of the Q-path VGA to decrease by Δ, so that A Q =A Q -Δ, and k Q =k Q +1, return to step 9; When k Q >1, and P Q (k Q -1)<P T With P Q (k Q )<P T When , the baseband processing unit controls the gain of the Q-path VGA to increase by Δ, so that A Q =A Q +Δ, and k Q =k Q +1, return to step 9; Step 11 is as follows: D I (n) and D Q (n) and we get the product G(n):

8. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 7, characterized in that: Step 12 is as follows: Take λ sampling points as the calculation interval, from the current First, we calculate the average value of G(n) in equation (12) in sections to obtain According to formula (2), the above formula can be simplified as follows:

9. A method for correcting IQ signal imbalance of a zero intermediate frequency receiver as claimed in claim 8, characterized in that: Step 13 is as follows: If Knowing that θ = 0, the calibration process ends; if The following situations are handled: when and When θ>0, the baseband processing unit controls the phase shift of the phase shifter through DAC to reduce Make and Return to step 12; when and When θ < 0, the baseband processing unit controls the phase shift of the phase shifter through DAC to increase Make and Return to step 12; when and or When , the calibration process ends; when and and When θ>0, the baseband processing unit controls the phase shift of the phase shifter through DAC to reduce Make and Return to step 12; when and and When θ < 0, the baseband processing unit controls the phase shift of the phase shifter through DAC to increase Make and Return to step 12.

10. A correction system for IQ signal imbalance of a zero intermediate frequency receiver, used to execute the method according to any one of claims 1 to 9, characterized in that: Includes the following modules: RF signal input module: inputs orthogonal modulated RF signal to zero intermediate frequency receiver; Mixing module: The RF signal is mixed with two local oscillator signals respectively; Filtering and amplifying module: The two signals output by the mixer are respectively passed through a low-pass filter and a variable gain amplifier and then output as filtered and amplified signals; Analog-to-digital conversion module: The two filtered and amplified signals are respectively passed through the analog-to-digital converter and then output analog-to-digital conversion signals; Power calculation module: The two analog-to-digital conversion signals are transmitted to the baseband processing unit, and the squares are calculated to obtain the power; Average power threshold setting module: sets the average power threshold of the signal that the zero intermediate frequency receiver can receive; The first average power obtaining module: selects several sampling points as the calculation interval to obtain the first average power; A first judging module: judging the first average power and the average power threshold, and executing the judgment by the first average power obtaining module or the second average power obtaining module according to the judgment result; Second average power obtaining module: selects several sampling points as calculation intervals to obtain the second average power; A second judgment module: judging the second average power and the average power threshold, and executing the second average power obtaining module or the product module according to the judgment result; Product module: multiply the two amplitude-corrected analog-to-digital conversion signals to obtain the product; Average value calculation module: select several sampling points as the calculation interval and calculate the average value of the multiplied interval; The third judgment module: decides to end the correction process or execute it by the average value obtaining module according to the average value.

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