Circuit board and manufacturing method thereof

Abstract

A circuit board comprises a first circuit layer, a second circuit layer, a third circuit layer, a first differential line group, a second differential line group, a third differential line group and a fourth differential line group. The first differential line group and the third differential line group are arranged between the first circuit layer and the second circuit layer. The second differential line group and the fourth differential line group are arranged between the first circuit layer and the third circuit layer. A first distance is formed between the first differential line group and the first circuit layer, a second distance is formed between the second differential line group and the first circuit layer, a third distance is formed between the third differential line group and the first circuit layer, a fourth distance is formed between the fourth differential line group and the first circuit layer, and the first distance is smaller than the third distance; the second distance is smaller than the fourth distance. The conductive structure of the differential line is composed of graphene, and the insulating structure of the differential line is composed of graphene oxide, so that the circuit board can reduce signal loss, and has a certain degree of heat resistance in a high-temperature environment.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board formed of graphene, graphene oxide and liquid metal and a manufacturing method thereof. Background Art

[0002] In the field of high-frequency transmission line technology, traditional circuit boards usually use via structures to achieve signal shielding, and common transmission line structures include microstrip and stripline structures. However, via structures will lead to impedance discontinuity, and the electromagnetic shielding structures in microstrip and stripline cannot achieve all-round shielding of electromagnetic interference (EMI).

[0003] In addition, the roughness of the conductor structure of the circuit board will also affect the signal shielding effect. If the roughness of the conductor structure is high, coupled with the skin effect of electrons, the conductor loss will be further increased, thereby affecting the signal shielding effect. In view of the above, it is currently urgent to develop a fully shielded circuit board and its manufacturing method to overcome the above shortcomings. Summary of the invention

[0004] At least one embodiment of the present invention provides a circuit board and a method for manufacturing the same. The conductive structure of the differential line of the present invention is composed of graphene, and the insulating structure of the differential line is composed of graphene oxide. Graphene has the characteristics of high conductivity, high thermal conductivity and low roughness, so it can reduce signal loss. Graphene oxide is an insulator and can also reduce the impact of roughness on high-frequency signals. The liquid metal-coated (three-dimensional surround) differential line of the present invention enables each group of transmission lines to have a separate shielding structure to achieve all-round shielding of signals.

[0005] The circuit board provided by at least one embodiment of the present invention comprises a first circuit layer, a second circuit layer, a third circuit layer, a first differential line group, a second differential line group, a third differential line group and a fourth differential line group. The first circuit layer is disposed between the second circuit layer and the third circuit layer. The first differential line group is disposed between the first circuit layer and the second circuit layer. The second differential line group is disposed between the first circuit layer and the third circuit layer. The third differential line group is disposed between the first circuit layer and the second circuit layer. The fourth differential line group is disposed between the first circuit layer and the third circuit layer. The first differential line group has a first orthographic projection on the first circuit layer, the second differential line group has a second orthographic projection on the first circuit layer, the third differential line group has a third orthographic projection on the first circuit layer, and the fourth differential line group has a fourth orthographic projection on the first circuit layer, wherein the first orthographic projection is separated from the third orthographic projection, and the second orthographic projection is separated from the fourth orthographic projection. There is a first distance between the first differential line group and the first circuit layer, a second distance between the second differential line group and the first circuit layer, a third distance between the third differential line group and the first circuit layer, and a fourth distance between the fourth differential line group and the first circuit layer, wherein the first distance is smaller than the third distance, and the second distance is smaller than the fourth distance.

[0006] In at least one embodiment of the present invention, each of the first differential line group, the second differential line group, the third differential line group, and the fourth differential line group includes two differential lines.

[0007] In at least one embodiment of the present invention, the circuit board further comprises a liquid metal structure. The liquid metal structure covers each differential line, wherein the liquid metal structure is distributed between the first circuit layer, the second circuit layer and the third circuit layer.

[0008] In at least one embodiment of the present invention, each differential line includes a conductive structure and an insulating structure, wherein the conductive structure is composed of graphene, and the insulating structure surrounds the conductive structure, wherein the insulating structure is composed of graphene oxide.

[0009] In at least one embodiment of the present invention, the circuit board further comprises a first insulating layer, a first adhesive layer, a second insulating layer and a second adhesive layer. The first insulating layer is disposed between the first circuit layer and the second circuit layer, wherein the first insulating layer surrounds the liquid metal structure. The first adhesive layer is disposed between the first insulating layer and the second circuit layer. The second insulating layer is disposed between the first circuit layer and the third circuit layer, wherein the second insulating layer surrounds the liquid metal structure. The second adhesive layer is disposed between the second insulating layer and the third circuit layer.

[0010] The manufacturing method of the circuit board provided by at least one embodiment of the present invention comprises the following steps. A first circuit layer is provided. A first patterned insulating layer is formed on the first surface of the first circuit layer, wherein the first patterned insulating layer comprises a plurality of first grooves. A second patterned insulating layer is formed on the second surface of the first circuit layer, wherein the second patterned insulating layer comprises a plurality of second grooves, wherein one of the plurality of first grooves is connected to one of the plurality of second grooves. A first liquid metal layer is formed on a portion of the first patterned insulating layer. A second liquid metal layer is formed on a portion of the second patterned insulating layer. A first differential line group is formed on a portion of the first liquid metal layer. A second differential line group is formed on a portion of the second liquid metal layer. A third patterned insulating layer is formed, wherein the third patterned insulating layer comprises a plurality of third grooves, and the plurality of first grooves are connected to the plurality of third grooves. A fourth patterned insulating layer is formed, wherein the fourth patterned insulating layer comprises a plurality of fourth grooves, and the plurality of second grooves are connected to the plurality of fourth grooves. A third liquid metal layer is formed on the first differential line group. A fourth liquid metal layer is formed on the second differential line group. A second circuit layer is formed on the first differential line group. The third circuit layer is formed on the second differential line group. After the second circuit layer and the third circuit layer are formed, the liquid metal material is filled in the first, second, third and fourth grooves. The holes in the second circuit layer are sealed.

[0011] In at least one embodiment of the present invention, the step of forming the first differential line group includes the following steps: forming a conductive structure on the first liquid metal layer, wherein the conductive structure is composed of graphene; forming an insulating structure on the conductive structure and surrounding the conductive structure, wherein the insulating structure is composed of graphene oxide.

[0012] In at least one embodiment of the present invention, the manufacturing method of the above-mentioned circuit board further includes the following steps: forming a third differential line group on a portion of the third liquid metal layer; forming a fourth differential line group on a portion of the fourth liquid metal layer; forming a fifth patterned insulating layer, wherein the fifth patterned insulating layer includes a plurality of fifth grooves, and the plurality of third grooves are connected to the plurality of fifth grooves; forming a sixth patterned insulating layer, wherein the sixth patterned insulating layer includes a plurality of sixth grooves, and the plurality of fourth grooves are connected to the plurality of sixth grooves; forming a fifth liquid metal layer on the third differential line group; forming a sixth liquid metal layer on the fourth differential line group, wherein the liquid metal material is also filled in the plurality of fifth and sixth grooves.

[0013] In at least one embodiment of the present invention, the first, second, third and fourth liquid metal layers are formed by sputtering.

[0014] In at least one embodiment of the present invention, the step of sealing the holes in the second circuit layer is performed at room temperature and in a vacuum environment.

[0015] The circuit board of the present invention has a certain degree of heat resistance in a high temperature environment. Due to the characteristics of liquid metal, liquid metal can undergo phase change reaction in a relatively high temperature environment. Since the graphene material and the graphene oxide material are used as the transmission line conductor and the insulating layer structure respectively, the circuit board of the present case has a design suitable for use in a relatively high temperature environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] When read in conjunction with the accompanying drawings, the various aspects of the present application can be best understood according to the following detailed description. It should be understood that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features can be arbitrarily increased or reduced for clarity.

[0017] Figures 1 to 12 Schematic cross-sectional view of a circuit board in various stages of a process according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0018] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of the elements (such as insulating layers, circuit layers and through holes, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes and deviations thereof caused by actual processes and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, while the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.

[0019] In addition, spatially relative terms such as "below," "below," "below," "above," "above," and other similar terms are used to facilitate describing the relationship between one element or feature and another element or feature in the figure. In addition to the orientation depicted in the figure, the spatially relative terms also cover other orientations of the device when in use or operation. That is, when the orientation of the device is different from the figure (rotated 90 degrees or in other orientations), the spatially relative terms used in this disclosure can also be interpreted accordingly.

[0020] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the embodiment, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0021] The terms "approximately", "approximately", "essentially", or "substantially" used herein may be selected based on the optical properties, etching properties, mechanical properties, measurement properties, coating properties, or other properties to select a more acceptable deviation range or standard deviation, and may not apply to all properties with one standard deviation. It should be noted that the first direction D1 and the second direction D2 are marked in the drawings of the present case to show the configuration relationship of the components in the drawings, and the first direction D1 and the second direction D2 are substantially perpendicular to each other.

[0022] Figures 1 to 12 FIG. 1 is a schematic cross-sectional view of a circuit board 100a in various stages of a process according to at least one embodiment of the present invention, wherein Fig.12 The circuit board 100a is shown. Figure 1 , the first circuit layer 110 has a first surface s1 and a second surface s2. The first insulating layer 111 is formed on the first surface s1, and the second insulating layer 112 is formed on the second surface s2. In other words, the first circuit layer 110 is sandwiched between the first insulating layer 111 and the second insulating layer 112. The first circuit layer 110, the first insulating layer 111, and the second insulating layer 112 are stacked along the first direction D1.

[0023] In this embodiment, the first circuit layer 110 is formed by etching a metal layer (eg, copper foil of a copper foil substrate), so the first circuit layer 110 is formed by a subtractive method. Figure 1 As shown, the first circuit layer 110 has a through hole H1. In this embodiment, the first insulating layer 111 and the second insulating layer 112 are photosensitive insulating materials, such as photo-imageable dielectric (PID). In this embodiment, the first insulating layer 111 and the second insulating layer 112 are formed on two opposite sides of the first circuit layer 110 by laminating.

[0024] Please refer to Figure 2 The first insulating layer 111 and the second insulating layer 112 are exposed and developed to form a first patterned insulating layer 111a and a second patterned insulating layer 112a, so that the first patterned insulating layer 111a is disposed on the first surface s1 of the first circuit layer 110, and the second patterned insulating layer 112a is disposed on the second surface s2 of the first circuit layer 110. The first patterned insulating layer 111a includes a plurality of first grooves R1, and the second patterned insulating layer 112a includes a plurality of second grooves R2, wherein one of the plurality of first grooves R1 is connected to one of the plurality of second grooves R2 through a through hole H1, as shown in FIG. Figure 2 shown.

[0025] Please refer to Figure 3, the first liquid metal layer 113 is formed on a portion of the first patterned insulating layer 111a, and the second liquid metal layer 114 is formed on a portion of the second patterned insulating layer 112a, wherein the first patterned insulating layer 111a and the second patterned insulating layer 112a are located between the first liquid metal layer 113 and the second liquid metal layer 114. In this embodiment, the first liquid metal layer 113 and the second liquid metal layer 114 are formed by sputtering. Figure 3 In the embodiment of FIG. 1 , the first liquid metal layer 113 and the second liquid metal layer 114 are in solid state.

[0026] In some embodiments, the first liquid metal layer 113 and the second liquid metal layer 114 are composed of liquid metals of silver (Ag, melting point 961.8°C), gallium (Ga, melting point 29.76°C), rubidium (Rb, melting point 38.89°C), cesium (Cs, melting point 28.44°C), mercury (Hg, melting point -38.86°C), francium (Fr, melting point 27°C) or alloys thereof. The present invention utilizes the phase change (i.e., conversion between solid and liquid) characteristics of liquid metal to allow the liquid metal to encapsulate the subsequently formed differential lines.

[0027] Still refer to Figure 3 , an insulating layer 115 is formed on the first liquid metal layer 113, and a conductive layer 117 is formed on the insulating layer 115. Similarly, an insulating layer 116 is formed on the second liquid metal layer 114, and a conductive layer 118 is formed on the insulating layer 116. It is worth noting that Figure 3 As shown, the width of the insulating layer 115 is greater than the width of the conductive layer 117 , and the width of the insulating layer 116 is greater than the width of the conductive layer 118 .

[0028] Please refer to Figure 4 , the insulating layer 119 covers the conductive layer 117, so that the insulating layer 119 and the insulating layer 115 surround the conductive layer 117. Similarly, the insulating layer 120 covers the conductive layer 118, so that the insulating layer 120 and the insulating layer 116 surround the conductive layer 118. In addition, Figure 4 The insulating layer 119 and the insulating layer 120 may both be U-shaped.

[0029] In some embodiments, the conductive layer 117 and the conductive layer 118 are composed of graphene. Graphene has the characteristic of high conductivity, therefore, the conductive layer 117 and the conductive layer 118 are conductive structures with conductive properties. It should be noted that the "graphene" material herein includes graphene fibers, graphene films and graphene aerogels. Since graphene has the characteristics of high conductivity, high thermal conductivity and low roughness, signal loss can be reduced. In this embodiment, the heat-resistant temperature of graphene is about 400°C. In this embodiment, the conductive layer 117 and the conductive layer 118 are formed by deposition.

[0030] In some embodiments, the insulating layer 119 and the insulating layer 115 are composed of graphene oxide (GO), and the insulating layer 120 and the insulating layer 116 are composed of graphene oxide. Since graphene oxide is an insulator, it can be understood that the insulating layer 119 and the insulating layer 115 together form an insulating structure, and the insulating layer 120 and the insulating layer 116 together form an insulating structure. In addition, due to its structural characteristics, graphene oxide can reduce the impact of roughness on high-frequency signals, thereby reducing signal loss. In the present embodiment, the heat-resistant temperature of graphene oxide is about 400°C. In the present embodiment, the insulating layer 115, the insulating layer 116, the insulating layer 119 and the insulating layer 120 are formed by deposition.

[0031] Figure 4 Two conductive layers 117, two insulating layers 115 and two insulating layers 119 (ie, two conductive structures and two insulating structures) are shown, which may be referred to as a “first differential line set DL1”. In other words, the first differential line set DL1 includes two differential lines, wherein Figure 4 The conductive layer 117 shown is a partial cross section of the differential line. Figure 4 As shown, the first differential line group DL1 is disposed on a portion of the first liquid metal layer 113 .

[0032] Figure 4 FIG. 2 shows two conductive layers 118, two insulating layers 116 and two insulating layers 120 (ie, two conductive structures and two insulating structures), which may be referred to as a “second differential line group DL2”. In other words, the second differential line group DL2 includes two differential lines, wherein Figure 4 The conductive layer 118 shown is a partial cross section of the differential line. Figure 4 As shown, the second differential line group DL2 is disposed on a portion of the second liquid metal layer 114 .

[0033] Please refer to Figure 5, the third insulating layer 121 is formed on the insulating layer 119 and covers the insulating layer 119. The third insulating layer 121 also covers a plurality of first grooves R1, so that the plurality of first grooves R1 are buried in the first patterned insulating layer 111a to form a cavity. The fourth insulating layer 122 is formed on the insulating layer 120 and covers the insulating layer 120. The fourth insulating layer 122 also covers a plurality of second grooves R2, so that the plurality of second grooves R2 are buried in the second patterned insulating layer 112a to form a cavity. In some embodiments, the materials of the third insulating layer 121 and the fourth insulating layer 122 are the same or similar to the materials of the first insulating layer 111 and the second insulating layer 112. In this embodiment, the third insulating layer 121 and the fourth insulating layer 122 are formed by laminating.

[0034] Please refer to Figure 6 The third insulating layer 121 and the fourth insulating layer 122 are exposed and developed to form a third patterned insulating layer 121a and a fourth patterned insulating layer 122a. The third patterned insulating layer 121a includes a plurality of third grooves R3 and a plurality of first grooves R1 (see Figure 5 ) are connected to the plurality of third grooves R3 respectively. The fourth patterned insulating layer 122a includes a plurality of fourth grooves R4, and a plurality of second grooves R2 (please refer to Figure 5 ) are connected to a plurality of fourth grooves R4 respectively. It is worth noting that the third patterned insulating layer 121a exposes the first differential line group DL1, and the fourth patterned insulating layer 122a exposes the second differential line group DL2.

[0035] Please refer to Figure 7 The third liquid metal layer 123 is formed on the first differential line group DL1 and covers a portion of the third patterned insulating layer 121a (eg Figure 7 The fourth liquid metal layer 124 is formed on the second differential line group DL2 and covers a portion of the fourth patterned insulating layer 122a (as shown in the right side of FIG. 1 ). Figure 7 The first differential line group DL1 and the second differential line group DL2 are located between the third liquid metal layer 123 and the fourth liquid metal layer 124. The materials and the forming methods of the third liquid metal layer 123 and the fourth liquid metal layer 124 are the same or similar to the materials and the forming methods of the first liquid metal layer 113 and the second liquid metal layer 114.

[0036] Still refer to Figure 7 , an insulating layer 125 is formed on a portion of the third liquid metal layer 123, and a conductive layer 127 is formed on the insulating layer 125. Similarly, an insulating layer 126 is formed on a portion of the fourth liquid metal layer 124, and a conductive layer 128 is formed on the insulating layer 126. It is worth noting that Figure 7As shown, the width of the insulating layer 125 is greater than the width of the conductive layer 127 , and the width of the insulating layer 126 is greater than the width of the conductive layer 128 .

[0037] Please refer to Figure 8 , the insulating layer 129 covers the conductive layer 127, so that the insulating layer 129 and the insulating layer 125 surround the conductive layer 127. Similarly, the insulating layer 130 covers the conductive layer 128, so that the insulating layer 130 and the insulating layer 126 surround the conductive layer 128. In addition, Figure 8 The insulating layer 129 and the insulating layer 130 in the embodiment may be U-shaped. The conductive layer 127 and the conductive layer 128 are composed of graphene. In the present embodiment, the conductive layer 127 and the conductive layer 128 are formed by deposition. The insulating layer 125, the insulating layer 126, the insulating layer 129 and the insulating layer 130 are composed of graphene oxide. In the present embodiment, the insulating layer 125, the insulating layer 126, the insulating layer 129 and the insulating layer 130 are formed by deposition.

[0038] Figure 8 FIG. 2 shows two conductive layers 127, two insulating layers 125 and two insulating layers 129 (ie, two conductive structures and two insulating structures), which may be referred to as a “third differential line group DL3”. In other words, the third differential line group DL3 includes two differential lines, wherein Figure 8 The conductive layer 127 shown is a partial cross section of the differential line. Figure 8 As shown, the third differential line group DL3 is disposed on a portion of the third liquid metal layer 123 .

[0039] Figure 8 FIG. 4 shows two conductive layers 128, two insulating layers 126 and two insulating layers 130 (ie, two conductive structures and two insulating structures), which may be referred to as a “fourth differential line group DL4”. In other words, the fourth differential line group DL4 includes two differential lines, wherein Figure 8 The conductive layer 128 shown is a partial cross section of the differential line. Figure 8 As shown, the fourth differential line group DL4 is disposed on a portion of the fourth liquid metal layer 124 .

[0040] Please refer to Fig. 9, the fifth insulating layer 131 is formed on the insulating layer 129 and covers the insulating layer 129. The fifth insulating layer 131 also covers a plurality of third grooves R3, so that the plurality of third grooves R3 are buried in the third patterned insulating layer 121a to form a cavity. The sixth insulating layer 132 is formed on the insulating layer 130 and covers the insulating layer 130. The sixth insulating layer 132 also covers a plurality of fourth grooves R4, so that the plurality of fourth grooves R4 are buried in the fourth patterned insulating layer 122a to form a cavity. In some embodiments, the materials of the fifth insulating layer 131 and the sixth insulating layer 132 are the same or similar to the materials of the first insulating layer 111 and the second insulating layer 112. In the present embodiment, the fifth insulating layer 131 and the sixth insulating layer 132 are formed by laminating.

[0041] Please refer to Fig.10 The fifth insulating layer 131 and the sixth insulating layer 132 are exposed and developed to form a fifth patterned insulating layer 131a and a sixth patterned insulating layer 132a. It is worth noting that the fifth patterned insulating layer 131a exposes the third differential line group DL3, and the sixth patterned insulating layer 132a exposes the fourth differential line group DL4.

[0042] The fifth patterned insulating layer 131a includes a plurality of fifth grooves R5 and a plurality of third grooves R3 (see Fig. 9 ) are connected to the plurality of fifth grooves R5. The sixth patterned insulating layer 132a includes a plurality of sixth grooves R6, and a plurality of fourth grooves R4 (please refer to Fig. 9 ) are connected to a plurality of sixth grooves R6. In this embodiment, the first groove R1 (please refer to Figure 2 )、The third groove R3 (please refer to Figure 6 ) and the fifth groove R5 (please refer to Fig.10 ) are aligned with each other, and the second groove R2 (please refer to Figure 2 )、The fourth groove R4 (please refer to Figure 6 ) and the sixth groove R6 (please refer to Fig.10 ) are aligned with each other.

[0043] It should be noted that the first patterned insulating layer 111a, the third patterned insulating layer 121a and the fifth patterned insulating layer 131a may be collectively referred to as an insulating layer IN1, and the second patterned insulating layer 112a, the fourth patterned insulating layer 122a and the sixth patterned insulating layer 132a may be collectively referred to as an insulating layer IN2.

[0044] Please refer to Fig.11, the fifth liquid metal layer 133 is formed on the third differential line group DL3, and the sixth liquid metal layer 134 is formed on the fourth differential line group DL4, wherein the third differential line group DL3 and the fourth differential line group DL4 are located between the fifth liquid metal layer 133 and the sixth liquid metal layer 134. The material and the forming method of the fifth liquid metal layer 133 and the sixth liquid metal layer 134 are the same or similar to the material and the forming method of the first liquid metal layer 113 and the second liquid metal layer 114.

[0045] Then, the second circuit layer 137 is disposed on the fifth patterned insulating layer 131a and the fifth liquid metal layer 133 through the adhesive layer 135, so that a plurality of grooves (such as the first groove R1, the third groove R3 and the fifth groove R5) are buried in the patterned insulating layer (such as Fig.10 The third circuit layer 138 is disposed on the sixth patterned insulating layer 132a and the sixth liquid metal layer 134 through the adhesive layer 136, so that a plurality of grooves (such as the second groove R2, the fourth groove R4 and the sixth groove R6) are buried in the patterned insulating layer (such as Fig.10 In the insulating layer IN2, a cavity is formed. In this embodiment, the second circuit layer 137 and the third circuit layer 138 are formed by laminating. In some embodiments, the materials of the adhesive layer 135 and the adhesive layer 136 are epoxy resin glue or other polymer glue. In some embodiments, the heat-resistant temperature of the adhesive layer 135 and the adhesive layer 136 is 180°C to 320°C.

[0046] It is worth noting that the second circuit layer 137 has at least one through hole H2, wherein the through hole H2 is connected to the fifth groove R5 (please refer to Fig.10 ). The through hole H2 is a subsequent liquid metal material 139 (see Fig.12 ) is used to fill the subsequent liquid metal material 139 (see Fig.12 ).

[0047] Please refer to Fig.11 and Fig.12 The liquid metal material 139 is modulated into a liquid metal material having a specific fluidity, a specific viscosity, or a molten state under a processing environment. The liquid metal material 139 is injected into a plurality of grooves in a pressurized environment (the pressure is designed according to the required parameters), and then cooled and formed. During the injection of the liquid metal material 139, a post-processing step (for example, infrared heating or sintering) may be optionally used to make the liquid metal material (including the material of the liquid metal layer) dense, thereby improving reliability.

[0048] Specifically, the liquid metal material 139 is filled into the first groove R1, the second groove R2, the third groove R3, the fourth groove R4, the fifth groove R5 and the sixth groove R6 through the through hole H2, thereby forming Fig.12 The circuit board 100a is then cooled and formed. Fig.11 The circuit board 100 is placed in a pressurized environment (and optionally a post-processing step), so that the first liquid metal layer 113, the second liquid metal layer 114, the third liquid metal layer 123, the fourth liquid metal layer 124, the fifth liquid metal layer 133 and the sixth liquid metal layer 134 have a specific fluidity, a specific viscosity, or are in a molten state, so Fig.11 The multiple grooves are connected to each other.

[0049] Then, the liquid metal material 139 flows and fills the plurality of grooves (eg, the first groove R1 to the sixth groove R6) through the height difference. Fig.12 In this embodiment, the material of the first liquid metal layer 113 to the sixth liquid metal layer 134 is the same as the material of the liquid metal material 139 .

[0050] It is understood that after the liquid metal material 139 is formed in the plurality of grooves, the temperature is lowered so that the liquid metal material becomes solid. Therefore, the liquid metal material 139 and the original first liquid metal layer 113 to the sixth liquid metal layer 134 form a liquid metal structure. The liquid metal structure covers each differential line, wherein the liquid metal structure is distributed between the first circuit layer 110, the second circuit layer 137 and the third circuit layer 138. It should be understood that the term "covering" herein means covering at least three planes of the three-dimensional structure, for example, six planes. The insulating layer IN1 and the insulating layer IN2 (please refer to Fig.10 ) around the liquid metal structure.

[0051] Please refer to Fig.12 After the liquid metal material 139 is filled in the plurality of grooves, the sealant 140 is used to seal the through hole H2 in the second circuit layer 137. In some embodiments, the step of sealing the through hole H2 in the second circuit layer 137 is performed at room temperature and in a vacuum environment.

[0052] Since each differential line is covered by the liquid metal structure, each differential line group has a separate shielding structure, thereby reducing signal loss. In addition, the liquid metal structure connects the first circuit layer 110, the second circuit layer 137 and the third circuit layer 138, so that the liquid metal structure is grounded, so the structure of the circuit board 100a can be improved, thereby reducing signal loss.

[0053] Please refer again Fig.12The circuit board 100a includes a first circuit layer 110, a second circuit layer 137, a third circuit layer 138, a first differential line group DL1, a second differential line group DL2, a third differential line group DL3, and a fourth differential line group DL4. The first circuit layer 110 is disposed between the second circuit layer 137 and the third circuit layer 138. The first differential line group DL1 is disposed between the first circuit layer 110 and the second circuit layer 137. The second differential line group DL2 is disposed between the first circuit layer 110 and the third circuit layer 138. The third differential line group DL3 is disposed between the first circuit layer 110 and the second circuit layer 137. The fourth differential line group DL4 is disposed between the first circuit layer 110 and the third circuit layer 138.

[0054] like Fig.12 As shown, the first differential line group DL1 is arranged along the first horizontal line HL1, the second differential line group DL2 is arranged along the second horizontal line HL2, the third differential line group DL3 is arranged along the third horizontal line HL3, and the fourth differential line group DL4 is arranged along the fourth horizontal line HL4, wherein the first horizontal line HL1, the second horizontal line HL2, the third horizontal line HL3 and the fourth horizontal line HL4 extend in a direction parallel to the second direction D2, and the first horizontal line HL1, the second horizontal line HL2, the third horizontal line HL3 and the fourth horizontal line HL4 are separated from each other. The third horizontal line HL3 is higher than the first horizontal line HL1, the first horizontal line HL1 is higher than the second horizontal line HL2, and the second horizontal line HL2 is higher than the fourth horizontal line HL4.

[0055] In other words, the first differential line group DL1 to the fourth differential line group DL4 have height differences, so that each differential line group is not on the same plane, which can avoid signal interference between differential lines (transmission lines). Fig.12 As shown, the first differential line group DL1 to the fourth differential line group DL4 have a mirror-symmetric structure with the first line layer 110 as the symmetry axis. Each of the first differential line group DL1 to the fourth differential line group DL4 may have different functions, such as different transmission frequencies. In some embodiments, the thickness of the conductive structure (e.g., conductive layer 117, conductive layer 118, conductive layer 127, and conductive layer 128) of each of the first differential line group DL1 to the fourth differential line group DL4 may be different.

[0056] Please refer to Fig.12The first differential line group DL1 has a first orthographic projection (not shown) on the first circuit layer 110, the second differential line group DL2 has a second orthographic projection (not shown) on the first circuit layer 110, the third differential line group DL3 has a third orthographic projection (not shown) on the first circuit layer 110, and the fourth differential line group DL4 has a fourth orthographic projection (not shown) on the first circuit layer 110, wherein the first orthographic projection is separated from the third orthographic projection, and the second orthographic projection is separated from the fourth orthographic projection.

[0057] It is understood that the term “orthogonal projection” herein refers to the projection of the first differential line group DL1 to the fourth differential line group DL4 on the first surface s1 or the second surface s2 of the first circuit layer 110 along the direction parallel to the first direction D1, just like the projection of a virtual light beam irradiating the first differential line group DL1 to the fourth differential line group DL4 on the first surface s1 or the second surface s2 of the first circuit layer 110 along the direction parallel to the first direction D1.

[0058] like Fig.12 As shown, there is a first distance d1 between the first differential line group DL1 and the first circuit layer 110, a second distance d2 between the second differential line group DL2 and the first circuit layer 110, a third distance d3 between the third differential line group DL3 and the first circuit layer 110, and a fourth distance d4 between the fourth differential line group DL4 and the first circuit layer 110, wherein the first distance d1 is less than the third distance d3, and the second distance d2 is less than the fourth distance d4. In some embodiments, the first distance d1 is substantially equal to the second distance d2, and the third distance d3 is substantially equal to the fourth distance d4.

[0059] In summary, the conductive structure of the differential line of the present invention is composed of graphene, and the insulating structure of the differential line is composed of graphene oxide. Graphene has the characteristics of high conductivity, high thermal conductivity and low roughness, so it can reduce signal loss. Graphene oxide is an insulator and can also reduce the impact of roughness on high-frequency signals. The liquid metal-coated (three-dimensional surround) differential line of the present invention enables each group of transmission lines to have a separate shielding structure to achieve all-round shielding of signals.

[0060] The features of multiple embodiments are summarized above so that those skilled in the art can better understand the aspects of the present application. Those skilled in the art should understand that the present application can be easily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present application, and various changes, substitutions and modifications of the present application can be made without departing from the spirit and scope of the present application.

[0061]

Explanation of symbols

[0062] 100,100a: Circuit board

[0063] 110: First circuit layer

[0064] 111: First insulation layer

[0065] 111a: first patterned insulating layer

[0066] 112: Second insulation layer

[0067] 112a: second patterned insulating layer

[0068] 113: First liquid metal layer

[0069] 114: Second liquid metal layer

[0070] 115: Insulation layer

[0071] 116: Insulation layer

[0072] 117: Conductive layer

[0073] 118: Conductive layer

[0074] 119: Insulation layer

[0075] 120: Insulation layer

[0076] 121: The third insulation layer

[0077] 121a: third patterned insulating layer

[0078] 122: Fourth insulation layer

[0079] 122a: fourth patterned insulating layer

[0080] 123: The third liquid metal layer

[0081] 124: Fourth liquid metal layer

[0082] 125: Insulation layer

[0083] 126: Insulation layer

[0084] 127: Conductive layer

[0085] 128: Conductive layer

[0086] 129: Insulation layer

[0087] 130: Insulation layer

[0088] 131: Fifth insulation layer

[0089] 131a: fifth patterned insulating layer

[0090] 132: Sixth insulation layer

[0091] 132a: sixth patterned insulating layer

[0092] 133: Fifth Liquid Metal Layer

[0093] 134: Sixth Liquid Metal Layer

[0094] 135: Adhesive layer

[0095] 136: Adhesive layer

[0096] 137: Second circuit layer

[0097] 138: The third circuit layer

[0098] 139: Liquid Metal Materials

[0099] 140: Seals

[0100] d1: first distance

[0101] d2: second distance

[0102] d3: third distance

[0103] d4: fourth distance

[0104] s1: first surface

[0105] s2: second surface

[0106] DL1: First differential line group

[0107] DL2: Second differential line group

[0108] DL3: The third differential line group

[0109] DL4: Fourth differential line group

[0110] D1: First direction

[0111] D2: Second direction

[0112] HL1: First horizontal line

[0113] HL2: Second Horizontal Line

[0114] HL3: Third Horizontal

[0115] HL4: Fourth Horizontal

[0116] R1: First groove

[0117] R2: Second groove

[0118] R3: The third groove

[0119] R4: Fourth groove

[0120] R5: Fifth groove

[0121] R6: Sixth groove

[0122] IN1: Insulation layer

[0123] IN2: Insulation layer

[0124] H1, H2: Through holes.

Claims

1. A circuit board, characterized in that: Include: The first circuit layer; The second circuit layer; A third circuit layer, wherein the first circuit layer is disposed between the second circuit layer and the third circuit layer; A first differential line group is arranged between the first circuit layer and the second circuit layer; A second differential line group is arranged between the first circuit layer and the third circuit layer; A third differential line group is arranged between the first circuit layer and the second circuit layer; and a fourth differential line group, arranged between the first circuit layer and the third circuit layer; The first differential line group has a first orthographic projection on the first circuit layer, the second differential line group has a second orthographic projection on the first circuit layer, the third differential line group has a third orthographic projection on the first circuit layer, and the fourth differential line group has a fourth orthographic projection on the first circuit layer, wherein the first orthographic projection is separated from the third orthographic projection, and the second orthographic projection is separated from the fourth orthographic projection; There is a first distance between the first differential line group and the first circuit layer, there is a second distance between the second differential line group and the first circuit layer, there is a third distance between the third differential line group and the first circuit layer, and there is a fourth distance between the fourth differential line group and the first circuit layer, wherein the first distance is smaller than the third distance, and the second distance is smaller than the fourth distance. 2 . The circuit board of claim 1 , wherein each of the first differential line group, the second differential line group, the third differential line group, and the fourth differential line group includes two differential lines.

3. The circuit board according to claim 2, wherein: Further including: The liquid metal structure covers each of the differential lines, wherein the liquid metal structure is distributed between the first circuit layer, the second circuit layer and the third circuit layer.

4. The circuit board according to claim 2, wherein each of the differential lines comprises: A conductive structure, wherein the conductive structure is composed of graphene; and An insulating structure surrounds the conductive structure, wherein the insulating structure is composed of graphene oxide.

5. The circuit board according to claim 1, wherein: Further including: A first insulating layer, disposed between the first circuit layer and the second circuit layer, wherein the first insulating layer surrounds the liquid metal structure; A first adhesive layer is disposed between the first insulating layer and the second circuit layer; A second insulating layer is disposed between the first circuit layer and the third circuit layer, wherein the second insulating layer surrounds the liquid metal structure; and The second adhesive layer is arranged between the second insulating layer and the third circuit layer.

6. A method for manufacturing a circuit board, characterized in that: Include: Providing a first circuit layer; forming a first patterned insulating layer on the first surface of the first circuit layer, wherein the first patterned insulating layer comprises a plurality of first grooves; forming a second patterned insulating layer on the second surface of the first wiring layer, wherein the second patterned insulating layer comprises a plurality of second grooves, wherein one of the plurality of first grooves is connected to one of the plurality of second grooves; forming a first liquid metal layer on a portion of the first patterned insulating layer; forming a second liquid metal layer on a portion of the second patterned insulating layer; forming a first differential line group on a portion of the first liquid metal layer; forming a second differential line group on a portion of the second liquid metal layer; forming a third patterned insulating layer, wherein the third patterned insulating layer comprises a plurality of third grooves, and the plurality of first grooves are connected to the plurality of third grooves; forming a fourth patterned insulating layer, wherein the fourth patterned insulating layer comprises a plurality of fourth grooves, and the plurality of second grooves are connected to the plurality of fourth grooves; forming a third liquid metal layer on the first differential line group; forming a fourth liquid metal layer on the second differential line group; forming a second circuit layer on the first differential line group; forming a third circuit layer on the second differential line group; After forming the second circuit layer and the third circuit layer, filling the first, second, third and fourth grooves with liquid metal material; and The holes in the second circuit layer are sealed.

7. The method for manufacturing a circuit board according to claim 6, wherein the step of forming the first differential line group comprises: forming a conductive structure on the first liquid metal layer, wherein the conductive structure is composed of graphene; and An insulating structure is formed on the conductive structure and surrounds the conductive structure, wherein the insulating structure is composed of graphene oxide.

8. The method for manufacturing a circuit board according to claim 6, wherein: Also includes: forming a third differential line group on a portion of the third liquid metal layer; forming a fourth differential line group on a portion of the fourth liquid metal layer; forming a fifth patterned insulating layer, wherein the fifth patterned insulating layer comprises a plurality of fifth grooves, and the plurality of third grooves are connected to the plurality of fifth grooves; forming a sixth patterned insulating layer, wherein the sixth patterned insulating layer comprises a plurality of sixth grooves, and the plurality of fourth grooves are connected to the plurality of sixth grooves; forming a fifth liquid metal layer on the third differential line set; and A sixth liquid metal layer is formed on the fourth differential line set, wherein the liquid metal material is also filled in the fifth and sixth grooves. 9 . The method for manufacturing a circuit board according to claim 6 , wherein the first, second, third and fourth liquid metal layers are formed by sputtering. 10 . The method for manufacturing a circuit board according to claim 6 , wherein the step of sealing the holes in the second circuit layer is performed at room temperature and in a vacuum environment.

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