Layout patterns for static random access memory

Abstract

The invention discloses a layout pattern of a static random access memory (SRAM), which comprises a substrate, a plurality of diffusion regions and a plurality of gate structures positioned on the substrate, each diffusion region comprises a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure stretches across the plurality of diffusion regions to form a plurality of transistors. The plurality of grids include a first grid, the first grid includes a first L-shaped portion, the first L-shaped portion spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), and the first diffusion region and the fifth diffusion region are adjacent to each other and are in direct contact with each other.

Description

Technical Field

[0001] The present invention relates to a static random access memory (SRAM), and more particularly to a static random access memory (SRAM) layout pattern with a body contact. Background Art

[0002] An embedded static random access memory (embedded SRAM) includes a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased at the same time. The way in which static random access memory stores data is to use the conductive state of the transistor in the memory cell. The design of static random access memory is based on mutually coupled transistors. There is no problem of capacitor discharge, and it does not need to be continuously charged to keep the data from being lost, that is, there is no need to update the memory. This is different from the way that dynamic random access memory (DRAM), which is also a volatile memory, uses the charged state of the capacitor to store data. The access speed of static random access memory is quite fast, so it is used as cache memory in computer systems. Summary of the invention

[0003] A layout pattern of a static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions located on the substrate, each diffusion region including a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, each diffusion region is arranged along a first direction (Y direction), a plurality of gate structures are located on the substrate, each gate structure extends along a second direction (X direction) and crosses the plurality of diffusion regions to form a plurality of transistors, wherein the plurality of transistors include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first access transistor PG1 and a second access transistor PG2, wherein the plurality of gates include a first gate, wherein the first gate includes a first L-shaped portion, the first L-shaped portion crosses the first diffusion region and the fifth diffusion region and forms the first pull-down transistor PD1, wherein the first diffusion region is adjacent to and directly contacts the fifth diffusion region.

[0004] The invention is characterized in that an improved static random access memory layout pattern is proposed, which includes some additional diffusion regions located next to the original diffusion regions, the additional diffusion regions have a conductivity type opposite to that of the original diffusion regions, and the gate structure is designed to be L-shaped or T-shaped (from a top view). In this way, the charges accumulated under the gate structure can flow out through the diffusion region and then be released through the contact structure, thereby avoiding affecting the electrical properties of the transistor and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a circuit diagram of an SRAM cell;

[0006] Figure 2 A layout diagram of a static random access memory (SRAM) cell;

[0007] Figure 3 is a schematic diagram of a cross-sectional structure of a transistor;

[0008] Figure 4 A layout diagram of a static random access memory (SRAM) cell according to a first preferred embodiment of the present invention;

[0009] Figure 5 for Figure 4 An enlarged schematic diagram of the middle gate structure G1 and the surrounding area;

[0010] Figure 6 A layout diagram of a static random access memory (SRAM) cell according to a second preferred embodiment of the present invention;

[0011] Figure 7A layout diagram of a static random access memory (SRAM) cell according to a third preferred embodiment of the present invention;

[0012] Figure 8 for Figure 7 An enlarged schematic diagram of the middle gate structure G2 and the surrounding area;

[0013] Fig. 9 A layout diagram of a static random access memory (SRAM) cell according to a fourth preferred embodiment of the present invention;

[0014] Fig.10 A layout diagram of a static random access memory (SRAM) cell according to a fifth preferred embodiment of the present invention;

[0015] Fig.11 FIG. 4 is a layout diagram of a static random access memory (SRAM) cell according to a sixth preferred embodiment of the present invention.

[0016] Explanation of symbols

[0017] 10: Static random access memory cell

[0018] 12: Base

[0019] 12A: Silicon layer

[0020] 12B: Insulation layer

[0021] 12C: Silicon layer

[0022] 14: Gate dielectric layer

[0023] 16: Depletion Zone

[0024] 18: Region

[0025] 19: Shallow Trench Isolation

[0026] 20: Substrate contact

[0027] 22: Substrate contact

[0028] 24: Substrate contact

[0029] D: Diffusion zone

[0030] D1: Diffusion zone (first diffusion zone)

[0031] D2: Diffusion zone (second diffusion zone)

[0032] D3: Diffusion zone (third diffusion zone)

[0033] D4: Diffusion zone (fourth diffusion zone)

[0034] D5: Diffusion Zone (Fifth Diffusion Zone)

[0035] D6: Diffusion Zone (Sixth Diffusion Zone)

[0036] D7: Diffusion Zone (Seventh Diffusion Zone)

[0037] D8: Diffusion Zone (Eighth Diffusion Zone)

[0038] G: Gate structure

[0039] G1: Gate structure (first gate)

[0040] G2: Gate structure (second gate)

[0041] G3: Gate structure (third gate)

[0042] G4: Gate structure (fourth gate)

[0043] G2A: Long side

[0044] G2B: Short side

[0045] Sr: Source

[0046] Dr: Drain

[0047] O: Center point

[0048] R: Region

[0049] R1: Region

[0050] P1: First L-shaped part

[0051] P1A: Long side

[0052] P1B: Short side

[0053] P2: Second L-shaped part

[0054] P2A: Long side

[0055] P2B: Short side

[0056] V: Contact column DETAILED DESCRIPTION

[0057] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0058] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.

[0059] The present invention provides a layout pattern of a static random access memory (embedded SRAM). Figure 1 , Figure 1 A circuit diagram of an SRAM cell is shown. In the present embodiment, an SRAM cell 10 preferably comprises a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1 and a second access transistor PG2 to form a flip-flop, wherein the first pull-up transistor PU1 and the second pull-up transistor PU2, the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit, so that data can be latched in the storage node N1 or N2. In addition, the first pull-up transistor PU1 and the second pull-up transistor PU2 are used as active loads, and they can also be replaced by ordinary resistors as pull-up transistors, in which case it is a four-device SRAM (4T-SRAM). In addition, in the present embodiment, a source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.

[0060] In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the SRAM cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2 and the first access transistor PG1, the second access transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors, but the present invention is not limited thereto. The first pull-up transistor PU1 and the first pull-down transistor PD1 together constitute an inverter, and the two ends of the series circuit formed by the two are respectively coupled to a voltage source Vcc and a voltage source Vss; similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 constitute another inverter, and the two ends of the series circuit formed by the two are also respectively coupled to the voltage source Vcc and the voltage source Vss. The above two inverters are coupled to each other to store data.

[0061] In addition, at the storage node N1, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first access transistor PG1 are electrically connected respectively; similarly, at the storage node N2, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, and the second access transistor PG2 are electrically connected respectively. As for the gates of the first access transistor PG1 and the second access transistor PG2, they are respectively coupled to the word line WL, and the sources of the first access transistor PG1 and the second access transistor PG2 are respectively coupled to the corresponding bit lines BL1 and BL2.

[0062] The above-mentioned SRAM cell 10 includes six transistors, and therefore can also be called a six-transistor static random access memory (6T-SRAM). However, the SRAM cell of the present invention is not limited to the use of 6T-SRAM, and other SRAM patterns with more transistors, such as 8T-SRAM and 10T-SRAM, can also be used as the SRAM cell of the present invention. In addition, each of the above transistors can also include a combination of other P-type transistors and N-type transistors.

[0063] Figure 21 is a layout diagram of a static random access memory (SRAM) cell. In this embodiment, the static random access memory cell 10 is located in a region R and is disposed on a substrate 12, such as a silicon-on-insulator (SOI) substrate. The substrate 12 is provided with a plurality of diffusion regions D arranged in parallel with each other, and shallow trench isolation (not shown) is provided around each diffusion region D.

[0064] In addition, the substrate 12 includes multiple gate structures G, and each of the above-mentioned transistors (including the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2) includes a gate structure G that spans at least one diffusion region D and constitutes each transistor.

[0065] like Figure 2 As shown, in order to clearly define the positions of each gate structure G and diffusion area D, the gate structure G is divided into gate structure G1, gate structure G2, gate structure G3, and gate structure G4, and the diffusion area D is also divided into diffusion area D1, diffusion area D2, diffusion area D3, and diffusion area D4. The gate structure G1 spans over the diffusion area D2 to form a pull-up transistor PU1; the gate structure G1 spans over the diffusion area D1 to form a pull-down transistor PD1; the gate structure G2 spans over the diffusion area D1 to form an access transistor PG1; the gate structure G3 spans over the diffusion area D3 to form a pull-up transistor PU2; the gate structure G3 spans over the diffusion area D4 to form a pull-down transistor PD2; the gate structure G4 spans over the diffusion area D4 to form an access transistor PG2. It can be understood that the gate structure G1, the gate structure G2, the gate structure G3, and the gate structure G4 all belong to the gate structure G, and the diffusion area D1, the diffusion area D2, the diffusion area D3, and the diffusion area D4 all belong to the diffusion area D.

[0066] In the present invention, the diffusion regions D1, D2, D3, and D4 are preferably arranged along a first direction (eg, the Y-axis direction), and the gate structures G1, G2, G3, and G4 are long strip-shaped structures, all arranged along a second direction (eg, the X-axis direction). Preferably, the first direction and the second direction are perpendicular to each other.

[0067] The region R also includes a plurality of metal layers (not shown) and contact pillars V. The metal layers and contact pillars V are mainly used to electrically connect each transistor to other components, such as word lines, bit lines, voltage sources, or to connect storage nodes to serve as the interconnection structure of transistors. The material of the metal layer and the contact pillars V is, for example, metal, and the two can have the same material. For the sake of simplicity of the drawings, Figure 2 The location of the metal layer is not shown in the figure, but for a clearer explanation, Figure 2 The transistors, storage nodes, word lines, bit lines, voltage sources, etc. to which each component is connected are marked on the diagram to clearly show the connection relationship between each component.

[0068] In addition, Figure 2 In the embodiment, since the first pull-down transistor PD1, the second pull-down transistor PD2 and the first access transistor PG1, the second access transistor PG2 are composed of N-type metal oxide semiconductor transistors, the diffusion region D they cross is also an N-type doped diffusion region. In contrast, since the first pull-up transistor PU1 and the second pull-up transistor PU2 are composed of P-type metal oxide semiconductor transistors, the diffusion region D they cross is also a P-type doped diffusion region. In other words, Figure 2 As shown, the diffusion regions D1 and D4 are N-type diffusion regions, while the diffusion regions D2 and D3 are P-type diffusion regions. Figure 2 In the figure, “N+” represents an N-type doped region, and “P+” represents a P-type doped region.

[0069] The applicant has discovered that when a transistor is formed on a silicon-on-insulator (SOI) substrate, some charges may be accumulated under the gate structure and be trapped, causing electrical instability. Figure 3 A schematic diagram of a cross-sectional structure of a transistor is shown. Figure 3 As shown, the substrate 12 is a SOI substrate, which includes a silicon layer 12A, an insulating layer 12B and a silicon layer 12C stacked from bottom to top, a gate structure G is located on the substrate 12, a gate dielectric layer 14 is included between the gate structure G and the substrate 12, the substrate on both sides of the gate structure includes a source Sr and a drain Dr respectively, and a shallow trench isolation (STI) 19 is located outside the source Sr and the drain Dr. A depletion region 16 is included below the gate structure G and between the source Sr and the drain Dr. However, there is a region 18 below the depletion region 16, located between the depletion region 16 and the insulating layer 12B, and some charges may be accumulated in the region 18, but these charges cannot be discharged from the region 18, and the charges accumulated in the region 18 may affect the electrical properties of the transistor.

[0070] In order to solve the above problems, the present invention provides several improved layout patterns of static random access memory, by adding a part of the diffusion region and changing the shape of the gate structure, so that the charge accumulated under the gate structure can be released, so as to avoid the problem of charge accumulation under the gate structure. Please refer to the following paragraphs for more details.

[0071] Figure 4 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a first preferred embodiment of the present invention. Figure 4 As shown, Figure 2Compared with the embodiment shown in FIG. 1 , in addition to the above-mentioned diffusion regions D1 to D4, the present embodiment further includes additional diffusion regions D5, D6, D7 and D8. The diffusion region D5 is connected to the diffusion region D1, the diffusion region D6 is connected to the diffusion region D2, the diffusion region D7 is connected to the diffusion region D3, and the diffusion region D8 is connected to the diffusion region D4. In addition, the shapes of the gate structures G1 and G3 are also similar to those of FIG. Figure 2 More specifically, Figure 5 Draw Figure 4 The enlarged schematic diagram of the middle gate structure G1 and the surrounding area. Please note Figure 5 The positional relationship between the gate structure G1 and the diffusion region is mainly drawn, and components such as the contact pillar V are omitted. Figure 5 As shown, taking the gate structure G1 as an example, the gate structure G1 includes a first L-shaped portion P1 constituting a pull-down transistor PD1 and a second L-shaped portion P2 constituting a pull-up transistor PU1, and the first L-shaped portion P1 includes a long side portion P1A and a short side portion P1B, and the second L-shaped portion P2 also includes a long side portion P2A and a short side portion P2B. From the top view, the first L-shaped portion P1 and the second L-shaped portion P2 are L-shaped, respectively, and the long side portion P1A of the first L-shaped portion P1 is located on the diffusion region D1, and the short side portion P1B is located on the diffusion region D5. The long side portion P2A of the second L-shaped portion P2 is located on the diffusion region D2, and the short side portion P2B is located on the diffusion region D6.

[0072] In this embodiment, the additional diffusion regions D5-D8 are located next to the diffusion regions D1-D4, and the electrical properties of the diffusion regions D5-D8 are opposite to those of the adjacent diffusion regions D1-D4. For example, if the diffusion region D1 is of N type, the diffusion region D5 adjacent to the diffusion region D1 is of P type. Similarly, in this embodiment, the diffusion regions D5 and D8 are of P type, and the diffusion regions D6 and D7 are of N type.

[0073] Taking the first pull-down transistor PD1 as an example, since the gate structure of the first pull-down transistor PD1 is N-type across the diffusion region D2, the source Sr and drain Dr of the first pull-down transistor D1 are N-type. In contrast, P-type charges will accumulate in the area directly below the gate and be limited by the N-type source Sr and drain Dr. If these charges are Figure 2 In the embodiment shown, the current is limited to the area directly below the gate structure and cannot be discharged. However, through the improved design of the present invention, such as Figure 4As shown, the P-type charge directly below the gate structure of the first pull-down transistor PD1 can flow out through the diffusion area D5 which is also P-type, and then will be connected to the Vss contact structure through the metal silicide layer (not shown) formed on the surface of the diffusion areas D1 to D8, so that the charge is released. Similarly, the charge (N-type charge) accumulated directly below the gate structure of the first pull-up transistor PU1 will also flow out through the N-type diffusion area D6, and then will be connected to the Vcc contact structure through the metal silicide layer (not shown), so that the charge is released. As for the second pull-up transistor PU2 and the second pull-down transistor PD2, the accumulated charge can flow out from the diffusion area D7 and the diffusion area D8 respectively in the same way. Since the second pull-up transistor PU2 and the second pull-down transistor are symmetrical patterns of the first pull-up transistor PU1 and the first pull-down transistor PD1 along the center point O, they will not be repeated here. Therefore, the Vss contact structure and the Vcc contact structure described herein can be used as body contacts of the pull-down transistor (PD1, PD2) and the pull-up transistor (PU1, PU2), respectively, and their function is to release the charges accumulated in the substrate.

[0074] Figure 4 In the layout design, the accumulated charges of the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2 and the second pull-down transistor PD2 can be released. In the actual experience of the applicant, the charge accumulation of the pull-down transistors PD1 and PD2 is more serious than that of the pull-up transistors PU1 and PU2. Therefore, in other embodiments of the present invention, the layout design can also be performed only for releasing the accumulated charges of the first pull-down transistor PD1 and the second pull-down transistor PD2.

[0075] Figure 6 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a second preferred embodiment of the present invention. In this embodiment, most of the structures are similar to those described above. Figure 4 The embodiments shown are the same, and the same parts are not repeated. The difference between this embodiment and the above embodiment is that the diffusion regions D6 and D7 are not included, and the second L-shaped portion P2 of the gate structure G1 and the gate structure G3 is not designed to be L-shaped. Therefore, in this embodiment, only the accumulated charges of the first pull-down transistor PD1 and the second pull-down transistor PD2 are released. However, compared with the above embodiment, the present invention has the advantages of simpler structure, easier manufacturing, and smaller occupied area.

[0076] Figure 7 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a third preferred embodiment of the present invention. In this embodiment, most of the structures are similar to those described above. Figure 4The embodiment shown is the same, and the same parts are not repeated. The difference between this embodiment and the above embodiment is that, from the top view, the gate structure G2 and the gate structure G4 are designed to be T-shaped. In more detail, Figure 8 Draw Figure 7 The enlarged schematic diagram of the middle gate structure G2 and the surrounding area. Please note Figure 8 The positional relationship between the gate structure G2 and the diffusion region is mainly drawn, and components such as the contact pillar V are omitted. Figure 8 As shown, taking the gate structure G2 as an example, the gate structure G2 is T-shaped, having a long side portion G2A and a short side portion G2B, the long side portion extends along the X-axis direction and is located on the diffusion region D1, and the short side portion G2B extends along the Y-axis direction and is located on the diffusion region D5. In this way, the accumulated charges directly under the gate structures of the first access transistor PG1 and the second access transistor PG2 can be released.

[0077] Similar to the above-mentioned method of releasing the accumulated charge of the first pull-down transistor PD1, through the design of this embodiment, the accumulated charge (P-type charge) directly below the gate structure of the first access transistor PG1 and the second access transistor PG2 can flow out from the diffusion area D5 and the diffusion area D8 respectively, and in this embodiment, a base contact 20 is formed on the diffusion area D5 and the diffusion area D8. The base contact 20 is similar to the contact column V and is electrically connected to the diffusion area D5. Therefore, the accumulated charge of the first access transistor PG1 and the second access transistor PG2 can be released through the base contact 20.

[0078] The static random access memory cells 10 described in this embodiment may be arranged in an array. Adjacent static random access memory cells 10 may share a portion of the diffusion region. For example, Figure 6 The region R shown contains a static random access memory cell, while another adjacent region R1 to the left of region R contains another static random access memory cell, wherein the diffusion area D5 of the static random access memory cell in region R is actually equal to the diffusion area D8 of the static random access memory cell in region R1.

[0079] Other embodiments of the present invention are provided below. The layout patterns of these embodiments are improved based on the above embodiments. Most of the components may be the same as those described in the above embodiments. These components are represented by the same reference numerals and will not be repeated.

[0080] Fig. 9 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a fourth preferred embodiment of the present invention. Most of the components in this embodiment are similar to Figure 7The third embodiment shown is the same, but the difference between this embodiment and the third embodiment is that a base contact 22 is further included in the diffusion region D5. The base contact 22 is similar to the contact column V, electrically connected to the diffusion region D5, and is located next to the first pull-down transistor PD1, so the accumulated charge of the pull-down transistor (PD1 or PD2) can be released through the base contact 22. In the above embodiment, the charge of the pull-down transistor (PD1 or PD2) is released by connecting the metal silicide subsequently formed on the surface of the diffusion region through the Vss contact structure, but the conductivity of the metal silicide may be poor due to the lack of manufacturing process. At this time, the base contact 22 can be added. This structure allows the access transistor (PG1 and PG2) and the pull-down transistor (PD1 or PD2) to each include a base contact 20 and a base contact 22, which can release the charge more effectively.

[0081] Fig.10 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a fifth preferred embodiment of the present invention. Most of the components in this embodiment are similar to Fig. 9 The fourth embodiment shown is the same, but the difference between this embodiment and the fourth embodiment is that the diffusion region D5 is divided into different regions. More specifically, the diffusion regions D5 included in the access transistor (PG1 and PG2) and the pull-down transistor (PD1 or PD2) are not directly connected to each other, and the access transistor (PG1 and PG2) releases the charge through the substrate contact 20, and the pull-down transistor (PD1 or PD2) releases the charge through the substrate contact 22 or the Vss contact structure. Such a variation also falls within the scope of the present invention.

[0082] Fig.11 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a sixth preferred embodiment of the present invention. Most of the components in this embodiment are similar to Fig. 9 The fourth embodiment shown is the same, but the difference between this embodiment and the fourth embodiment is that a base contact 24 is added, which is located at the junction of the diffusion area D1 and the diffusion area D5, and the base contact 20 is omitted in this embodiment and the diffusion area D5 near it is reduced. In other words, the access transistor (PG1 and PG2) and the pull-down transistor (PD1 or PD2) of this embodiment can share the base contact 24 or the Vss contact structure (used as the base contact) to release the charge. This variation also falls within the scope of the present invention.

[0083] In summary, the present invention provides a layout pattern of a static random-access memory (SRAM), including a substrate 12, a plurality of diffusion regions D1-D8 located on the substrate, each diffusion region including a first diffusion region D1, a second diffusion region D2, a third diffusion region D3, a fourth diffusion region D4, a fifth diffusion region D5, a sixth diffusion region D6, a seventh diffusion region D7 and an eighth diffusion region D8, and each diffusion region is arranged along a first direction (Y direction). A plurality of gate structures G are disposed on a substrate, each of the gate structures G extending along a second direction (X direction) and crossing a plurality of diffusion regions D1-D8 to form a plurality of transistors, wherein the plurality of transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1) and a second access transistor (PG2), wherein the plurality of gates include a first gate G1, wherein the first gate G1 includes a first L-shaped portion P1, the first L-shaped portion P1 crossing the first diffusion region D1 and the fifth diffusion region D5 and forming a first pull-down transistor (PD1), wherein the first diffusion region D1 is adjacent to and directly contacts the fifth diffusion region D5 (e.g. Figure 5 embodiment shown).

[0084] In some embodiments of the present invention, the first L-shaped portion P1 includes a short side portion P1B and a long side portion P1A, wherein the short side portion P1B of the first L-shaped portion P1 is arranged along a first direction (Y direction), and the long side portion P1A of the first L-shaped portion P1 is arranged along a second direction (X direction).

[0085] In some embodiments of the present invention, the short side portion P1B of the first L-shaped portion P1 is located on the fifth diffusion region D5 , and the long side portion P1A of the first L-shaped portion P1 is located on the first diffusion region D1 .

[0086] In some embodiments of the present invention, the first gate G1 includes a second L-shaped portion P2, the second L-shaped portion P2 spans the second diffusion region D2 and the sixth diffusion region D6 and forms a first pull-up transistor (PU1), wherein the second diffusion region D2 is adjacent to and directly contacts the sixth diffusion region D6 (e.g. Figure 4 embodiment shown).

[0087] In some embodiments of the present invention, the second L-shaped portion P2 includes a short side portion P2B and a long side portion P2A, wherein the short side portion P2B of the second L-shaped portion P2 is arranged along the first direction (Y direction), and the long side portion P2A of the second L-shaped portion P2 is arranged along the second direction (X direction).

[0088] In some embodiments of the present invention, the long side portion P1A of the first L-shaped portion P1 and the long side portion P2A of the second L-shaped portion P2 are aligned with each other in the second direction (X direction).

[0089] In some embodiments of the present invention, the short side portion P2B of the second L-shaped portion P2 is located on the sixth diffusion region D6, and the long side portion P2A of the second L-shaped portion P2 is located on the second diffusion region D2.

[0090] In some embodiments of the present invention, the plurality of gates G include a second gate G2, which spans the first diffusion region D1 and the fifth diffusion region D5 and forms a first access transistor (PG1), wherein from a top view, the second gate G2 has a T-shaped profile (e.g. Figure 6 embodiment shown).

[0091] In some embodiments of the present invention, the second gate G2 has a short side portion G2B and a long side portion G2A, wherein the short side portion G2B of the second gate G2 is arranged along the first direction (Y direction), and the long side portion G2A of the second gate G2 is arranged along the second direction (X direction).

[0092] In some embodiments of the present invention, the short side portion G2B of the second gate G2 is located on the fifth diffusion region D5, and the long side portion G2A of the second gate G2 is located on the first diffusion region D1.

[0093] In some embodiments of the present invention, a base contact 20 is further included, which is located on the fifth diffusion region D5 and is electrically connected to the fifth diffusion region D5.

[0094] In some embodiments of the present invention, the first diffusion region D1, the fourth diffusion region D4, the sixth diffusion region D6 and the seventh diffusion region D7 include a first conductivity type (e.g., N-type), and the second diffusion region D2, the third diffusion region D3, the fifth diffusion region D5 and the eighth diffusion region D8 include a second conductivity type (e.g., P-type).

[0095] In some embodiments of the present invention, the first conductivity type (eg, N-type) is different from the second conductivity type (eg, P-type).

[0096] In some embodiments of the present invention, the substrate 12 includes a SOI substrate.

[0097] In some embodiments of the present invention, a third gate G3 is further included. The third gate G3 spans the third diffusion region D3 and the seventh diffusion region D7 to form a second pull-up transistor (PU2). The third diffusion region D3 is adjacent to and directly contacts the seventh diffusion region D7.

[0098] In some embodiments of the present invention, the third gate G3 crosses over the fourth diffusion region D4 and the eighth diffusion region D8 and forms a second pull-down transistor (PD2), wherein the fourth diffusion region D4 and the eighth diffusion region D8 are adjacent to and directly contact each other.

[0099] In some embodiments of the present invention, the first gate G1 and the third gate G3 are symmetrical to each other along a center point O.

[0100] In some embodiments of the present invention, the plurality of gates include a fourth gate G4, which spans across the fourth diffusion region D4 and the eighth diffusion region D8 and forms a second access transistor (PG2), wherein the fourth gate G4 has a T-shaped profile from a top view.

[0101] In some embodiments of the present invention, the second gate G2 and the fourth gate G4 are symmetrical to each other along a center point O.

[0102] In some embodiments of the present invention, a layout pattern of a static random access memory is arranged adjacent to a layout pattern of another static random access memory (for example, respectively located in region R and region R1), and a fifth diffusion region D5 of the layout pattern of the static random access memory is in direct contact with an eighth diffusion region D8 of the layout pattern of another static random access memory.

[0103] The invention is characterized in that an improved static random access memory layout pattern is proposed, which includes some additional diffusion regions located next to the original diffusion regions, the additional diffusion regions have a conductivity type opposite to that of the original diffusion regions, and the gate structure is designed to be L-shaped or T-shaped (from a top view). In this way, the charges accumulated under the gate structure can flow out through the diffusion region and then be released through the contact structure, thereby avoiding affecting the electrical properties of the transistor and improving the product yield.

[0104] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A layout pattern of a static random-access memory (SRAM), comprising: substrate; A plurality of diffusion regions are located on the substrate, each of the diffusion regions includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each of the diffusion regions is arranged along a first direction (Y direction); A plurality of gate structures are located on the substrate, each gate structure extends along a second direction (X direction) and crosses the plurality of diffusion regions to form a plurality of transistors, wherein the plurality of transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1) and a second access transistor (PG2); in, The plurality of gates include a first gate, wherein the first gate includes a first L-shaped portion, the first L-shaped portion spans the first diffusion region and the fifth diffusion region and constitutes the first pull-down transistor (PD1), wherein the first diffusion region is adjacent to and directly contacts the fifth diffusion region.

2. The layout pattern of the static random access memory as described in claim 1, wherein the first L-shaped portion includes a short side portion and a long side portion, wherein the short side portion of the first L-shaped portion is arranged along the first direction (Y direction), and the long side portion of the first L-shaped portion is arranged along the second direction (X direction). 3 . The layout pattern of the static random access memory as claimed in claim 2 , wherein the short side portion of the first L-shaped portion is located on the fifth diffusion region, and the long side portion of the first L-shaped portion is located on the first diffusion region.

4. The layout pattern of the static random access memory as claimed in claim 2, wherein: The first gate includes a second L-shaped portion, which spans the second diffusion region and the sixth diffusion region and constitutes the first pull-up transistor (PU1), wherein the second diffusion region is adjacent to and directly contacts the sixth diffusion region.

5. The layout pattern of the static random access memory as described in claim 4, wherein the second L-shaped portion includes a short side portion and a long side portion, wherein the short side portion of the second L-shaped portion is arranged along the first direction (Y direction), and the long side portion of the second L-shaped portion is arranged along the second direction (X direction). 6 . The layout pattern of the static random access memory as claimed in claim 5 , wherein the long side portion of the first L-shaped portion and the long side portion of the second L-shaped portion are aligned with each other in the second direction (X direction). 7 . The layout pattern of the static random access memory as claimed in claim 4 , wherein the short side portion of the second L-shaped portion is located on the sixth diffusion region, and the long side portion of the second L-shaped portion is located on the second diffusion region.

8. The layout pattern of the static random access memory as claimed in claim 4, wherein: The plurality of gates include a second gate that spans the first diffusion region and the fifth diffusion region and forms the first access transistor (PG1), wherein the second gate has a T-shaped profile as seen from a top view.

9. The layout pattern of the static random access memory as described in claim 8, wherein the second gate has a short side portion and a long side portion, wherein the short side portion of the second gate is arranged along the first direction (Y direction), and the long side portion of the second gate is arranged along the second direction (X direction). 10 . The layout pattern of the static random access memory as claimed in claim 9 , wherein the short side portion of the second gate is located on the fifth diffusion region, and the long side portion of the second gate is located on the first diffusion region.

11. The layout pattern of the static random access memory as claimed in claim 8, further comprising a substrate contact located on the fifth diffusion region and electrically connected to the fifth diffusion region.

12. The layout pattern of the static random access memory as claimed in claim 1, wherein the first diffusion region, the fourth diffusion region, the sixth diffusion region and the seventh diffusion region include a first conductivity type, and the second diffusion region, the third diffusion region, the fifth diffusion region and the eighth diffusion region include a second conductivity type. 13 . The layout pattern of the static random access memory as claimed in claim 12 , wherein the first conductivity type is different from the second conductivity type.

14. The layout pattern of the static random access memory as claimed in claim 1, wherein the substrate comprises an SOI substrate.

15. The layout pattern of the static random access memory as described in claim 1 further comprises a third gate, which crosses the third diffusion region and the seventh diffusion region and constitutes the second pull-up transistor (PU2), wherein the third diffusion region is adjacent to and directly contacts the seventh diffusion region.

16. The layout pattern of the static random access memory as claimed in claim 15, wherein the third gate crosses over the fourth diffusion region and the eighth diffusion region and constitutes the second pull-down transistor (PD2), wherein the fourth diffusion region is adjacent to and directly contacts the eighth diffusion region. 17 . The layout pattern of the static random access memory as claimed in claim 16 , wherein the first gate and the third gate are symmetrical to each other along a center point.

18. The layout pattern of the static random access memory as described in claim 1, wherein the multiple gates include a second gate and a fourth gate, the fourth gate spans the fourth diffusion region and the eighth diffusion region and constitutes the second access transistor (PG2), wherein from a top view, the fourth gate has a T-shaped profile. 19 . The layout pattern of the static random access memory as claimed in claim 18 , wherein the second gate and the fourth gate are symmetrical to each other along a center point.

20. The layout pattern of the static random access memory as described in claim 1, wherein the layout pattern of the static random access memory is arranged adjacent to the layout pattern of another static random access memory, and the fifth diffusion region of the layout pattern of the static random access memory is in direct contact with the eighth diffusion region of the layout pattern of the other static random access memory.

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