Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and a memory system, and the semiconductor device comprises a plurality of semiconductor columns which extend along a first direction, and each semiconductor column comprises a first end and a second end which are opposite to each other in the first direction; the bit lines are located on one side of the semiconductor columns in the first direction and connected with the first ends of the semiconductor columns respectively, the bit lines extend in the second direction and are arranged at intervals in the third direction, and any two of the first direction, the second direction and the third direction intersect with each other; the insulating layer is located on the multiple bit lines and located among the multiple semiconductor columns, the interior of the insulating layer comprises air gaps defined by the inner surface of the insulating layer, the air gaps are arranged between every two adjacent bit lines, the air gaps comprise first air gaps, the first top surfaces of the first air gaps extend in the second direction and the third direction, and the second top surfaces of the second air gaps extend in the third direction. The first top surface is on a side of the first end away from the second end.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] Dynamic random access memory is an important memory. The storage unit of dynamic random access memory mainly includes a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor is used to store data, and the transistor is used to control the storage of data in the storage capacitor.

[0003] Currently, the performance of dynamic random access memory needs to be further improved. How to improve the performance of dynamic random access memory is a technical problem that needs to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a storage system to improve the performance of the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] a plurality of semiconductor pillars extending along a first direction, the semiconductor pillars comprising first and second ends opposite to each other in the first direction;

[0007] a plurality of bit lines, located at one side of the plurality of semiconductor pillars in the first direction and respectively connected to the first ends of the plurality of semiconductor pillars, the plurality of bit lines extending along the second direction and arranged at intervals along the third direction, and any two of the first direction, the second direction and the third direction intersecting with each other; and

[0008] An insulating layer is located on the plurality of bit lines and between the plurality of semiconductor pillars, the interior of the insulating layer includes an air gap enclosed by the inner surface of the insulating layer, the air gap is arranged between two adjacent bit lines, the air gap includes a first air gap, a first top surface of the first air gap extends along the second direction and the third direction, and the first top surface is located on the side of the first end away from the second end.

[0009] In some embodiments, the first top surface comprises a flat surface.

[0010] In some embodiments, the air gap also includes a second air gap adjacent to and connected to the first air gap in the second direction, the second top surface of the second air gap includes a curved surface, the second top surface is adjacent to the first top surface and is located on the side of the first end away from the second end.

[0011] In some embodiments, the insulating layer further includes a first air gap region provided with the first air gap and a second air gap region provided with the second air gap, and a sum of areas of the first air gap regions is greater than a sum of areas of the second air gap regions.

[0012] In some embodiments, a vertex of the arc surface is located on a side of the first top surface away from the first end.

[0013] In some embodiments, a size of the first top of the first air gap in the third direction is less than or equal to a size of the first bottom of the first air gap in the third direction, the first top is arranged opposite to the first bottom in the first direction, and the first top of the first air gap is located on the side of the first end away from the second end.

[0014] In some embodiments, a dimension of the second top of the second air gap in the third direction is smaller than a dimension of the second bottom of the second air gap in the third direction, the second top is opposite to the second bottom in the first direction, and the second top is located on the side of the first end away from the second end.

[0015] In some embodiments, a plurality of the first air gaps are arranged in an array along the second direction and the third direction, a second air gap is disposed between two adjacent first air gaps in the second direction, and a bit line is disposed between two adjacent first air gap regions in the third direction.

[0016] In some embodiments, the first air gap further includes a first bottom surface, the first bottom surface is disposed opposite to the first top surface in the first direction, and the first bottom surface extends along the second direction and the third direction.

[0017] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, the method comprising:

[0018] forming a plurality of semiconductor pillars extending along a first direction, the semiconductor pillars including first and second ends opposite to each other in the first direction;

[0019] forming a plurality of bit lines, the plurality of bit lines being located on one side of the plurality of semiconductor pillars in the first direction and respectively contacting the first ends of the plurality of semiconductor pillars, the plurality of bit lines extending along the second direction and being arranged at intervals along the third direction, and any two of the first direction, the second direction and the third direction intersecting with each other; and

[0020] An insulating layer is formed, the insulating layer is located on the plurality of the bit lines and between the plurality of the semiconductor pillars, the interior of the insulating layer includes an air gap enclosed by the inner surface of the insulating layer, the air gap is arranged between two adjacent bit lines, the air gap includes a first air gap, a first top surface of the first air gap extends along the second direction and the third direction, and the first top surface is located on a side of the first end away from the second end.

[0021] In some embodiments, forming the insulating layer includes: forming a first insulating layer between the plurality of semiconductor pillars;

[0022] forming a sacrificial line extending along a second direction on the first insulating layer, wherein the sacrificial line is located between adjacent bit lines and adjacent semiconductor pillars; and

[0023] A second insulating layer is formed to cover the sacrificial line and the plurality of bit lines.

[0024] In some embodiments, the forming of the insulating layer further comprises: removing at least a portion of the second insulating layer in the first region and retaining the second insulating layer in the second region to form an insulating layer opening exposing a portion of the sacrificial line, wherein the first region and the second region both overlap with the sacrificial line and are adjacently disposed in the second direction; and

[0025] The sacrificial line is removed through the insulating layer opening to form a first air gap located in the second area and between the second insulating layer and the first insulating layer.

[0026] In some embodiments, forming the insulating layer also includes: forming a third insulating layer at the opening of the insulating layer to form a second air gap connected to the first air gap, the first insulating layer, the remaining second insulating layer and the third insulating layer constitute the insulating layer, and the second air gap and the first air gap constitute the air gap.

[0027] In some embodiments, the sum of the areas of the second regions is greater than the sum of the areas of the first regions.

[0028] In some embodiments, forming a sacrificial line extending along the second direction on the first insulating layer includes: forming a plurality of sacrificial lines spaced apart along a third direction;

[0029] The forming of the insulating layer opening exposing the portion of the sacrificial line comprises:

[0030] The insulating layer opening extending along the third direction is formed on the second insulating layer.

[0031] In some embodiments, the forming of a plurality of semiconductor pillars extending along the first direction comprises: forming a plurality of initial semiconductor pillars extending along the first direction, the initial semiconductor pillars comprising first initial ends and second initial ends opposite to each other in the first direction;

[0032] The forming of the first insulating layer between the plurality of semiconductor pillars comprises: filling a dielectric layer between the plurality of initial semiconductor pillars; and

[0033] A portion of the dielectric layer close to the first initial end is removed to form a groove extending along the first direction and the second direction, and the remaining dielectric layer forms the first insulating layer. The groove is disposed adjacent to the initial semiconductor column.

[0034] In some embodiments, forming a sacrificial line extending along the second direction on the first insulating layer includes:

[0035] forming the sacrificial line in the groove and contacting the first insulating layer, wherein the sacrificial line is disposed adjacent to the initial semiconductor column;

[0036] The forming of a plurality of semiconductor pillars extending along the first direction also includes: removing a portion of a first initial end of the initial semiconductor pillar to form the first end, the remaining initial semiconductor pillar forming the semiconductor pillar, and the sacrificial line top surface away from the first insulating layer is located on the side of the first end away from the second end.

[0037] In a third aspect, the present application further provides a storage system, including:

[0038] A memory, comprising the semiconductor device of any of the above embodiments; and

[0039] The controller is connected to the memory and is used to control the memory.

[0040] According to some embodiments of the present application, since the interior of the insulating layer includes an air gap enclosed by the inner surface of the insulating layer, the air gap is located between two adjacent bit lines, and the air gap includes a first air gap, the first top surface of the first air gap extends along the second direction and the third direction, and the first top surface is located on the side of the first end away from the second end. With this design, the first air gap extends away from the first top surface of the semiconductor column along two intersecting directions. In this way, the relative position between the first top surface and the bit line is more controllable, and it is easier to make the first top surface located on the side of the bit line away from the semiconductor column. The air gap including the first air gap can better improve the coupling effect between adjacent bit lines, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0042] Figure 2A is a schematic diagram of a cross-sectional structure of a semiconductor layer in some embodiments of the present application;

[0043] Figure 2B It is a schematic plan view of forming an initial semiconductor column and a gate structure in a semiconductor layer in some embodiments of the present application;

[0044] Figure 2C For along Figure 2B The schematic diagram of the cross-sectional structure taken along the A-A' tangent line is shown;

[0045] Figure 2D A schematic cross-sectional structure diagram of forming a first electrode and thinning the second surface to form a third surface in some embodiments of the present application;

[0046] Figure 2E is a schematic cross-sectional structure diagram of forming a first insulating layer in some embodiments of the present application;

[0047] Figure 2F A schematic cross-sectional structure diagram of forming a sacrificial layer in some embodiments of the present application;

[0048] Figure 2G is a schematic cross-sectional structure diagram of a sacrificial line formed in a groove and contacting a first insulating layer in some embodiments of the present application;

[0049] Figure 2H A schematic cross-sectional structure diagram of removing a portion of a first initial end of an initial semiconductor column to form a semiconductor column in some embodiments of the present application;

[0050] Fig.2I A schematic diagram of a planar structure for forming a bit line in some embodiments of the present application;

[0051] Figure 2J For along Fig.2I Schematic diagram of the cross-sectional structure taken along the B-B' tangent line;

[0052] Figure 3A A schematic plan view of forming a second insulating layer covering a plurality of sacrificial lines and a plurality of bit lines in some embodiments of the present application;

[0053] Figure 3B For along Figure 3A Schematic diagram of the cross-sectional structure taken along the C-C' tangent line;

[0054] Figure 3C is a schematic planar structural diagram of forming a mask pattern on the second insulating layer in some embodiments of the present application;

[0055] Figure 3D For along Figure 3C Schematic diagram of the cross-sectional structure taken along the D-D' tangent line;

[0056] Figure 3E For along Figure 3C Schematic diagram of the cross-sectional structure taken along the E-E' tangent line;

[0057] Figure 3F It is a schematic diagram of a planar structure in which an insulating layer opening extending along a third direction is formed on the second insulating layer in some embodiments of the present application;

[0058] Figure 3G For along Figure 3F Schematic diagram of the cross-sectional structure taken along the F-F' tangent line;

[0059] Figure 3H For along Figure 3F Schematic diagram of the cross-sectional structure taken along the G-G' tangent line;

[0060] Fig. 3I A schematic diagram of a planar structure of removing a plurality of sacrificial lines through an opening in an insulating layer in some embodiments of the present application;

[0061] Figure 3J For along Fig. 3I Schematic diagram of the cross-sectional structure taken along the H-H' tangent line;

[0062] Figure 3K For along Fig. 3I Schematic diagram of the cross-sectional structure taken along the I-I' tangent line;

[0063] Figure 4A It is a schematic diagram of a planar structure in which a third insulating layer is formed at an opening of the insulating layer in some embodiments of the present application;

[0064] Figure 4B A schematic diagram of a planar structure of an air gap and a bit line in some embodiments of the present application;

[0065] Figure 4C For along Figure 4A A schematic diagram of a cross-sectional structure taken along the J-J' tangent line;

[0066] Figure 4D For along Figure 4A Another schematic diagram of the cross-sectional structure taken along the J-J' tangent line;

[0067] Figure 4E For along Figure 4A Schematic diagram of the cross-sectional structure taken along the K-K' tangent line;

[0068] Figure 4FSchematic diagram of the planar structure of the gate structure and the semiconductor pillar of some embodiments of the present application;

[0069] Figure 5 A block diagram of a storage system according to some embodiments of the present application;

[0070] Figure 6 A block diagram of a storage system according to some other embodiments of the present application;

[0071] Figure 7 A block diagram of an electronic device according to some embodiments of the present application.

[0072] The reference numerals are as follows:

[0073] z, first direction; y, second direction; x, third direction;

[0074] 10, semiconductor layer; 10a, first surface; 10b, second surface; 10e, third surface; 10c, first groove; 10d, second groove; 101, initial semiconductor column; 1011, first initial end; 1012, second initial end; 102, semiconductor column; 1021, first end; 1022, second end; 1023, channel structure;

[0075] 11, insulating layer; 111, dielectric layer; 111a, groove; 111a1, bottom surface of groove; 112, first insulating layer; 112a, insulating top surface; 113, second insulating layer; 113a, first region; 113b, second region; 113c, insulating layer opening; 114, third insulating layer; 11a, air gap region; 11b, first air gap region; 11c, second air gap region;

[0076] 12, gate structure; 121, gate line; 122, gate insulating layer;

[0077] 131, a first electrode; 132, a second electrode;

[0078] 141, sacrificial layer; 142, sacrificial line; 142a, sacrificial line top surface; 142b, sacrificial line bottom surface; 142c, sacrificial line side surface;

[0079] 151, bit line; 152, mask pattern;

[0080] 161, initial air gap; 162, first air gap; 162a, first top surface; 162b, first bottom surface; 1621, first top; 1622, first bottom; 162c, first side surface; 163, second air gap; 163a, second top surface; 163b, second bottom surface; O, arc vertex; 164, air gap; 1631, second top; 1632, second bottom;

[0081] 100, semiconductor device; 200, memory; 300, controller; 400, storage system; 500, electronic device; host, 600. DETAILED DESCRIPTION

[0082] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0083] Please refer to Figure 1 , which is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application. The method for manufacturing a semiconductor device comprises the following steps:

[0084] Step S101: forming a plurality of semiconductor pillars extending along a first direction, wherein the semiconductor pillars include a first end and a second end opposite to each other in the first direction;

[0085] Step S102: forming a plurality of bit lines, the plurality of bit lines being located on one side of the plurality of semiconductor pillars in a first direction and respectively contacting the first ends of the plurality of semiconductor pillars, the plurality of bit lines extending along a second direction and being spaced apart along a third direction, and any two of the first direction, the second direction and the third direction intersecting with each other; and

[0086] Step S103: forming an insulating layer, the insulating layer being located on the plurality of bit lines and between the plurality of semiconductor pillars, the interior of the insulating layer including an air gap enclosed by the inner surface of the insulating layer, an air gap being arranged between two adjacent bit lines, the air gap including a first air gap, a first top surface of the first air gap extending along the second direction and the third direction, the first top surface being located on a side of the first end away from the second end.

[0087] In some embodiments of the present application, the above method is used to form an air gap including a first air gap between two adjacent bit lines, the first top surface of the first air gap extends along the second direction and the third direction, and the first top surface is located on the side of the first end away from the second end. In this way, the first air gap extends away from the first top surface of the semiconductor column along two intersecting directions, the relative position between the first top surface and the bit line is more controllable, and it is easier to make the first top surface located on the side of the bit line away from the semiconductor column, and the air gap including the first air gap can better improve the coupling effect between adjacent bit lines, thereby improving the performance of the semiconductor device.

[0088] The manufacturing method of the semiconductor device is described in detail below in conjunction with specific embodiments.

[0089] First, refer to FIG. 2A to FIG. 2H As shown, the above step S101 is performed: a plurality of semiconductor pillars 102 extending along a first direction z are formed, and the semiconductor pillars 102 include a first end 1021 and a second end 1022 opposite to each other in the first direction z.

[0090] In some embodiments, reference FIG. 2A to FIG. 2C As shown, forming a plurality of semiconductor pillars 102 extending along a first direction z includes: providing a semiconductor layer 10 , the semiconductor layer 10 having a first surface 10 a and a second surface 10 b opposite to each other in the first direction z; and

[0091] Part of the semiconductor layer 10 is removed to form a plurality of first grooves 10c extending along the first direction z and the second direction y and arranged along the third direction x. The remaining semiconductor layer 10 includes a plurality of active lines (not shown). The first grooves 10c are sunken from the first surface 10a to the second surface 10b.

[0092] In some embodiments, the material of the semiconductor layer 10 includes but is not limited to single-element semiconductor materials such as single crystal silicon. Specifically, the semiconductor layer 10 includes a silicon wafer.

[0093] In some embodiments, reference Figure 2B and Figure 2C As shown, the cross-section of the plurality of first grooves 10c parallel to the first direction z and the third direction x includes a rectangular or inverted trapezoidal shape. The dimension of the first grooves 10c along the first direction z is smaller than the thickness of the semiconductor layer 10.

[0094] In some embodiments, each active line is located between two adjacent first grooves 10c. The cross-section of each active line parallel to the first direction z and the third direction x includes a rectangle or a trapezoid.

[0095] In some embodiments, the first direction z may be the thickness direction of the semiconductor layer 10, but is not limited thereto. The first direction z may also be an acute angle with the thickness direction of the semiconductor layer 10. Any two of the first direction z, the second direction y, and the third direction x are perpendicular to each other, but are not limited thereto. The angle between any two of the first direction z, the second direction y, and the third direction x may also be an obtuse angle or an acute angle.

[0096] Next, please continue to refer to Figure 2B and Figure 2C As shown, during the process of performing the above step S101, the above step S103 is performed to form an insulating layer 11. In some embodiments, forming the insulating layer 11 includes: filling a dielectric layer 111 in the plurality of first grooves 10c. The dielectric layer 111 is used to isolate the plurality of active lines. The material of the dielectric layer 111 includes but is not limited to at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0097] Please refer again Figure 2B and Figure 2C As shown, after forming the dielectric layer 111, the above step S101 is continued. Forming a plurality of semiconductor pillars 102 extending along the first direction z further includes: removing part of the active line and part of the dielectric layer 111, forming a plurality of second grooves 10d extending along the first direction z and the third direction x and arranged along the second direction y, the plurality of second grooves 10d intersecting with the plurality of active lines, and the remaining active lines including a plurality of initial semiconductor pillars 101 extending along the first direction z and arranged in an array along the second direction y and the third direction x.

[0098] In some embodiments, the dimension of the second groove 10d along the first direction z is smaller than the thickness of the semiconductor layer 10. The dimension of the second groove 10d along the first direction z is smaller than the dimension of the first groove 10c along the first direction z.

[0099] In some embodiments, the above method is used to form intersecting first grooves 10c and second grooves 10d in the semiconductor layer 10, thereby forming a plurality of array-arranged initial semiconductor columns 101 in the semiconductor layer 10. The initial semiconductor column 101 includes a first initial end 1011 and a second initial end 1012 opposite to each other in the first direction z, and the second initial end 1012 is located on a side of the first initial end 1011 away from the second surface 10b. The cross-section of the initial semiconductor column 101 parallel to the first direction z and the third direction x is rectangular or trapezoidal.

[0100] In some embodiments, reference Figure 2B As shown, after forming a plurality of initial semiconductor pillars 101 , the method for manufacturing a semiconductor device further includes: forming a plurality of gate structures 12 in the plurality of second grooves 10 d , respectively.

[0101] In some embodiments, a plurality of gate structures 12 extend along the first direction z and the third direction x and are arranged at intervals along the second direction y. The gate structure 12 includes a gate line 121 and a gate insulating layer 122 disposed between the sidewall of the initial semiconductor column 101 and the gate line 121. The material of the gate line 121 includes a metal material and a non-metallic conductive material. The metal material includes but is not limited to at least one of copper, aluminum and tungsten. The non-metallic conductive material includes but is not limited to titanium nitride. The material of the gate insulating layer 122 includes but is not limited to at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0102] In some embodiments, reference Figure 2DAs shown, after forming a plurality of gate structures 12, the method for manufacturing a semiconductor device further includes: performing a doping process on the second initial end 1012 of the initial semiconductor column 101 to form a first electrode 131; and forming a capacitor (not shown) connected to the first electrode 131, the capacitor being located on a side of the first electrode 131 away from the semiconductor layer 10. The first electrode 131 is one of a source and a drain.

[0103] In some embodiments, please refer to Figure 2D As shown, after the capacitor is formed, the method for manufacturing the semiconductor device further includes: flipping the semiconductor layer 10 to place the second surface 10b of the semiconductor layer 10 on top, thinning the second surface 10b of the semiconductor layer 10 to form a thinned third surface 10e, and exposing the dielectric layer 111 in the first groove 10c.

[0104] In some embodiments, reference Figure 2E As shown, after the thinned third surface 10e is formed, the above step S103 is continued to be performed to form the insulating layer 11. The forming of the insulating layer 11 also includes: removing a portion of the dielectric layer 111 close to the first initial end 1011 to form a groove 111a extending along the first direction z and the second direction y, and the remaining dielectric layer 111 forms a first insulating layer 112, the groove 111a is sunken from the third surface 10e to the first surface 10a, and the groove 111a is arranged adjacent to the initial semiconductor column 101.

[0105] In some embodiments, an etching process is used to remove a portion of the dielectric layer 111 close to the first initial end 1011 . After removing the portion of the dielectric layer 111 close to the first initial end 1011 , the first initial end 1011 of the initial semiconductor pillar 101 protrudes from the first insulating layer 112 .

[0106] In some embodiments, a plurality of grooves 111a extend along the first direction z and the second direction y, and are arranged along the third direction x. The plurality of grooves 111a provide space for forming a plurality of sacrificial lines 142 described below. The groove bottom surface 111a1 of the groove 111a extends along the second direction y and the third direction x, that is, the insulating top surface 112a of the first insulating layer 112 close to the first initial end 1011 extends along the second direction y and the third direction x. In this way, the sacrificial line bottom surface 142b of the sacrificial line 142 formed in the groove 111a described below also extends along the second direction y and the third direction x. After removing the sacrificial line 142, the shape of the first bottom surface 162b of the first air gap 162 formed described below is easier to control. The first bottom surface 162b of the first air gap 162 is controlled to be located on the side of the bit line 151 close to the first electrode 131, and the first air gap 162 can better improve the coupling effect between adjacent bit lines 151. Specifically, the groove bottom surface 111a1 of the groove 111a includes a plane.

[0107] It should be noted that, in the present application, a plane refers to a substantially plane or a nearly plane. A plane may include a partially uneven surface caused by process reasons, but the whole plane substantially extends in two intersecting directions.

[0108] In some embodiments, reference Figure 2F and Figure 2J As shown, after forming the first insulating layer 112, continue to perform the above step S103, and the formation of the insulating layer 11 also includes: forming a sacrificial line 142 extending along the second direction y on the first insulating layer 112, and the sacrificial line 142 is located between the adjacent bit lines 151 and the adjacent semiconductor pillars 102; and forming a second insulating layer 113 covering the sacrificial line 142 and multiple bit lines 151.

[0109] In some embodiments, reference Figure 2F and Figure 2G As shown, forming a sacrificial line 142 extending along the second direction y on the first insulating layer 112 includes: forming a sacrificial line 142 in contact with the first insulating layer 112 in the groove 111 a , and the sacrificial line 142 is disposed adjacent to the initial semiconductor column 101 .

[0110] Specifically, a sacrificial layer 141 is formed on the first insulating layer 112 to fill the groove 111a and cover the initial semiconductor column 101, and a portion of the sacrificial layer 141 is removed to form a plurality of sacrificial lines 142 extending along the first direction z and the second direction y and spaced apart along the third direction x. The method of removing a portion of the sacrificial layer 141 includes, but is not limited to, chemical mechanical polishing.

[0111] In some embodiments, the sacrificial line 142 includes a sacrificial line top surface 142a and a sacrificial line bottom surface 142b opposite to each other in the first direction z, and the sacrificial line top surface 142a is located on a side of the sacrificial line bottom surface 142b away from the first insulating layer 112. The sacrificial line 142 also includes two sacrificial line side surfaces 142c opposite to each other in the third direction x, and the sacrificial line side surfaces 142c are connected between the sacrificial line top surface 142a and the sacrificial line bottom surface 142b.

[0112] Since the groove bottom surface 111 a 1 includes a plane, the sacrificial line bottom surface 142 b also includes a plane.

[0113] In some embodiments, the sacrificial line top surface 142a is flush or substantially flush with the end surface of the first initial end 1011, but is not limited thereto. In some embodiments, the sacrificial line top surface 142a also extends along the second direction y and the third direction x, which is beneficial for the first top surface 162a of the first air gap 162 formed after the sacrificial line 142 is removed to also extend along the second direction y and the third direction x, and the relative position between the first top surface 162a and the bit line 151 is easier to control.

[0114] In some embodiments, the sacrificial line side surface 142c also extends along two intersecting directions. For example, the sacrificial line side surface 142c extends along the first direction z and the second direction y, which is beneficial for the first side surface 162c of the first air gap 162 formed after the sacrificial line 142 is removed to also extend along the two intersecting directions.

[0115] Specifically, the sacrificial line side surface 142 c and the sacrificial line top surface 142 a also each include a flat surface.

[0116] In some embodiments, the shape of the cross section of the sacrificial line 142 parallel to the first direction z and the third direction x is a rectangle. The shape of the cross section of the sacrificial line 142 parallel to the second direction y and the third direction x is also a rectangle. The shape of the cross section of the sacrificial line 142 parallel to the second direction y and the first direction z is also a rectangle. The material of the sacrificial line 142 includes but is not limited to spin on carbon (Spin On Carbon, SOC).

[0117] In some embodiments, after forming a plurality of sacrificial lines 142, referring to Figures 2H to 2J As shown, the above step S101 is returned to be executed. Forming a plurality of semiconductor pillars 102 extending along the first direction z further includes: removing a portion of the first initial end 1011 of the initial semiconductor pillar 101 to form a first end 1021, the remaining initial semiconductor pillar 101 forms a semiconductor pillar 102, the sacrificial line 142 away from the first insulating layer 112, the sacrificial line top surface 142a is located on the side of the first end 1021 away from the second end 1022; and doping the second ends 1022 of the plurality of semiconductor pillars 102 to form a plurality of second electrodes 132.

[0118] In some embodiments of the present application, a portion of the first initial end 1011 of the initial semiconductor column 101 is removed to form the semiconductor column 102. Thus, in the first direction z, the sacrificial line top surface 142a of the sacrificial line 142 protrudes from the first end 1021 of the semiconductor column 102, that is, in the first direction z, the sacrificial line top surface 142a is located on the side of the first end 1021 away from the second end 1022. The method of removing a portion of the first initial end 1011 of the initial semiconductor column 101 includes but is not limited to an etching process.

[0119] In some embodiments, the first end 1021 of the semiconductor pillar 102 includes a second electrode 132, and the second end 1022 of the semiconductor pillar 102 includes the first electrode 131. The second electrode 132 is the other of the source and the drain. The semiconductor pillar 102 also includes a channel structure 1023 between the first electrode 131 and the second electrode 132.

[0120] In some embodiments, reference Fig.2I and Figure 2J As shown, after forming a plurality of semiconductor pillars 102, the step S103 is performed, and the step S102 is performed. A plurality of bit lines 151 are formed, and the plurality of bit lines 151 are located on one side of the plurality of semiconductor pillars 102 in the first direction z and are respectively in contact with the first ends 1021 of the plurality of semiconductor pillars 102, and the plurality of bit lines 151 extend along the second direction y and are spaced apart along the third direction x.

[0121] In some embodiments, forming a plurality of bit lines 151 includes: forming a plurality of bit lines 151 on the first ends 1021 of a plurality of semiconductor pillars 102. In the first direction z, the sacrificial line top surface 142a is located on the side of the bit line 151 away from the semiconductor pillar 102, and in the first direction z, the sacrificial line bottom surface 142b is located on the side of the bit line 151 close to the first electrode 131. A bit line 151 contacts the second electrode 132 of a row of semiconductor pillars 102 arranged along the second direction y. The material of the bit line 151 includes a metal material and a non-metallic conductive material. The metal material includes but is not limited to at least one of copper, aluminum and tungsten. The non-metallic conductive material includes but is not limited to titanium nitride.

[0122] In some embodiments, reference Figure 3A and Figure 3B As shown, after forming the plurality of bit lines 151 , the above step S103 is continued. Forming the insulating layer 11 further includes: forming a second insulating layer 113 covering the plurality of sacrificial lines 142 and the plurality of bit lines 151 .

[0123] In some embodiments, the second insulating layer 113 has a first region 113a and a second region 113b adjacent to each other in the second direction y, and both the first region 113a and the second region 113b overlap with the sacrificial line 142. Thus, after removing at least a portion of the second insulating layer 113 in the first region 113a to form an insulating layer opening 113c and retaining the second insulating layer 113 in the second region 113b, the sacrificial line 142 in the first region 113a and the second region 113b can be removed through the insulating layer opening 113c.

[0124] In some embodiments, Figure 3A As shown, the first region 113a and the second region 113b both extend along the third direction x and intersect with the sacrificial line 142; when the number of the first region 113a and the second region 113b is multiple, the multiple first regions 113a and the multiple second regions 113b are alternately arranged along the second direction y. In other embodiments, the first region 113a and the second region 113b may also extend along the second direction y and be adjacently arranged in the second direction y. In some embodiments, the material of the second insulating layer 113 is the same as that of the dielectric layer 111, but is not limited thereto.

[0125] In some embodiments, the sum of the areas of the plurality of second regions 113b is greater than the sum of the areas of the plurality of first regions 113a. Thus, after removing the plurality of sacrificial lines 142, the sum of the layout areas of the first air gaps 162 is greater than the sum of the layout areas of the second air gaps 163, which can better improve the coupling effect between adjacent bit lines 151.

[0126] In some embodiments, reference FIG. 3C to FIG. 3H As shown, forming the insulating layer 11 also includes: removing at least a portion of the second insulating layer 113 in the first area 113a, and retaining the second insulating layer 113 in the second area 113b, to form an insulating layer opening 113c exposing a portion of the sacrificial line 142; and removing the sacrificial line 142 through the insulating layer opening 113c, to form a first air gap 162 located in the second area 113b and between the second insulating layer 113 and the first insulating layer 112.

[0127] In some embodiments, reference FIG. 3C to FIG. 3H As shown, removing at least a portion of the second insulating layer 113 in the first region 113a and retaining the second insulating layer 113 in the second region 113b to form an insulating layer opening 113c exposing a portion of the sacrificial line 142 includes: forming a mask pattern 152 on the second insulating layer 113, the mask pattern 152 covering the second region 113b of the second insulating layer 113 and exposing the second insulating layer 113 in the first region 113a; and

[0128] Using the mask pattern 152 as a mask, a portion of the second insulating layer 113 in the first region 113a is removed and the second insulating layer 113 in the second region 113b is retained. An insulating layer opening 113c extending along the third direction x is formed on the second insulating layer 113. The insulating layer opening 113c exposes a portion of the sacrificial line 142.

[0129] In some embodiments, reference Figure 3F As shown, the plurality of insulating layer openings 113c intersect with the plurality of sacrificial lines 142, so as to facilitate the removal of the plurality of sacrificial lines 142 through the plurality of insulating layer openings 113c. In some embodiments, the plurality of insulating layer openings 113c extend along the third direction x and are arranged along the second direction y. In other embodiments, the extension direction of the insulating layer openings 113c may also intersect with the second direction y and the third direction x. In other embodiments, the extension direction of the insulating layer openings 113c may also be parallel to the second direction y, and the plurality of insulating layer openings 113c are arranged at intervals along the third direction x.

[0130] In some embodiments, reference FIG. 3I to FIG. 3KAs shown, after forming a plurality of insulating layer openings 113 c , a plurality of sacrificial lines 142 are removed through the plurality of insulating layer openings 113 c to form a first air gap 162 located in the second region 113 b and between the second insulating layer 113 and the first insulating layer 112 .

[0131] In some embodiments of the present application, after removing the plurality of sacrificial lines 142 through the insulating layer opening 113c, a plurality of initial air gaps 161 extending along the first direction z and the second direction y and arranged along the third direction x are formed. The initial air gaps 161 are connected to the insulating layer opening 113c, and each initial air gap 161 is located between two adjacent bit lines 151. Methods for removing the plurality of sacrificial lines 142 include, but are not limited to, dry etching.

[0132] The overlapped portion of the initial air gap 161 and the second region 113b constitutes a first air gap 162. The first top surface 162a and the first bottom surface 162b of the first air gap 162 are arranged opposite to each other in the first direction z, and the first side surface 162c of the first air gap 162 is connected between the first top surface 162a and the first bottom surface 162b.

[0133] The first top surface 162 a and the first bottom surface 162 b both extend along the second direction y and the third direction x, and the relative positions of the first top surface 162 a and the first bottom surface 162 b and the bit line 151 are more easily controlled.

[0134] The first side surface 162c extends along two intersecting directions, for example, along the first direction z and the second direction y, which is beneficial to increase the average spacing between the first air gap 162 and the two first side surfaces 162c in the third direction x, that is, increase the average size of the first air gap 162 in the third direction x, and the first air gap 162 has a better electrical isolation effect. The first air gap 162 can better isolate two adjacent bit lines 151, thereby better improving the coupling effect between adjacent bit lines 151.

[0135] Specifically, the first top surface 162 a , the first bottom surface 162 b , and the first side surface 162 c each include a plane.

[0136] Reference Figure 4C and Figure 4DAs shown, in the first direction z, the sacrificial line top surface 142a is located at the side of the bit line 151 away from the semiconductor pillar 102, and in the first direction z, the sacrificial line bottom surface 142b is located at the side of the bit line 151 close to the first electrode 131. After removing the sacrificial line 142, the first top surface 162a is located at the side of the bit line 151 away from the semiconductor pillar 102, and the first bottom surface 162b is located at the side of the bit line 151 close to the first electrode 131, that is, the first top surface 162a and the first bottom surface 162b of the first air gap 162 in the first direction z are located on both sides of the bit line 151. In this way, the first air gap 162 has a better electrical isolation effect, and the first air gap 162 can better isolate two adjacent bit lines 151, thereby better improving the coupling effect between adjacent bit lines 151.

[0137] In some embodiments, reference FIG. 4A to FIG. 4E As shown, forming the insulating layer 11 also includes: forming a third insulating layer 114 at the insulating layer opening 113c, forming a second air gap 163 connected to the first air gap 162, the first insulating layer 112, the remaining second insulating layer 113 and the third insulating layer 114 constitute the insulating layer 11, and the second air gap 163 and the first air gap 162 constitute an air gap 164.

[0138] In some embodiments, the material of the third insulating layer 114 is the same as that of the second insulating layer 113 .

[0139] Reference Figure 4A and Figure 4B As shown, the insulating layer 11 includes a plurality of air gap regions 11a extending along the first direction z and the second direction y and spaced apart along the third direction x. An air gap region 11a is provided between two adjacent bit lines 151, and an air gap 164 is provided in the air gap region 11a to electrically isolate the two adjacent bit lines 151. The plurality of air gaps 164 extend along the first direction z and the second direction y and are spaced apart along the third direction x. Each air gap 164 includes a first air gap 162 and a second air gap 163 adjacently provided and connected along the second direction y, the first air gap 162 being provided in the first air gap region 11b, and the second air gap 163 being provided in the second air gap region 11c.

[0140] In some embodiments, Figure 4EAs shown, the second air gap 163 includes a second top surface 163a and a second bottom surface 163b opposite to each other in the first direction z, the second top surface 163a is adjacent to the first top surface 162a and is located on the side of the first end 1021 away from the second end 1022, and the second bottom surface 163b is adjacent to the first bottom surface 162b. When the second air gap 163 is formed in the third insulating layer 114, due to process reasons, the second top surface 163a and the second bottom surface 163b both include arc surfaces, resulting in that the size of the second air gap 163 in the third direction x and the first direction z is difficult to control. Specifically, when approaching the arc vertex O of the second top surface 163a, the size of the second top surface 163a along the third direction x gradually decreases, that is, the size of the second top 1631 of the second air gap 163 along the third direction x gradually decreases.

[0141] In some embodiments of the present application, first, a plurality of sacrificial lines 142 are formed on the first insulating layer 112, and a sacrificial line 142 is disposed between two adjacent bit lines 151. Next, a second insulating layer 113 is formed to cover the plurality of sacrificial lines 142 and the plurality of bit lines 151, and an insulating layer opening 113c is formed in the second insulating layer 113. The plurality of sacrificial lines 142 are removed through the insulating layer opening 113c to form a first air gap 162 with a good electrical isolation effect. Finally, a third insulating layer 114 is formed at the insulating layer opening 113c to form a second air gap 163 connected to the first air gap 162, and an air gap 164 is formed to isolate the bit lines 151 and includes the first air gap 162 and the second air gap 163.

[0142] Since the first top surface 162a, the first bottom surface 162b, and the first side surface 162c of the first air gap 162 all include planes, the average size of the first air gap 162 along the third direction x is greater than the average size of the second air gap 163 along the third direction x, the first air gap 162 has a better electrical isolation effect, and the air gap 164 can better improve the coupling effect between adjacent bit lines 151. Moreover, the relative positions between the first top surface 162a and the first bottom surface 162b and the bit line 151 are easier to control, further improving the electrical isolation effect of the first air gap 162.

[0143] In addition, the sum of the areas of the first air gap regions 11b is greater than the sum of the areas of the second air gap regions 11c, so that the sum of the layout areas of the first air gaps 162 is greater than the sum of the layout areas of the second air gaps 163. In this way, the average size of the air gaps 164 along the third direction x increases, further improving the electrical isolation effect of the air gaps 164 and the coupling effect between adjacent bit lines 151.

[0144] The present application also provides a semiconductor device obtained by the manufacturing method of the semiconductor device. 4A to 4FThe semiconductor device of some embodiments of the present application is described in detail. The semiconductor device includes a plurality of semiconductor pillars 102 , a plurality of bit lines 151 , an insulating layer 11 and a plurality of gate structures 12 .

[0145] Reference FIG. 4C to FIG. 4F As shown, a plurality of semiconductor pillars 102 extend along a first direction z, and are arranged in an array along a second direction y and a third direction x. The semiconductor pillar 102 includes a first end 1021 and a second end 1022 that are opposite to each other in the first direction z. The first end 1021 of the semiconductor pillar 102 includes a second electrode 132, the second end 1022 of the semiconductor pillar 102 includes a first electrode 131, and the semiconductor pillar 102 also includes a channel structure 1023 located between the second electrode 132 and the first electrode 131. One of the first electrode 131 and the second electrode 132 is a source, and the other of the first electrode 131 and the second electrode 132 is a drain. The first electrode 131 is connected to a capacitor. The second electrode 132 is connected to a bit line 151. As shown in FIG. Figure 4C and Figure 4E As shown, the shape of the cross section of the semiconductor pillar 102 parallel to the first direction z and the third direction x can be a rectangle. Figure 4D As shown, the shape of the cross section of the semiconductor pillar 102 parallel to the first direction z and the third direction x may also be an inverted trapezoid.

[0146] In some embodiments, any two of the first direction z, the second direction y, and the third direction x intersect each other. Specifically, any two of the first direction z, the second direction y, and the third direction x are perpendicular to each other.

[0147] Reference FIG. 4A to FIG. 4E As shown, a plurality of bit lines 151 are located on one side of a plurality of semiconductor pillars 102 in a first direction z, and are respectively in contact with and connected to the second electrodes 132 of the first ends 1021 of the plurality of semiconductor pillars 102. A plurality of bit lines 151 extend along a second direction y and are spaced apart along a third direction x. A bit line 151 is connected to a column of semiconductor pillars 102 arranged along the second direction y. The material of the bit line 151 includes a metal material and a non-metallic conductive material. The metal material includes, but is not limited to, at least one of copper, aluminum, and tungsten. The non-metallic conductive material includes, but is not limited to, titanium nitride.

[0148] Reference FIG. 4A to FIG. 4EAs shown, the insulating layer 11 covers a plurality of bit lines 151 and is located between a plurality of semiconductor pillars 102. The insulating layer 11 includes a plurality of air gap regions 11a, and the plurality of air gap regions 11a extend along the second direction y and are arranged along the third direction x. An air gap region 11a is provided between two adjacent bit lines 151. Each air gap region 11a includes a first air gap region 11b and a second air gap region 11c that are adjacently provided in the second direction y. The interior of the insulating layer 11 includes an air gap 164 enclosed by the inner surface of the insulating layer 11, the air gap 164 is located in the air gap region 11a, and an air gap 164 is provided between two adjacent bit lines 151 to electrically isolate the two adjacent bit lines 151 and improve the coupling effect between the adjacent bit lines 151.

[0149] Each air gap 164 includes a first air gap 162 located in the first air gap region 11b and a second air gap 163 located in the second air gap region 11c. The first air gap 162 is adjacent to and connected to the second air gap 163 in the second direction y. A plurality of first air gaps 162 are arranged in an array along the second direction y and the third direction x, a second air gap 163 is provided between two adjacent first air gaps 162 in the second direction y, and a bit line 151 is provided between two adjacent first air gaps 162 in the third direction x.

[0150] The first air gap 162 includes a first top surface 162a and a first bottom surface 162b opposite to each other in the first direction z, and the first top surface 162a is located on a side of the first end 1021 away from the second end 1022. The first air gap 162 also includes a first side surface 162c, and two opposite first side surfaces 162c are connected between the first top surface 162a and the first bottom surface 162b in the third direction x.

[0151] The first top surface 162a extends along the second direction y and the third direction x, so that the formation process of the first top surface 162a is more controllable, and it is easier to locate the first top surface 162a on the side of the bit line 151 away from the second end 1022, and the average size of the first air gap 162 along the third direction x is larger, and the first air gap 162 can better improve the coupling effect between adjacent bit lines 151.

[0152] The first bottom surface 162b also extends along the second direction y and the third direction x, so that the formation process of the first bottom surface 162b is more controllable, and it is easier to locate the first bottom surface 162b on the side of the bit line 151 close to the first electrode 131. The average size of the first air gap 162 along the third direction x is larger, and the first air gap 162 can better improve the coupling effect between adjacent bit lines 151.

[0153] The first side surface 162c also extends along two intersecting directions, so that the formation process of the first side surface 162c is more controllable, the size of the first air gap 162 along the third direction x is more controllable, and the first air gap 162 can better improve the coupling effect between adjacent bit lines 151. For example, referring to Figure 4C As shown, the first side surface 162c extends along the first direction z and the second direction y; or, referring to Figure 4D As shown, the first side surface 162c extends along the fourth direction and the second direction y, the angle between the fourth direction and the first direction z is an acute angle, and the fourth direction intersects the second direction y and the third direction x.

[0154] Specifically, the first bottom surface 162 b , the first top surface 162 a , and the first side surface 162 c each include a plane.

[0155] In some embodiments, a size of the first top 1621 of the first air gap 162 in the third direction x is less than or equal to a size of the first bottom 1622 of the first air gap 162 in the third direction x, the first top 1621 and the first bottom 1622 are arranged opposite to each other in the first direction z, and the first top 1621 of the first air gap 162 is located on the side of the first end 1021 away from the second end 1022.

[0156] Specifically, refer to Figure 4C As shown, the cross-section of the first air gap 162 parallel to the first direction z and the third direction x is rectangular. At this time, the size of the first top 1621 of the first air gap 162 in the third direction x is equal to the size of the first bottom 1622 of the first air gap 162 in the third direction x. Figure 4D As shown, the shape of the cross section of the first air gap 162 parallel to the first direction z and the third direction x is a trapezoid or tends to be a trapezoid. At this time, the size of the first top 1621 of the first air gap 162 in the third direction x is smaller than the size of the first bottom 1622 of the first air gap 162 in the third direction x.

[0157] Reference Figure 4E As shown, the second air gap 163 includes a second top surface 163a and a second bottom surface 163b opposite to each other in the first direction z, the second top surface 163a is adjacent to the first top surface 162a and is located on the side of the first end 1021 away from the second end 1022, and the second bottom surface 163b is adjacent to the first bottom surface 162b.

[0158] In some embodiments, the size of the second top 1631 of the second air gap 163 in the third direction x is smaller than the size of the second bottom 1632 of the second air gap 163 in the third direction x, and the second top 1631 and the second bottom 1632 are arranged opposite to each other in the first direction z, and the second top 1631 is located on the side of the first end 1021 away from the second end 1022.

[0159] Specifically, the second top surface 163a and the second bottom surface 163b both include arc surfaces. The second top surface 163a of the second air gap 163 also includes an arc vertex O. In the direction close to the arc vertex O, the size of the second air gap 163 along the third direction x gradually decreases, that is, the second top 1631 of the second air gap 163 is gradually narrowed.

[0160] It should be noted that, in combination with the above, the inner surface of the second air gap 163 is different from the inner surface of the first air gap 162, and the inner surface of the first air gap 162 is more controllable in the process. Since the first bottom surface 162b, the first top surface 162a and the first side surface 162c all include planes, the second top surface 163a and the second bottom surface 163b both include arc surfaces. The relative positions of the first bottom surface 162b and the first top surface 162a of the first air gap 162 and the bit line 151 are easier to control, and the size of the first air gap 162 along the third direction x is easier to control. Therefore, compared with the second air gap 163, the first air gap 162 has a better electrical isolation effect and can better improve the coupling effect between adjacent bit lines 151.

[0161] In some embodiments, the average size of the second air gap 163 along the third direction x is smaller than the average size of the first air gap 162 , and the electrical isolation effect of the first air gap 162 is better than that of the second air gap 163 .

[0162] In some embodiments, the sum of the areas of the first air gap regions 11b is greater than the sum of the areas of the second air gap regions 11c, so that the sum of the areas of the layout regions of the multiple first air gaps 162 is greater than the sum of the areas of the layout regions of the multiple second air gaps 163, further increasing the average size of the air gap 164 along the third direction x and improving the coupling effect between two adjacent bit lines 151.

[0163] In some embodiments, the arc vertex O of the second top surface 163a is located on the side of the first top surface 162a away from the first end 1021, thereby increasing the size of the second air gap 163 along the first direction z, improving the electrical isolation effect of the second air gap 163, and improving the coupling effect between two adjacent bit lines 151.

[0164] Reference Figure 4FAs shown, a plurality of gate structures 12 extend along the first direction z and the third direction x, and are arranged at intervals along the second direction y. One gate structure 12 is located between two adjacent rows of semiconductor pillars 102 in the second direction y. Each gate structure 12 includes a gate line 121 and a gate insulating layer 122 located between the gate line 121 and the sidewall of the semiconductor pillar 102.

[0165] In addition, refer to Figure 5 and Figure 6 As shown, based on the same inventive concept, the present application further provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the above embodiments.

[0166] Among them, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0167] In some embodiments, reference Figure 5 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 may be integrated into a three-dimensional memory card.

[0168] Among them, the three-dimensional memory card includes any one of PC card (PCMCIA, Personal Computer Three-Dimensional Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, three-dimensional memory, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0169] In other embodiments, referring to Figure 6 As shown, the storage system 400 includes a plurality of memories 200 and a controller 300. The storage system 400 is integrated into a solid state drive (SSD).

[0170] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0171] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, laptops, and enterprise storage arrays.

[0172] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes for data read from or written to the memory 200.

[0173] Of course, the controller 300 may also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0174] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0175] Please refer to Figure 7 Some embodiments of the present application further provide an electronic device 500. The electronic device 500 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0176] The electronic device 500 may include the above-mentioned storage system 400 and a host 600 , and the host 600 includes at least one of a central processing unit (CPU) and a cache.

[0177] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: a plurality of semiconductor pillars extending along a first direction, the semiconductor pillars comprising first and second ends opposite to each other in the first direction; a plurality of bit lines, located at one side of the plurality of semiconductor pillars in the first direction and respectively connected to the first ends of the plurality of semiconductor pillars, the plurality of bit lines extending along the second direction and arranged at intervals along the third direction, and any two of the first direction, the second direction and the third direction intersecting with each other; as well as An insulating layer is located on the plurality of bit lines and between the plurality of semiconductor pillars, the interior of the insulating layer includes an air gap enclosed by the inner surface of the insulating layer, the air gap is arranged between two adjacent bit lines, the air gap includes a first air gap, a first top surface of the first air gap extends along the second direction and the third direction, and the first top surface is located on the side of the first end away from the second end.

2. The semiconductor device according to claim 1, wherein: The first top surface includes a flat surface.

3. The semiconductor device according to claim 1 or 2, characterized in that: The air gap further includes a second air gap adjacent to and connected to the first air gap in the second direction, a second top surface of the second air gap includes an arc surface, the second top surface is adjacent to the first top surface and is located on a side of the first end away from the second end.

4. The semiconductor device according to claim 3, characterized in that The insulating layer further includes a first air gap region provided with the first air gap and a second air gap region provided with the second air gap, and a sum of areas of the first air gap regions is greater than a sum of areas of the second air gap regions.

5. The semiconductor device according to claim 3, characterized in that The arc surface vertex of the arc surface is located on a side of the first top surface away from the first end.

6. The semiconductor device according to claim 1, wherein: The size of the first top of the first air gap in the third direction is smaller than or equal to the size of the first bottom of the first air gap in the third direction, the first top is arranged opposite to the first bottom in the first direction, and the first top of the first air gap is located on the side of the first end away from the second end.

7. The semiconductor device according to claim 3 or 6, characterized in that: The second top of the second air gap has a smaller dimension in the third direction than the second bottom of the second air gap, the second top is opposite to the second bottom in the first direction, and the second top is located on the side of the first end away from the second end.

8. The semiconductor device according to claim 3, characterized in that A plurality of the first air gaps are arranged in an array along the second direction and the third direction, a second air gap is arranged between two adjacent first air gaps in the second direction, and a bit line is arranged between two adjacent first air gap regions in the third direction.

9. The semiconductor device according to claim 1, wherein: The first air gap further includes a first bottom surface, the first bottom surface is disposed opposite to the first top surface in the first direction, and the first bottom surface extends along the second direction and the third direction.

10. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a plurality of semiconductor pillars extending along a first direction, the semiconductor pillars including first and second ends opposite to each other in the first direction; forming a plurality of bit lines, the plurality of bit lines being located on one side of the plurality of semiconductor pillars in the first direction and respectively contacting the first ends of the plurality of semiconductor pillars, the plurality of bit lines extending along the second direction and being arranged at intervals along the third direction, and any two of the first direction, the second direction and the third direction intersecting with each other; and An insulating layer is formed, the insulating layer is located on the plurality of the bit lines and between the plurality of the semiconductor pillars, the interior of the insulating layer includes an air gap enclosed by the inner surface of the insulating layer, the air gap is arranged between two adjacent bit lines, the air gap includes a first air gap, a first top surface of the first air gap extends along the second direction and the third direction, and the first top surface is located on a side of the first end away from the second end.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The forming of the insulating layer comprises: forming a first insulating layer between the plurality of semiconductor pillars; forming a sacrificial line extending along a second direction on the first insulating layer, wherein the sacrificial line is located between adjacent bit lines and adjacent semiconductor pillars; and A second insulating layer is formed to cover the sacrificial line and the plurality of bit lines.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The forming of the insulating layer further comprises: removing at least a portion of the second insulating layer in the first region and retaining the second insulating layer in the second region to form an insulating layer opening exposing a portion of the sacrificial line, wherein both the first region and the second region overlap with the sacrificial line and are adjacently disposed in the second direction; and The sacrificial line is removed through the insulating layer opening to form a first air gap located in the second area and between the second insulating layer and the first insulating layer.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: The forming of the insulating layer also includes: forming a third insulating layer at the opening of the insulating layer to form a second air gap connected to the first air gap, the first insulating layer, the remaining second insulating layer and the third insulating layer constitute the insulating layer, and the second air gap and the first air gap constitute the air gap.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The sum of the areas of the second regions is greater than the sum of the areas of the first regions.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: The forming of the sacrificial line extending along the second direction on the first insulating layer comprises: forming a plurality of the sacrificial lines spaced apart along the third direction; The forming of the insulating layer opening exposing the portion of the sacrificial line comprises: The insulating layer opening extending along the third direction is formed on the second insulating layer.

16. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The forming of a plurality of semiconductor pillars extending along the first direction comprises: forming a plurality of initial semiconductor pillars extending along the first direction, the initial semiconductor pillars comprising first initial ends and second initial ends opposite to each other in the first direction; The forming of the first insulating layer between the plurality of semiconductor pillars comprises: filling a dielectric layer between the plurality of initial semiconductor pillars; and A portion of the dielectric layer close to the first initial end is removed to form a groove extending along the first direction and the second direction, and the remaining dielectric layer forms the first insulating layer. The groove is disposed adjacent to the initial semiconductor column.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The forming of a sacrificial line extending along the second direction on the first insulating layer comprises: forming the sacrificial line in the groove and contacting the first insulating layer, the sacrificial line being disposed adjacent to the initial semiconductor column; and The forming of a plurality of semiconductor pillars extending along the first direction also includes: removing a portion of a first initial end of the initial semiconductor pillar to form the first end, the remaining initial semiconductor pillar forming the semiconductor pillar, and the sacrificial line top surface away from the first insulating layer is located on the side of the first end away from the second end.

18. A storage system, characterized in that: include: A memory, comprising a semiconductor device as claimed in any one of claims 1 to 9; as well as The controller is connected to the memory and is used to control the memory.

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