Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and is applied to the technical field of semiconductors. According to the invention, the shapes and areas of the insulating structures in the peripheral region of the substrate and the units can be different, so that different isolation effects are achieved, and part of the insulating structures are prevented from peeling off.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor memory structure and a preparation method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the DRAM cell with only a planar gate structure under the current mainstream development trend. Generally speaking, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from the bit line and the word line. However, due to the limitations of process technology, the existing DRAM cell with a recessed gate structure still has many defects, and further improvements are needed to effectively improve the performance and reliability of the relevant memory components. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor structure and a method for preparing the same, by setting the portions of the insulating structure located in the first zone and the second zone into different shapes, and setting the insulating structure in the second zone into a second insulating structure with a large rectangular pattern and covering the entire substrate of the second zone, to achieve different isolation effects and avoid peeling of part of the insulating structure.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a method for preparing a semiconductor structure, which may at least include:

[0005] Providing a substrate, the substrate comprising a first region, a second region, and a third region;

[0006] forming a first surrounding pattern, wherein the first surrounding pattern includes a plurality of strip patterns, the strip patterns extending in a first direction and spanning across the substrates of the first region and the second region, and the plurality of strip patterns including a connected end portion, the connected end portion also extending in the first direction to the substrate of the third region;

[0007] forming a dielectric layer, wherein the dielectric layer is located on the substrate and fills the gaps between adjacent first surrounding patterns;

[0008] forming a hard mask layer, the hard mask layer comprising a plurality of second surrounding patterns, the second surrounding patterns being located on the dielectric layer in the first region and the second region and being staggered with the first surrounding patterns, the second surrounding patterns comprising a long axis extending in a second direction perpendicular to the first direction and a short axis extending in the first direction;

[0009] forming a barrier layer on the dielectric layer and the hard mask layer, wherein the barrier layer has an opening exposing the second surrounding pattern of the second region;

[0010] Using the barrier layer as a mask, removing the second surrounding pattern corresponding to the opening;

[0011] Using the remaining hard mask layer as a mask, removing a portion of the dielectric layer and the first surrounding pattern to form a groove of the substrate exposing the first area and the second area;

[0012] An insulating layer is formed to fill the groove.

[0013] Optionally, the first surrounding pattern may include: a plurality of bit line patterns and a spacer pattern surrounding the bit line patterns, and the bit line pattern includes the connected end portions.

[0014] Optionally, the end portion may include insulating material.

[0015] Optionally, the spacer pattern may be in the shape of a ring frame.

[0016] Optionally, before forming the first surrounding pattern, the method may further include:

[0017] A plurality of word line structures are formed, the plurality of word line structures are disposed in the substrate of the first region in a spaced-apart manner and are interlaced with the plurality of bit line patterns.

[0018] Optionally, the word line structure may further include an insulating capping layer, and the insulating layer filled in the groove contacts the insulating capping layer.

[0019] Optionally, a bottom surface of the groove in the first region may be higher than a bottom surface of the groove in the second region.

[0020] Optionally, top surfaces of the spacer pattern in the first region and in the second region may be at different levels.

[0021] Optionally, a top surface of the spacer pattern located in the first region may be higher than a top surface of the spacer pattern located in the second region.

[0022] In a second aspect, based on the same inventive concept, the present invention further provides a semiconductor structure, which may at least include:

[0023] a substrate comprising a first region and a second region;

[0024] A plurality of word line structures extending along a second direction and spaced apart from each other in a first direction perpendicular to the second direction are disposed in the substrate of the first region;

[0025] a plurality of bit line patterns extending along the first direction and arranged on the word line structure spaced apart from each other in the second direction;

[0026] A plurality of first insulating structures, located on the word line structure in the first region, the first insulating structure comprising a ring-shaped frame pattern, and the first insulating structure further comprising a long axis extending in the second direction and a short axis extending in the first direction;

[0027] A second insulating structure is located on the substrate of the second zone, the second insulating structure includes a large rectangular pattern, and the second insulating structure also includes a long side extending in the second direction and a short side extending in the first direction, wherein the length of the short side is greater than the length of the short axis.

[0028] Optionally, the length of the long side may be greater than the length of the long axis.

[0029] Optionally, in a third direction perpendicular to the substrate, a bottom surface of the second insulating structure may be lower than a bottom surface of the first insulating structure.

[0030] Optionally, the word line structure may include an insulating capping layer, and the first insulating structure may directly contact the insulating capping layer.

[0031] In the present invention, by depositing a barrier layer with an opening and removing all the second surrounding patterns on the second zone based on the barrier layer, the shapes of the gaps of the insulating structures to be formed on the first zone and the second zone are adjusted to be different, and the gaps on the second zone for forming the insulating structure are enlarged, thereby forming insulating structures of different shapes in the first zone and the second zone, and setting the insulating structure in the second zone to a second insulating structure in the shape of a large rectangular pattern and covering the entire base of the second zone, thereby achieving different isolation effects and avoiding the peeling of part of the insulating structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0033] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present invention;

[0034] Figure 2 to Figure 16 It is a structural schematic diagram of a method for preparing a semiconductor structure provided in one embodiment of the present invention during the preparation process.

[0035] Wherein, the accompanying drawings are marked as follows:

[0036] 100-substrate, 101-first region, 102-second region, 103-third region, 110-trench isolation, 120-word line structure, 121-gate dielectric layer, 122-work function layer, 123-conductive layer, 124-insulating cap layer, 130-insulating layer, 140-bit line pattern (strip pattern), 141-first bit line pattern, 142-second bit line pattern, 143-third bit line pattern (adjacent end), 150-spacer pattern, 160-first surrounding pattern, 200-dielectric layer, 300-hard mask layer, 170-second surrounding pattern , 170a-the short axis of the second surrounding pattern, 170b-the long axis of the second surrounding pattern, 400-barrier layer, 210-groove, 211-the first groove, 212-the second groove, H-the height difference between the bottom surfaces of the first groove and the second groove, 500-insulating layer, 501-the first insulating structure, 502-the second insulating structure, 501a-the long axis of the first insulating structure, 501b-the short axis of the first insulating structure, 502a-the long side of the second insulating structure, 502b-the short side of the second insulating structure, D1-the first direction, D2-the second direction, and D3-the third direction.

[0037] In the drawings, the same reference numerals are used for the same components and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0038] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0039] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something without intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something with intervening features or layers.

[0040] For ease of understanding, a first direction D1, a second direction D2 and a third direction D3 are defined below, wherein the first direction D1 is a direction parallel to the surface of the substrate 100; the third direction D3 is a direction perpendicular to the surface of the substrate 100, and the second direction D2 is a direction perpendicular to the plane where the first direction D1 and the third direction D3 are located.

[0041] Please refer to Figure 1 As shown, what is depicted is a schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present invention. Figure 1 As shown, the method for preparing a semiconductor structure provided by an embodiment of the present invention at least comprises the following steps:

[0042] Step S101, providing a substrate, wherein the substrate includes a first area, a second area, and a third area;

[0043] Step S102, forming a first surrounding pattern, wherein the first surrounding pattern includes a plurality of strip patterns, wherein the strip patterns extend in a first direction and span across the substrate of the first area and the second area, and the plurality of strip patterns include a connected end portion, and the connected end portion further extends in the first direction to the substrate of the third area;

[0044] Step S103, forming a dielectric layer, wherein the dielectric layer is located on the substrate and fills the gaps between adjacent first surrounding patterns;

[0045] Step S104, forming a hard mask layer, the hard mask layer comprising a plurality of second surrounding patterns, the second surrounding patterns being located on the dielectric layer in the first region and the second region and interlaced with the first surrounding patterns, the second surrounding patterns comprising a long axis extending in a second direction perpendicular to the first direction and a short axis extending in the first direction;

[0046] Step S105, forming a barrier layer on the dielectric layer and the hard mask layer, wherein the barrier layer has an opening exposing the second surrounding pattern of the second region;

[0047] Step S106, using the barrier layer as a mask to remove the second surrounding pattern corresponding to the opening;

[0048] Step S107, using the remaining hard mask layer as a mask, removing a portion of the dielectric layer and the first surrounding pattern to form a groove of the substrate exposing the first area and the second area;

[0049] Step S108 , forming an insulating layer to fill the groove.

[0050] In order to enable a person skilled in the art to which the present invention belongs to easily understand the method for preparing a semiconductor structure in the embodiment of the present invention, the method for preparing a semiconductor structure proposed by the present invention will be further described below in conjunction with various structural schematic diagrams of the preparation method during the preparation process. Figure 2 to Figure 16 It is a structural schematic diagram of the preparation method of the semiconductor structure provided in an embodiment of the present invention during the preparation process.

[0051] Please refer to Figure 2 and Figure 3 As shown, Figure 2 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Figure 3 for Figure 2 The semiconductor structure shown is a schematic cross-sectional view taken along line AA.

[0052] Execute the above step S101: provide a substrate 100, the substrate 100 includes a first region 101, a second region 102 and a third region 103; the first region 101 is, for example, a cell region with a relatively high component density of a semiconductor memory, and the second region 102 and the third region 103 are, for example, both peripheral regions with a relatively low component density of a semiconductor memory. The substrate 100 is any suitable substrate material known in the art, for example, a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto; the first region 101, the second region 102 and the third region 103 can be arranged adjacent to each other in sequence along the first direction D1, but not limited thereto.

[0053] In one embodiment, a plurality of trench isolations 110 arranged in sequence along the first direction D1 may be provided in the substrate 100, wherein one of the trench isolations 110 has a larger width than the other trench isolations 110 and is located on one side of all other trench isolations 110, and the trench isolation 110 is located in the second area 102 and the third area 103 to define the peripheral area and the unit area of ​​the substrate 100. Specifically, the trench isolation 110 may include a single layer or multiple layers of dielectric material, and applicable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorinated silicon glass, carbon silicon oxide, spin-on silicon glass, porous low dielectric constant dielectric materials, organic polymer dielectric materials, or a combination of the above materials, but not limited thereto. In addition, a plurality of word line structures 120 may be provided in the substrate 100 of the first area 101. The multiple word line structures 120 are arranged in a spaced relationship along the first direction D1 and are in the shape of long strips extending along the second direction D2. The details of the word line structures 120 may include a gate dielectric layer 121 (material is, for example, a high dielectric constant), a work function layer 122 (material is, for example, titanium nitride), a conductive layer 123 (material is, for example, metal tungsten) and an insulating cap layer 124 (material is, for example, an oxide or a nitride), but are not limited thereto. Furthermore, an insulating layer 130 may be disposed on the substrate 100, and the insulating layer 130 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer (such as a silicon oxide layer). Figure 2 It may also be a composite layer (not shown), such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but is not limited thereto.

[0054] Please continue to refer to Figure 2 and Figure 3 As shown, the above step S102 is performed: a first surrounding pattern 160 is formed on the first area 101, the second area 102 and the third area 103 of the substrate 100; wherein the first surrounding pattern 160 may include a plurality of bit line patterns 140 and a spacer pattern 150 surrounding the bit line pattern 140; in detail, the bit line pattern 140 may include a first bit line pattern 141, a second bit line pattern 142 and a third bit line pattern 143 respectively located on the substrate 100 in the first area 101, the second area 102 and the third area 103; wherein the first bit line pattern 141 and the second bit line pattern 142 both extend along the first direction D1 and the short ends of the two are connected at the junction of the first area 101 and the second area 102 (such as Figure 2The first bit line pattern 141 and the second bit line pattern 142 are connected at their short ends and are shaped like strips across the first area 101 and the second area 102 along the first direction D1. Based on this, the first bit line pattern 141 and the second bit line pattern 142 are connected at their short ends and are shaped like strips across the first area 101 and the second area 102. In the embodiment of the present invention, the first bit line pattern 141 and the second bit line pattern 142 are connected at their short ends and are shaped like strips as a whole, so that the multiple bit line patterns 140 included in the first surrounding pattern 160 are divided into multiple strip patterns spaced apart from each other along the second direction D2 in the form of strip patterns, and the multiple second bit line patterns 142 in the multiple strip patterns are extended in the first direction D1 to the substrate 100 of the third area 103 and are connected at one end thereof as the third bit line pattern 143. In this way, the gap wall pattern 150 used to isolate the first bit line pattern 141, the second bit line pattern 142 and the third bit line pattern 143 and located on their side walls respectively can be specifically shaped like a ring frame. In one embodiment, the first bit line pattern 141 located in the first region 101 may include in detail a semiconductor layer (not shown, for example, including semiconductor materials such as doped polysilicon and doped amorphous silicon), a barrier layer (not shown, for example, titanium and / or titanium nitride), a metal layer (not shown, for example, metal tungsten) and a capping layer (not shown, for example, silicon oxide or silicon nitride) stacked in sequence, the second bit line pattern 142 located in the second region 102 and the third bit line pattern 143 located in the third region 103 may include in detail an insulating material such as silicon oxide and silicon nitride; the top surfaces of the spacer pattern 150 in the first region 101 and the second region 102 are at different levels, for example Fig.16 The top surface of the spacer pattern 150 in the first region 101 may be higher than the top surface of the spacer pattern 150 in the second region 102, and the spacer structure formed on the sidewall of the bit line structure based on the spacer pattern 150 may include a single layer of dielectric material (such as Figure 3 150), such as a silicon oxide layer or silicon nitride, may also include multiple layers of dielectric materials (not shown), such as a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or nitrogen-doped silicon carbide, but is not limited thereto.

[0055] Please refer to Figure 4 and Figure 5 As shown, Figure 4 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Figure 5 for Figure 4 The semiconductor structure shown is a schematic cross-sectional view taken along line AA.

[0056] Execute the above step S103: using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., a dielectric layer 200 is formed on the first area 101, the second area 102 and the third area 103 of the substrate 100 to fill the gaps between the adjacent first surrounding patterns 160 on the substrate 100; in one embodiment, the top surface of the dielectric layer 200 may be higher than the top surfaces of the plurality of bit line patterns 140 in the first surrounding pattern 160 to bury the film layer structure on the substrate 100, and the material of the dielectric layer 200 may be, for example, a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or nitrogen-doped silicon carbide, but is not limited thereto.

[0057] Please refer to Figure 6 and Figure 7 As shown, Figure 6 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Figure 7 for Figure 6 The semiconductor structure shown is a schematic cross-sectional view taken along line AA.

[0058] Execute the above step S104: form a hard mask layer 300 (material is, for example, silicon oxide or silicon nitride) including a plurality of second surrounding patterns 170 on the dielectric layer 200 to prepare for the location of the first insulating structure 501 and the second insulating structure 502 to be formed subsequently; in one embodiment, the hard mask layer 300 has the plurality of second surrounding patterns 170 on parts of the first area 101 and the second area 102; wherein the plurality of second surrounding patterns 170 are all in the shape of a closed annular frame as a whole and are arranged in sequence along the first direction D1, and the second surrounding pattern 170 may include a short axis 170a extending in the first direction D1 and a long axis 170b extending in the second direction D2; illustratively, the length of the long axis 170b of the plurality of second surrounding patterns 170 located in the first area 101 may be less than the length of the long axis 170b of the plurality of second surrounding patterns 170 located in the second area 102, but is not limited thereto.

[0059] Please refer to Figure 8 and Fig. 9 As shown, Figure 8 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Fig. 9 for Figure 8 The semiconductor structure shown is a schematic cross-sectional view taken along line AA.

[0060] Execute the above-mentioned step S105: form a barrier layer 400 (material is, for example, oxide or nitride) on the first area 101 and the third area 103 of the substrate 100; specifically, the barrier layer 400 specifically covers the hard mask layer 300 and fills the gaps in the second surrounding patterns 170 in the hard mask layer 300, so that when observed from the top view schematic diagram, all the second surrounding patterns 170 on the first area 101 and all the hard mask layers 300 on the third area 103 are shielded by the barrier layer 400; in addition, the barrier layer 400 also has an opening, so that when observed from the top view schematic diagram, the opening can expose all film layer structures on the second area 102, for example, expose multiple second surrounding patterns 170 of the hard mask layer 300 on the second area 102 and the dielectric layer 200 between adjacent second surrounding patterns 170.

[0061] Please refer to Fig.10 and Fig.11 As shown, Fig.10 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Fig.11 for Fig.10 The schematic cross-sectional view of the semiconductor structure along the AA cut line is shown. The above step S106 is performed: Then, an etching process such as a dry etching process or a wet etching process can be used to remove all the second surrounding patterns 170 on the second region 102 exposed by the opening in the barrier layer 400 along the third direction D3 by using the barrier layer 400 as a mask, until the dielectric layer 200 thereunder is exposed, and then the barrier layer 400 is removed by an etching process such as a dry etching process. It should be understood that after forming the hard mask layer 300 having the multiple second surrounding patterns 170, the embodiment of the present invention does not directly perform the above steps S107 and S108 to form multiple first insulating structures 501 in the shape of annular frames on the word line structure 120 and the second area 102, but adds the steps of depositing the barrier layer 400 with openings and removing all the second surrounding patterns 170 on the second area 102 based on the barrier layer 400. Furthermore, through the added steps S105 and S106, the shapes of the gaps reserved on the first area 101 and the second area 102 for subsequent formation of insulating structures are different, and the shapes of the insulating structures subsequently formed in the first area 101 and the second area 102 are different, thereby achieving different isolation effects and avoiding the problem of peeling of some insulating structures.

[0062] Please refer to Fig.12 and Fig.13 As shown, combined Fig.11 As shown, Fig.12 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Fig.13 for Fig.12 The schematic cross-sectional view of the semiconductor structure along the AA cut line is shown. The above step S107 is performed: the hard mask layer 300 remaining on the first area 101 and the third area 103 can be used as a mask, and the dielectric layer 200 not shielded by the hard mask layer 300 and the first surrounding pattern 160 filled with the dielectric layer 200 are etched downward along the third direction D3 to remove part of the dielectric layer 200 and the first surrounding pattern 160, so as to form a groove 210 of the substrate 100 exposing the first area 101 and the second area 102. Specifically, since the portion of the remaining hard mask layer 300 located on the first area 101 after executing the above step S106 is a plurality of second surrounding patterns 170 with gaps and in the shape of an annular frame, during the etching process of the present step S107 based on the remaining hard mask layer 300, the dielectric layer 200 and the first surrounding pattern 160 located on the second area 102 are all removed, the dielectric layer 200 located on the third area 103 is not removed, and all the first surrounding patterns 160 located on the first area 101 are removed, thereby forming the following: Fig.13 The first groove 211 located on the second region 102 and the plurality of second grooves 212 located on the first region 101 and aligned with the word line structures 120 thereunder are shown. In one embodiment, the bottom surfaces of the first groove 211 and the second groove 212 can be located at different horizontal heights by controlling the process parameters of the etching process of step S107, that is, there is a height difference H between the bottom surfaces of the first groove 211 and the second groove 212 along the third direction D3, and H>0; illustratively, the first groove 211 located on the second area 102 can be deeply inserted into the wider trench isolation 110 located in the substrate 100 of the second area 102, and the second groove 212 located on the first area 101 can be deeply inserted into the corresponding word line structure 120 located in the trench isolation 110 of the first area 101; wherein the bottom surface of the second groove 212 located in the first area 101 can be higher than the bottom surface of the first groove 211 located in the second area 102, and the bottom surface of the second groove 212 located in the first area 101 can also be higher than the bottom surface of the insulating cap layer 124 of the corresponding word line structure 120 (combined with Figure 3 shown).

[0063] Please refer to Figures 14 to 16 As shown, Fig.14 is a partial top view schematic diagram of a semiconductor structure in one embodiment of the present invention, Fig.15 for Fig.14 The schematic cross-sectional view of the semiconductor structure shown is taken along the AA cut line. Fig.16 for Fig.14The semiconductor structure is shown as a cross-sectional schematic diagram along the BB cut line and the CC cut line, respectively. Execute the above step S108: fill the first groove 211 located on the second area 102 and the plurality of second grooves 212 located on the first area 101 with an insulating layer 500 (material is, for example, nitride) by a deposition process, so as to form a plurality of first insulating structures 501 in the shape of an annular frame aligned with the word line structure 120 on the first area 101 and a second insulating structure 502 on the second area 102. In one embodiment, the first insulating structure 501 located on the word line structure 120 in the first area 101 may include an annular frame pattern, which specifically includes a long axis 501a extending in the second direction D2 and a short axis 501b extending in the first direction D1; the second insulating structure 502 located on the substrate 100 in the second area 102 may include a large rectangular pattern, which may include a long side 502a extending in the second direction D2 and a short side 502b extending in the first direction D1; wherein the length of the short side 502b is greater than the length of the short axis 501b, and the length of the long side 502a is greater than the length of the long axis 501a; and in the third direction D3, the bottom surface of the second insulating structure 502 may be lower than the bottom surface of the first insulating structure 501, but is not limited to this. Under this configuration, the insulating layer 500 filled in each of the second grooves 212 located on the first region 101 in the embodiment of the present invention is in direct contact with the insulating capping layer 124 of the corresponding word line structure 120 .

[0064] In summary, the method for preparing a semiconductor structure provided by the present invention includes forming a barrier layer located on the dielectric layer and the hard mask layer, the barrier layer having an opening exposing the second surrounding pattern of the second zone, using the barrier layer as a mask to remove the second surrounding pattern corresponding to the opening, using the remaining hard mask layer as a mask to remove part of the dielectric layer and the first surrounding pattern to form a groove of the substrate exposing the first zone and the second zone, and forming an insulating layer to fill the groove. That is, the present invention is to adjust the shapes of the gaps of the insulating structures to be formed on the first zone and the second zone to be different by additionally depositing a barrier layer with an opening and removing all the second surrounding patterns on the second zone based on the barrier layer, and to increase the gaps on the second zone for forming the insulating structure, thereby realizing the formation of insulating structures of different shapes in the first zone and the second zone, and setting the insulating structure in the second zone to a second insulating structure with a large rectangular pattern and covering the entire second zone substrate, thereby achieving different isolation effects and avoiding the purpose of peeling of part of the insulating structure.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region, a second region, and a third region; forming a first surrounding pattern, wherein the first surrounding pattern includes a plurality of strip patterns, the strip patterns extending in a first direction and spanning across the substrates of the first region and the second region, and the plurality of strip patterns including a connected end portion, the connected end portion also extending in the first direction to the substrate of the third region; forming a dielectric layer, wherein the dielectric layer is located on the substrate and fills the gaps between adjacent first surrounding patterns; forming a hard mask layer, the hard mask layer comprising a plurality of second surrounding patterns, the second surrounding patterns being located on the dielectric layer in the first region and the second region and being staggered with the first surrounding patterns, the second surrounding patterns comprising a long axis extending in a second direction perpendicular to the first direction and a short axis extending in the first direction; forming a barrier layer on the dielectric layer and the hard mask layer, wherein the barrier layer has an opening exposing the second surrounding pattern of the second region; Using the barrier layer as a mask, removing the second surrounding pattern corresponding to the opening; Using the remaining hard mask layer as a mask, removing a portion of the dielectric layer and the first surrounding pattern to form a groove of the substrate exposing the first area and the second area; An insulating layer is formed to fill the groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first surrounding pattern includes: a plurality of bit line patterns and a spacer pattern surrounding the bit line patterns, and the bit line pattern includes the connected end portions.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The end portion includes an insulating material.

4. The method for preparing a semiconductor structure according to claim 2, wherein: The spacer pattern is in a ring frame shape.

5. The method for preparing a semiconductor structure according to claim 2, wherein: Before forming the first surrounding pattern, the method further includes: A plurality of word line structures are formed, the plurality of word line structures are disposed in the substrate of the first region in a spaced-apart manner and are interlaced with the plurality of bit line patterns.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The word line structure further includes an insulating capping layer, and the insulating layer filled in the groove contacts the insulating capping layer.

7. The method for preparing a semiconductor structure according to claim 1, wherein: A bottom surface of the groove located in the first region is higher than a bottom surface of the groove located in the second region.

8. The method for preparing a semiconductor structure according to claim 2, wherein: Top surfaces of the spacer pattern in the first region and in the second region are at different levels.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: A top surface of the spacer pattern located in the first region is higher than a top surface of the spacer pattern located in the second region.

10. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A plurality of word line structures extending along a second direction and spaced apart from each other in a first direction perpendicular to the second direction are disposed in the substrate of the first region; a plurality of bit line patterns extending along the first direction and arranged on the word line structure spaced apart from each other in the second direction; A plurality of first insulating structures, located on the word line structure in the first region, the first insulating structure comprising a ring-shaped frame pattern, and the first insulating structure further comprising a long axis extending in the second direction and a short axis extending in the first direction; A second insulating structure is located on the substrate of the second zone, the second insulating structure includes a large rectangular pattern, and the second insulating structure also includes a long side extending in the second direction and a short side extending in the first direction, wherein the length of the short side is greater than the length of the short axis.

11. The semiconductor structure according to claim 10, characterized in that The length of the long side is greater than the length of the long axis.

12. The semiconductor structure according to claim 10, wherein: In a third direction perpendicular to the substrate, a bottom surface of the second insulating structure is lower than a bottom surface of the first insulating structure.

13. The semiconductor structure according to claim 10, wherein: The word line structure includes an insulating capping layer, and the first insulating structure directly contacts the insulating capping layer.

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