Single-gate multi-programming non-volatile memory structure, array and operation method

Abstract

The present invention provides a single-gate multi-programming non-volatile memory structure, an array and an operation method. The memory structure includes: a substrate, a deep well region formed on the substrate, a first P well, an N well and a second P well formed in the deep well region at intervals, a first N-type region and a first P-type region formed in the first P well at intervals, second, third, fourth P-type regions and a second N-type region formed in the N well at intervals, a third N-type region and a fifth P-type region formed in the second P well at intervals, a first electrode formed on the first P well and bridging the first N-type region and the first P-type region, a second electrode formed on the N well and bridging the second P-type region and the third P-type region, a third electrode formed on the N well and bridging the third P-type region and the fourth P-type region, a fourth electrode formed on the second P well and bridging the third N-type region and the fifth P-type region, and the first, second and fourth electrodes form a floating gate. By means of the present invention, the problems of large area and high power consumption existing in traditional memories are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory, and in particular relates to a single-gate multi-programmable non-volatile storage structure, an array and an operation method. Background Art

[0002] Single-gate multiple-time programmable non-volatile memory (MTP) is widely used in integrated circuit design because it is compatible with CMOS technology and can achieve non-volatile storage without adding additional masks.

[0003] The programming of traditional single-gate multi-erasable non-volatile memory is mainly based on saturated hot carrier injection. This programming method requires the application of a bias voltage generated by a charge pump and a milliampere-level drive current between the source and drain. The large drive current leads to a large charge pump area. Since the area of ​​small-capacity memory is mainly limited by the peripheral charge pump, the memory has a large area in small-capacity applications and is not economical. Moreover, since programming requires the generation of saturated hot carriers, the power consumption is relatively high (greater than 1 mA), which is not suitable for low-power application scenarios.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a single-gate multiple-programmable non-volatile storage structure, array and operation method to solve the problems of large area and high power consumption of traditional single-gate multiple-erasable non-volatile memory.

[0006] To achieve the above objectives and other related objectives, the present invention provides a single-gate multi-programmable non-volatile storage structure, comprising:

[0007] A substrate, a deep well region formed on the substrate, a first P-well, an N-well and a second P-well formed in the deep well region, a first N-type region and a first P-type region formed in the first P-well, a second P-type region, a third P-type region, a fourth P-type region and a second N-type region formed in the N-well, a third N-type region and a fifth P-type region formed in the second P-well, a first electrode formed on the first P-well and bridging the first N-type region and the first P-type region, a second electrode formed on the N-well and bridging the second P-type region and the third P-type region, a third electrode formed on the N-well and bridging the third P-type region and the fourth P-type region, and a fourth electrode formed on the second P-well and bridging the third N-type region and the fifth P-type region;

[0008] The first electrode, the first N-type region, the first P-type region and the first P-well constitute a tunneling tube, the second electrode, the second P-type region, the third P-type region and the N-well constitute a floating gate tube, the third electrode, the third P-type region, the fourth P-type region and the N-well constitute a gate tube, and the fourth electrode, the third N-type region, the fifth P-type region and the second P-well constitute a control tube; the first electrode, the second electrode and the fourth electrode form a floating gate, the first N-type region and the first P-type region are short-circuited and a tunneling gate terminal is led out through a first metal wire, the second P-type region leads to a source line terminal through a second metal wire, the third electrode leads to a word line terminal through a third metal wire, the fourth P-type region leads to a bit line terminal through a fourth metal wire, the second N-type region leads to a substrate terminal through a fifth metal wire, the third N-type region and the fifth P-type region are short-circuited and a control gate terminal is led out through a sixth metal wire; wherein the tunneling tube and the control tube are N-type capacitors, and the floating gate tube and the gate tube are PMOS tubes.

[0009] Optionally, the first P-well, the N-well and the second P-well are arranged in sequence along the first direction and are arranged in parallel with each other.

[0010] Optionally, the first P-well has a first width in the first direction, the N-well has a second width in the first direction, and the second P-well has a third width in the first direction, wherein the first width is less than or equal to the second width, and the second width is less than the third width.

[0011] Optionally, the first electrode, the second electrode and the fourth electrode are made of the same polysilicon, there is a first overlapping area between the polysilicon and the first P-well, there is a second overlapping area between the polysilicon and the N-well, there is a third overlapping area between the polysilicon and the second P-well, wherein the first overlapping area is less than or equal to the second overlapping area, and the second overlapping area is less than the third overlapping area.

[0012] Optionally, the polysilicon overlapping with the first P-well has a fourth width in the second direction, the polysilicon overlapping with the N-well has a fifth width in the second direction, and the polysilicon overlapping with the second P-well has a sixth width in the second direction, wherein the fourth width is less than or equal to the fifth width, and the fifth width is less than the sixth width.

[0013] Optionally, the polysilicon is L-shaped, and the L-shaped polysilicon includes a longitudinal portion and a transverse portion, the longitudinal portion spanning the first P-well, the N-well and the second P-well along a first direction, and the transverse portion extending along a second direction with the longitudinal portion on the second P-well as a starting point; wherein the width of the longitudinal portion in the second direction is set to be equal, or, at least, is set to decrease in sequence from the N-well to the first P-well or is set to decrease in a step-like manner.

[0014] Optionally, the single-gate multi-programmed non-volatile storage structure also includes at least one of a first isolation portion, a second isolation portion and a third isolation portion, wherein the first isolation portion is formed between the first P-well and the N-well, the second isolation portion is formed between the fourth P-type region and the second N-type region in the N-well, and the third isolation portion is formed between the N-well and the second P-well.

[0015] The present invention also provides a single-gate multi-programmable non-volatile storage array, comprising:

[0016] At least one storage block, the storage block comprising a first storage unit, a second storage unit, a third storage unit and a fourth storage unit, wherein each storage unit is implemented by a single-gate multi-programmable non-volatile storage structure according to any one of claims 1 to 7;

[0017] The first storage unit and the third storage unit, and the second storage unit and the fourth storage unit are all arranged in a central symmetric manner in the first direction, and the first storage unit and the second storage unit, and the third storage unit and the fourth storage unit are all arranged in an axisymmetric manner in the second direction; wherein the first storage unit and the third storage unit share the first P well, the second storage unit and the fourth storage unit share the first P well, the first storage unit and the second storage unit share the N well and the second P well, and the third storage unit and the fourth storage unit share the N well and the second P well;

[0018] Among them, the first memory cell and the third memory cell share the same tunneling gate terminal and are connected to the first tunneling gate line, the second memory cell and the fourth memory cell share the same tunneling gate terminal and are connected to the second tunneling gate line, the first memory cell and the second memory cell share the same control gate terminal and are connected to the first control gate line, the third memory cell and the fourth memory cell share the same control gate terminal and are connected to the second control gate line, the source line terminal and the bit line terminal of the first memory cell and the third memory cell are respectively connected to the first source line and the first bit line, the source line terminal and the bit line terminal of the second memory cell and the fourth memory cell are respectively connected to the second source line and the second bit line, the word line terminal of the first memory cell and the second memory cell is connected to the first word line, the word line terminal of the third memory cell and the fourth memory cell is connected to the second word line, and the first memory cell, the second memory cell, the third memory cell and the fourth memory cell share the same substrate terminal and are connected to the substrate line.

[0019] Optionally, the outer contours of the two L-shaped polysilicon in the first storage unit and the third storage unit that are centrally symmetrical are rectangular, and the outer contours of the two L-shaped polysilicon in the second storage unit and the fourth storage unit that are centrally symmetrical are rectangular.

[0020] The present invention also provides an operating method of the single-gate multi-programmable non-volatile storage structure as described in any one of the above, comprising:

[0021] Applying a negative voltage to the control gate terminal and the tunnel gate terminal, applying a first positive voltage to the source line terminal and the substrate terminal, and performing an erasing operation on the single-gate multiple-programming non-volatile storage structure;

[0022] Applying a negative voltage to the tunneling gate terminal, applying a first positive voltage to the control gate terminal, the source line terminal and the substrate terminal, and performing a programming operation on the single-gate multiple-programming non-volatile memory structure;

[0023] Applying a second positive voltage to the source line terminal and the substrate terminal, applying a ground voltage to the control gate terminal, the tunnel gate terminal and the word line terminal, and performing a read operation on the single-gate multiple-programmable non-volatile storage structure;

[0024] Wherein, a voltage value of the first positive voltage is greater than a voltage value of the second positive voltage.

[0025] Optionally, during an erase operation, a first positive voltage is also applied to the word line end and the bit line end of the single-gate multiple-programming non-volatile storage structure; during a programming operation, a first positive voltage is also applied to the word line end and the bit line end of the single-gate multiple-programming non-volatile storage structure; during a read operation, a ground voltage is also applied to the bit line end of the single-gate multiple-programming non-volatile storage structure.

[0026] Optionally, the voltage value of the first positive voltage is between 6V and 9V, the voltage value of the negative voltage is between -9V and -6V, and the voltage value of the second positive voltage is between 1.5V and 3V.

[0027] As described above, the single-gate multi-programmable non-volatile storage structure, array and operation method of the present invention propose a 2T2C storage structure and implement programming and erasing based on the tunneling effect, which does not require a large driving current, is beneficial to reducing power consumption and area, and is suitable for applications with low power consumption and small capacity storage requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of the storage structure in Embodiment 1 of the present invention.

[0029] Figure 2 Display as Figure 1 A top view of the storage structure shown.

[0030] Figure 3 Display as Figure 1 Schematic diagram of voltages applied to each end of the storage structure during an erase operation.

[0031] Figure 4 Display as Figure 1 Schematic diagram of voltages applied to each terminal of the storage structure during programming operation.

[0032] Figure 5 Display as Figure 1 Schematic diagram of voltage applied to each end of the storage structure during a read operation.

[0033] Figure 6 Shown is a schematic diagram of a storage array in Embodiment 2 of the present invention.

[0034] Figure 7 Display as Figure 6 Equivalent circuit diagram of the memory array shown.

[0035] Figure 8 It is a schematic diagram showing voltages applied to respective terminals of respective memory cells when an erase operation is performed on the first memory cell in a memory block.

[0036] Fig. 9 It is a schematic diagram showing voltages applied to respective terminals of respective memory cells when a programming operation is performed on the first memory cell in a memory block.

[0037] Fig.10 It is a schematic diagram showing voltages applied to respective terminals of respective memory cells when a read operation is performed on the first memory cell in the memory block.

[0038] Explanation of component numbers: 10 storage block, 11 first storage cell, 12 second storage cell, 13 third storage cell, 14 fourth storage cell, 100 single-gate multiple-programmable non-volatile storage structure, 101 substrate, 102 deep well region, 103 first P-well, 104 N-well, 105 second P-well, 106 first N-type region, 107 second N-type region, 108 third N-type region, 109 first P-type region, 110 second P-type region, 111 third P-type region, 112 fourth P-type region, 113 fifth P-type region, 114 first electrode, 115 second electrode, 116 third electrode, 117 fourth electrode, 118 first isolation portion, 119 second isolation portion, 120 third isolation portion. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated. Embodiment 1

[0041] like Figure 1 and Figure 2 As shown, the present embodiment provides a single-gate multi-programmable non-volatile memory structure 100, including a substrate 101, a deep well region 102, a first P-well 103, an N-well 104, a second P-well 105, a first N-type region 106, a second N-type region 107, a third N-type region 108, a first P-type region 109, a second P-type region 110, a third P-type region 111, a fourth P-type region 112, a fifth P-type region 113, a first electrode 114, a second electrode 115, a third electrode 116 and a fourth electrode 117.

[0042] The substrate 101 is used as a semiconductor base of the single-gate multi-programmable non-volatile memory structure 100. Figure 1 As shown; in one example, the substrate 101 includes a P-type silicon substrate.

[0043] A deep well region 102 is formed on the substrate 101 to isolate the substrate 101 from the devices above. Figure 1 As shown; in one example, the deep well region 102 is a deep N well.

[0044] The first P well 103, the N well 104 and the second P well 105 are formed in the deep well region 102 at intervals, and serve as the active region for device fabrication. Figure 1 In one example, the first P well 103, the N well 104 and the second P well 105 are sequentially arranged in a spaced manner along the first direction and the wells are arranged in parallel. Figure 2 As shown; wherein, the first P well 103 has a first width W1 in the first direction, the N well 104 has a second width W2 in the first direction, and the second P well 105 has a third width W3 in the first direction, the first width W1 is less than or equal to the second width W2, and the second width W2 is less than the third width W3, that is, W1≤W2<W3, to facilitate the design of subsequent capacitors.

[0045] The first N-type region 106 and the first P-type region 109 are formed in the first P-well 103 at intervals. The first electrode 114 is formed on the first P-well 103 and bridges the first N-type region 106 and the first P-type region 109. Figure 1 As shown; at this time, the first electrode 114, the first N-type region 106, the first P-type region 109 and the first P-well 103 constitute a tunneling tube, wherein the tunneling tube is an N-type capacitor. Specifically, for the N-type capacitor, the first electrode 114 can be regarded as the first plate of the N-type capacitor, and the first P-well 103 and the first P-type region can be regarded as the second plate of the N-type capacitor.

[0046] The second P-type region 110, the third P-type region 111, the fourth P-type region 112 and the second N-type region 107 are formed in the N-well 104 at intervals. The second electrode 115 is formed on the N-well 104 and bridges the second P-type region 110 and the third P-type region 111. The third electrode 116 is formed on the N-well 104 and bridges the third P-type region 111 and the fourth P-type region 112. Figure 1 As shown; at this time:

[0047] The second electrode 115, the second P-type region 110, the third P-type region 111 and the N-well 104 constitute a floating gate transistor. Of course, it can also be said that the second electrode 115, the second P-type region 110, the third P-type region 111, the second N-type region 107 and the N-well 104 constitute a floating gate transistor, wherein the floating gate transistor is a PMOS transistor. Specifically, for the PMOS transistor, the second electrode 115 can be regarded as the gate terminal of the PMOS transistor, the second P-type region 110 can be regarded as the source terminal of the PMOS transistor, the third P-type region 111 can be regarded as the drain terminal of the PMOS transistor, and the second N-type region 107 can be regarded as the substrate terminal of the PMOS transistor.

[0048] The third electrode 116, the third P-type region 111, the fourth P-type region 112 and the N-well 104 constitute a gate transistor. Of course, it can also be said that the third electrode 116, the third P-type region 111, the fourth P-type region 112, the second N-type region 107 and the N-well 104 constitute a gate transistor, wherein the gate transistor is a PMOS transistor. Specifically, for the PMOS transistor, the third electrode 116 can be regarded as the gate terminal of the PMOS transistor, the third P-type region 111 can be regarded as the source terminal of the PMOS transistor, the fourth P-type region 112 can be regarded as the drain terminal of the PMOS transistor, and the second N-type region 107 can be regarded as the substrate terminal of the PMOS transistor.

[0049] The third N-type region 108 and the fifth P-type region 113 are formed in the second P-well 105 at intervals. The fourth electrode 117 is formed on the second P-well 105 and bridges the third N-type region 108 and the fifth P-type region 113. Figure 1 As shown; at this time, the fourth electrode 117, the third N-type region 108, the fifth P-type region 113 and the second P-well 105 constitute a control tube, wherein the control tube is an N-type capacitor. Specifically, for the N-type capacitor, the fourth electrode 117 can be regarded as the first plate of the N-type capacitor, and the second P-well 105 and the fifth P-type region 113 can be regarded as the second plate of the N-type capacitor.

[0050] The first electrode 114, the second electrode 115 and the fourth electrode 117 form a floating gate, which is marked as FG. In one example, the first electrode 114, the second electrode 115 and the fourth electrode 117 are made of the same polysilicon. Figure 2 As shown. Specifically, there is a first overlapping area Stg between the polysilicon and the first P well 103, a second overlapping area Sfg between the polysilicon and the N well 104, and a third overlapping area Scg between the polysilicon and the second P well 105. The first overlapping area Stg is less than or equal to the second overlapping area Sfg, and the second overlapping area Sfg is less than the third overlapping area Scg, that is, Stg≤Sfg<Scg; the capacitance corresponding to the first overlapping area Stg is recorded as Ctg, the capacitance corresponding to the second overlapping area Sfg is recorded as Cfg, and the capacitance corresponding to the third overlapping area Scg is recorded as Ccg, and the capacitance values ​​of each capacitor satisfy the relationship Ctg≤Cfg<Ccg. By designing the capacitance values ​​of the corresponding capacitors, it is beneficial to couple the voltages required for operations such as erasing and programming through the corresponding capacitors and apply them to the corresponding positions, thereby improving the efficiency of operations such as erasing and programming.

[0051] In practical applications, since the widths of the first P-well 103, the N-well 104 and the second P-well 105 in the first direction satisfy W1≤W2<W3, the overlapping parts of the polysilicon and each well can be designed to be of equal width in the second direction. For example, the polysilicon is rectangular and spans the first P-well 103, the N-well 104 and the second P-well 105 along the first direction. At this time, the overlapping area of ​​the polysilicon and the first P-well 103, the N-well 104 and the second P-well 105 satisfies Stg≤Sfg<Scg. Of course, the overlapping parts of the polysilicon and each well can also be designed to have unequal widths in the second direction. For example, the polysilicon overlapping the first P-well 103 has a fourth width W4 in the second direction, the polysilicon overlapping the N-well 104 has a fifth width W5 in the second direction, and the polysilicon overlapping the second P-well 105 has a sixth width W6 in the second direction. The fourth width W4 is less than or equal to the fifth width W5, and the fifth width W5 is less than the sixth width W6, that is, W4≤W5<W6; in one example, the polysilicon is designed to be L-shaped, and the L-shaped polysilicon includes a longitudinal portion and a transverse portion, the longitudinal portion spanning the first P-well 103, the N-well 104 and the second P-well 105 along the first direction, and the transverse portion extends along the second direction with the longitudinal portion on the second P-well 105 as the starting point, such as Figure 2 As shown, at this time, if the width of the longitudinal portion in the second direction is set to be equal, then the overlapping area of ​​the polysilicon and each well satisfies Stg=Sfg<Scg; if the width of the longitudinal portion in the second direction is set to decrease successively or in a step-like manner from at least the N-well 104 to the first P-well 103, then the overlapping area of ​​the polysilicon and each well satisfies Stg<Sfg<Scg.

[0052] Among them, the first N-type region 106 and the first P-type region 109 are short-circuited and lead to the tunnel gate terminal through the first metal line, marked as TG; the second P-type region 110 leads to the source line terminal through the second metal line, marked as SL; the third electrode 116 leads to the word line terminal through the third metal line, marked as WL; the fourth P-type region 112 leads to the bit line terminal through the fourth metal line, marked as BL; the second N-type region 107 leads to the substrate terminal through the fifth metal line, marked as NW; the third N-type region 108 and the fifth P-type region 113 are short-circuited and lead to the control gate terminal through the sixth metal line, marked as CG. In practical applications, each metal line is implemented by the same or different metal layers, and there is no limitation on this.

[0053] Furthermore, the single-gate multiple-programming non-volatile memory structure 100 further includes at least one of a first isolation portion 118, a second isolation portion 119, and a third isolation portion 220; in this embodiment, the single-gate multiple-programming non-volatile memory structure 100 includes the first isolation portion 118, the second isolation portion 119, and the third isolation portion 220. Among them, the first isolation portion 118 is formed between the first P-well 103 and the N-well 104, the second isolation portion 119 is formed between the fourth P-type region 112 and the second N-type region 107 in the N-well 104, and the third isolation portion 120 is formed between the N-well 104 and the second P-well 105. In one example, each isolation portion is implemented by field oxide or shallow trench isolation.

[0054] Accordingly, this embodiment also provides an operation method of the single-gate multiple-programming non-volatile storage structure 100, including methods of erasing operation, programming operation and reading operation, such as Figure 3~Figure 5 shown.

[0055] For the erase operation:

[0056] A negative voltage VBB is applied to the control gate terminal CG and the tunnel gate terminal TG, a first positive voltage VPP is applied to the source line terminal SL and the substrate terminal NW, and further, a first positive voltage VPP is applied to the word line terminal WL and the bit line terminal BL to perform an erase operation on the single-gate multiple-programmable non-volatile memory structure 100, such as Figure 3 In practical applications, specific values ​​are selected as the negative voltage VBB and the first positive voltage VPP in combination with specific requirements; in one example, the voltage value of the negative voltage VBB is between -9V and -6V (including the two endpoint values), and the voltage value of the first positive voltage VPP is between 6V and 9V (including the two endpoint values).

[0057] By applying a negative voltage VBB to the control gate terminal CG and the tunnel gate terminal TG and applying a first positive voltage VPP to the source line terminal SL and the substrate terminal NW, due to Ccg>Cfg≥Ctg, based on the coupling effect of capacitance, the floating gate FG across the first P well 103, the N well 104 and the second P well 105 is coupled and controlled, and the floating gate FG and the tunnel gate terminal TG are at the same potential. This voltage drop is mainly applied to the floating gate FG region, and the erase voltage = (VPP-VBB)*(Ccg+Ctg) / (Ccg+Cfg+Ctg); generally after a few ms, the electrons in the floating gate FG are removed from the floating gate FG due to the tunneling (Fowler-Nordheim tunneling) effect under the reverse voltage bias condition and enter the N well 104 and the third P-type region 111, so that the storage structure is erased.

[0058] For programming operation: a negative voltage VBB is applied to the tunnel gate terminal TG, a first positive voltage VPP is applied to the control gate terminal CG, the source line terminal SL and the substrate terminal NW, and further, a first positive voltage VPP is applied to the word line terminal WL and the bit line terminal BL, so as to perform programming operation on the single-gate multiple programming non-volatile memory structure 100, such as Figure 4 shown.

[0059] By applying a negative voltage VBB to the tunneling gate terminal TG and applying a first positive voltage VPP to the control gate terminal CG, the source line terminal SL and the substrate terminal NW, due to Ccg>Cfg≥Ctg, based on the coupling effect of capacitance, the floating gate FG across the first P well 103, the N well 104 and the second P well 105 is coupled and controlled, and the floating gate FG and the control gate terminal CG have the same potential. This voltage drop is mainly applied to the tunneling gate terminal TG region, and the programming voltage = (VPP-VBB)*(Ccg+Cfg) / (Ccg+Cfg+Ctg); generally after a few ms, electrons are injected into the floating gate FG due to the tunneling (Fowler-Nordheim tunneling) effect under the forward voltage bias condition, that is, electrons enter the floating gate FG from the tunneling gate terminal TG, so that the storage structure is programmed.

[0060] For the read operation: a second positive voltage VLDO is applied to the source line terminal SL and the substrate terminal NW, a ground voltage GND is applied to the control gate terminal CG, the tunnel gate terminal TG and the word line terminal WL, and further, a ground voltage GND is applied to the bit line terminal BL to perform a read operation on the single-gate multiple-programmable non-volatile memory structure 100, such as Figure 5 As shown; wherein, the voltage value of the second positive voltage VLDO is less than the voltage value of the first positive voltage VPP. In practical applications, a specific value is selected as the second positive voltage VLDO in combination with specific requirements; in one example, the voltage value of the second positive voltage VLDO is between 1.5V and 3V (including the two endpoint values), for example, 2V.

[0061] The programmed floating gate will turn on the floating gate tube, while the erased floating gate will turn off the floating gate tube. When performing a read operation, a second positive voltage VLDO is applied to the source line terminal SL and the substrate terminal NW, and a ground voltage GND is applied to the control gate terminal CG, the tunnel gate terminal TG, and the word line terminal WL. If the storage structure is programmed, current can be read at the bit line terminal BL. If the storage structure is erased, current cannot be read at the bit line terminal BL. In this way, data reading is achieved. Embodiment 2

[0062] like Figure 6 As shown, this embodiment provides a single-gate multi-time programmable non-volatile memory array, including at least one memory block 10; in practical applications, the number of memory blocks 10 should be designed in combination with specific requirements, and there is no limitation on this.

[0063] In one example, the storage block 10 includes a first storage unit 11, a second storage unit 12, a third storage unit 13 and a fourth storage unit 14, wherein each storage unit is implemented using the storage structure described in Example 1; of course, in other examples, the storage block 10 may also include other numbers of storage units, for example, one, two, three, five storage units, etc., which has no effect on the functional implementation; however, the structural design of this example can make the storage array more compact, which is conducive to minimizing the area.

[0064] Specifically, the first storage unit 11 and the third storage unit 13 are arranged centrally and symmetrically in the first direction, the second storage unit 12 and the fourth storage unit 14 are arranged centrally and symmetrically in the first direction, and the first storage unit 11 and the second storage unit 12 are arranged axisymmetrically in the second direction, and the third storage unit 13 and the fourth storage unit 14 are arranged axisymmetrically in the second direction; wherein the first storage unit 11 and the third storage unit 13 share the first P well 103, the second storage unit 12 and the fourth storage unit 14 share the first P well 103, the first storage unit 11 and the second storage unit 12 share the N well 104 and the second P well 105, and the third storage unit 13 and the fourth storage unit 14 share the N well 104 and the second P well 105. For the case where the first electrode 114, the second electrode 115 and the fourth electrode 117 in each storage unit are made of the same polycrystalline silicon and the polycrystalline silicon is L-shaped, the outer contours of the two L-shaped polycrystalline silicon located in the first direction are rectangular, that is, the outer contours of the two centrally symmetrical L-shaped polycrystalline silicon in the first storage unit 11 and the third storage unit 13 are rectangular, and the outer contours of the two centrally symmetrical L-shaped polycrystalline silicon in the second storage unit 12 and the fourth storage unit 14 are rectangular, so as to make the array structure as compact as possible.

[0065] Among them, the first storage unit 11 and the third storage unit 13 share the same tunneling gate terminal TG and are connected to the first tunneling gate line TG0, the second storage unit 12 and the fourth storage unit 14 share the same tunneling gate terminal TG and are connected to the second tunneling gate line TG1, the source line terminals SL of the first storage unit 11 and the third storage unit 13 are both connected to the first source line SL0, the source line terminals SL of the second storage unit 12 and the fourth storage unit 14 are both connected to the second source line SL1, the bit line terminals BL of the first storage unit 11 and the third storage unit 13 are both connected to the first bit line BL0, and the bit line terminals BL of the second storage unit 12 and the fourth storage unit 14 are connected to the second bit line BL0. The first storage unit 11 and the second storage unit 12 share the same control gate terminal CG and are connected to the first control gate line CG0, the third storage unit 13 and the fourth storage unit 14 share the same control gate terminal CG and are connected to the second control gate line CG1, the word line terminals WL of the first storage unit 11 and the second storage unit 12 are both connected to the first word line WL0, the word line terminals WL of the third storage unit 13 and the fourth storage unit 14 are both connected to the second word line WL1, the first storage unit 11, the second storage unit 12, the third storage unit 13 and the fourth storage unit 14 share the same substrate terminal NW and are connected to the substrate line (not shown in the figure).

[0066] The equivalent circuit of the storage array of this embodiment is as follows: Figure 7 As shown, each storage unit in the storage block 10 is composed of two PMOS tubes and two N-type capacitors, forming a 2T2C structure. When performing an erase operation, a program operation, and a read operation on any storage unit in the storage block 10, for example, the first storage unit 11, based on the operation method described in the first embodiment, the voltage applied to each end of each storage unit is as follows: Figure 8~Figure 10 As shown. Among them:

[0067] During the erasing operation, a negative voltage VBB is applied to the tunneling gate terminals of the first storage unit 11 and the third storage unit 13 based on the first tunneling gate line TG0, a negative voltage VBB is applied to the tunneling gate terminals of the second storage unit 12 and the fourth storage unit based on the second tunneling gate line TG1, a negative voltage VBB is applied to the control gate terminals of the first storage unit 11 and the second storage unit based on the first control gate line CG0, a ground voltage GND is applied to the control gate terminals of the third storage unit 13 and the fourth storage unit 14 based on the second control gate line CG1, a first positive voltage VPP is applied to the source line terminals of the first storage unit 11 and the third storage unit 13 based on the first source line SL0, and a positive voltage VPP is applied to the control gate terminals of the second storage unit 12 and the fourth storage unit based on the second source line SL1. A first positive voltage VPP is applied to the source line terminal of the first memory cell 14, a first positive voltage VPP is applied to the bit line terminals of the first memory cell 11 and the third memory cell 13 based on the first bit line BL0, a first positive voltage VPP is applied to the bit line terminals of the second memory cell 12 and the fourth memory cell 14 based on the second bit line BL1, a first positive voltage VPP is applied to the substrate terminals of the first memory cell 11, the second memory cell 12, the third memory cell 13 and the fourth memory cell 14 based on the substrate line, a first positive voltage VPP is applied to the word line terminals of the first memory cell 11 and the second memory cell 12 based on the first word line WL0, and a first positive voltage VPP is applied to the word line terminals of the third memory cell 13 and the fourth memory cell 14 based on the second word line WL1, as shown in FIG. Figure 8 Thus, the erasing operation of the first storage unit 11 in the storage block 10 is realized. Since the first storage unit 11 and the second storage unit 12 are connected to the same control gate line, the second storage unit 12 is erased together.

[0068] During the programming operation, a negative voltage VBB is applied to the tunneling gate terminals of the first storage unit 11 and the third storage unit 13 based on the first tunneling gate line TG0, a ground voltage GND is applied to the tunneling gate terminals of the second storage unit 12 and the fourth storage unit based on the second tunneling gate line TG1, a first positive voltage VPP is applied to the control gate terminals of the first storage unit 11 and the second storage unit based on the first control gate line CG0, a ground voltage GND is applied to the control gate terminals of the third storage unit 13 and the fourth storage unit 14 based on the second control gate line CG1, a first positive voltage VPP is applied to the source line terminals of the first storage unit 11 and the third storage unit 13 based on the first source line SL0, and a positive voltage VPP is applied to the control gate terminals of the second storage unit 12 and the fourth storage unit based on the second source line SL1. A ground voltage GND is applied to the source line terminal of the storage unit 14, a first positive voltage VPP is applied to the bit line terminals of the first storage unit 11 and the third storage unit 13 based on the first bit line BL0, a ground voltage GND is applied to the bit line terminals of the second storage unit 12 and the fourth storage unit 14 based on the second bit line BL1, a first positive voltage VPP is applied to the substrate terminals of the first storage unit 11, the second storage unit 12, the third storage unit 13 and the fourth storage unit 14 based on the substrate line, a first positive voltage VPP is applied to the word line terminals of the first storage unit 11 and the second storage unit 12 based on the first word line WL0, and a first positive voltage VPP is applied to the word line terminals of the third storage unit 13 and the fourth storage unit 14 based on the second word line WL1, as shown in FIG. Fig. 9 As shown; in this way, the programming operation of the first storage unit 11 in the storage block 10 is implemented.

[0069] During the read operation, a ground voltage GND is applied to the tunnel gate terminals of the first storage unit 11 and the third storage unit 13 based on the first tunnel gate line TG0, a ground voltage GND is applied to the tunnel gate terminals of the second storage unit 12 and the fourth storage unit based on the second tunnel gate line TG1, a ground voltage GND is applied to the control gate terminals of the first storage unit 11 and the second storage unit based on the first control gate line CG0, a ground voltage GND is applied to the control gate terminals of the third storage unit 13 and the fourth storage unit 14 based on the second control gate line CG1, a second positive voltage VLDO is applied to the source line terminals of the first storage unit 11 and the third storage unit 13 based on the first source line SL0, and a positive voltage VLDO is applied to the control gate terminals of the second storage unit 12 and the fourth storage unit based on the second source line SL1. A ground voltage GND is applied to the source line terminal of the storage unit 14, a ground voltage GND is applied to the bit line terminals of the first storage unit 11 and the third storage unit 13 based on the first bit line BL0, a ground voltage GND is applied to the bit line terminals of the second storage unit 12 and the fourth storage unit 14 based on the second bit line BL1, a second positive voltage VLDO is applied to the substrate terminals of the first storage unit 11, the second storage unit 12, the third storage unit 13 and the fourth storage unit 14 based on the substrate line, a ground voltage GND is applied to the word line terminals of the first storage unit 11 and the second storage unit 12 based on the first word line WL0, and a second positive voltage VLDO is applied to the word line terminals of the third storage unit 13 and the fourth storage unit 14 based on the second word line WL1, as shown in FIG. Fig.10 As shown; in this way, the read operation on the first storage unit 11 in the storage block 10 is implemented.

[0070] In summary, the present invention provides a single-gate multi-programmable non-volatile storage structure, array and operation method, proposes a 2T2C storage structure and implements programming and erasing based on the tunneling effect, does not require a large driving current, is conducive to reducing power consumption and area, and is suitable for applications with low power consumption and small capacity storage requirements. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A single-gate multi-programmable non-volatile storage structure, characterized in that: include: A substrate, a deep well region formed on the substrate, a first P-well, an N-well and a second P-well formed in the deep well region, a first N-type region and a first P-type region formed in the first P-well, a second P-type region, a third P-type region, a fourth P-type region and a second N-type region formed in the N-well, a third N-type region and a fifth P-type region formed in the second P-well, a first electrode formed on the first P-well and bridging the first N-type region and the first P-type region, a second electrode formed on the N-well and bridging the second P-type region and the third P-type region, a third electrode formed on the N-well and bridging the third P-type region and the fourth P-type region, and a fourth electrode formed on the second P-well and bridging the third N-type region and the fifth P-type region; The first electrode, the first N-type region, the first P-type region and the first P-well constitute a tunneling tube, the second electrode, the second P-type region, the third P-type region and the N-well constitute a floating gate tube, the third electrode, the third P-type region, the fourth P-type region and the N-well constitute a gate tube, and the fourth electrode, the third N-type region, the fifth P-type region and the second P-well constitute a control tube; the first electrode, the second electrode and the fourth electrode form a floating gate, the first N-type region and the first P-type region are short-circuited and a tunneling gate terminal is led out through a first metal wire, the second P-type region leads to a source line terminal through a second metal wire, the third electrode leads to a word line terminal through a third metal wire, the fourth P-type region leads to a bit line terminal through a fourth metal wire, the second N-type region leads to a substrate terminal through a fifth metal wire, the third N-type region and the fifth P-type region are short-circuited and a control gate terminal is led out through a sixth metal wire; wherein the tunneling tube and the control tube are N-type capacitors, and the floating gate tube and the gate tube are PMOS tubes; The first electrode, the second electrode and the fourth electrode are made of the same polysilicon, there is a first overlapping area between the polysilicon and the first P-well, there is a second overlapping area between the polysilicon and the N-well, there is a third overlapping area between the polysilicon and the second P-well, wherein the first overlapping area is less than or equal to the second overlapping area, and the second overlapping area is less than the third overlapping area.

2. The single-gate multi-programmable non-volatile memory structure according to claim 1, characterized in that: The first P-well, the N-well and the second P-well are sequentially arranged at intervals along a first direction and the wells are arranged in parallel.

3. The single-gate multi-programmable non-volatile storage structure according to claim 2, characterized in that: The first P-well has a first width in the first direction, the N-well has a second width in the first direction, and the second P-well has a third width in the first direction, wherein the first width is less than or equal to the second width, and the second width is less than the third width.

4. The single-gate multi-time programming non-volatile memory structure according to claim 1, characterized in that: The polysilicon overlapping with the first P-well has a fourth width in the second direction, the polysilicon overlapping with the N-well has a fifth width in the second direction, and the polysilicon overlapping with the second P-well has a sixth width in the second direction, wherein the fourth width is less than or equal to the fifth width, and the fifth width is less than the sixth width.

5. The single-gate multi-programmable non-volatile memory structure according to claim 4, characterized in that: The polysilicon is L-shaped, and the L-shaped polysilicon includes a longitudinal portion and a transverse portion, wherein the longitudinal portion spans the first P-well, the N-well and the second P-well along a first direction, and the transverse portion extends along a second direction with the longitudinal portion on the second P-well as a starting point; wherein the width of the longitudinal portion in the second direction is set to be equal, or, at least, is set to decrease in sequence from the N-well to the first P-well or is set to decrease in a step-like manner.

6. The single-gate multi-programmable non-volatile memory structure according to claim 1, characterized in that: The single-gate multi-programmed non-volatile storage structure also includes at least one of a first isolation portion, a second isolation portion and a third isolation portion, wherein the first isolation portion is formed between the first P-well and the N-well, the second isolation portion is formed between the fourth P-type region and the second N-type region in the N-well, and the third isolation portion is formed between the N-well and the second P-well.

7. A single-gate multi-programmable non-volatile memory array, characterized in that: include: At least one storage block, the storage block includes a first storage unit, a second storage unit, a third storage unit and a fourth storage unit, wherein each storage unit is implemented by a single-gate multi-programmable non-volatile storage structure as claimed in any one of claims 1 to 6; the first storage unit and the third storage unit and the second storage unit and the fourth storage unit are all centrally symmetrically arranged in a first direction, and the first storage unit and the second storage unit and the third storage unit and the fourth storage unit are all axially symmetrically arranged in a second direction; wherein the first storage unit and the third storage unit share the first P well, the second storage unit and the fourth storage unit share the first P well, the first storage unit and the second storage unit share the N well and the second P well, and the third storage unit and the fourth storage unit share the N well and the second P well; Among them, the first memory cell and the third memory cell share the same tunneling gate terminal and are connected to the first tunneling gate line, the second memory cell and the fourth memory cell share the same tunneling gate terminal and are connected to the second tunneling gate line, the first memory cell and the second memory cell share the same control gate terminal and are connected to the first control gate line, the third memory cell and the fourth memory cell share the same control gate terminal and are connected to the second control gate line, the source line terminal and the bit line terminal of the first memory cell and the third memory cell are respectively connected to the first source line and the first bit line, the source line terminal and the bit line terminal of the second memory cell and the fourth memory cell are respectively connected to the second source line and the second bit line, the word line terminal of the first memory cell and the second memory cell is connected to the first word line, the word line terminal of the third memory cell and the fourth memory cell is connected to the second word line, and the first memory cell, the second memory cell, the third memory cell and the fourth memory cell share the same substrate terminal and are connected to the substrate line.

8. The single-gate multi-time programmable nonvolatile memory array according to claim 7, characterized in that: The outer contours of the two L-shaped polysilicon chips in the first storage unit and the third storage unit, which are centrally symmetrical, are rectangular, and the outer contours of the two L-shaped polysilicon chips in the second storage unit and the fourth storage unit, which are centrally symmetrical, are rectangular.

9. An operating method of the single-gate multi-programmable non-volatile storage structure according to any one of claims 1 to 6, characterized in that: include: Applying a negative voltage to the control gate terminal and the tunnel gate terminal, applying a first positive voltage to the source line terminal and the substrate terminal, and performing an erasing operation on the single-gate multiple-programming non-volatile storage structure; Applying a negative voltage to the tunneling gate terminal, applying a first positive voltage to the control gate terminal, the source line terminal and the substrate terminal, and performing a programming operation on the single-gate multiple-programming non-volatile memory structure; Applying a second positive voltage to the source line terminal and the substrate terminal, applying a ground voltage to the control gate terminal, the tunnel gate terminal and the word line terminal, and performing a read operation on the single-gate multiple-programmable non-volatile storage structure; Wherein, a voltage value of the first positive voltage is greater than a voltage value of the second positive voltage.

10. The method for operating the single-gate multi-time programming non-volatile memory structure according to claim 9, characterized in that: During the erase operation, a first positive voltage is also applied to the word line end and the bit line end of the single-gate multiple-programming non-volatile storage structure; during the programming operation, a first positive voltage is also applied to the word line end and the bit line end of the single-gate multiple-programming non-volatile storage structure; during the read operation, a ground voltage is also applied to the bit line end of the single-gate multiple-programming non-volatile storage structure.

11. The method for operating the single-gate multi-time programming non-volatile memory structure according to claim 9 or 10, characterized in that: The voltage value of the first positive voltage is between 6V and 9V, the voltage value of the negative voltage is between -9V and -6V, and the voltage value of the second positive voltage is between 1.5V and 3V.

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