Fabrication process for silicon carbide power devices with variable dopant concentration

Abstract

Embodiments of the present disclosure relate to fabrication processes for silicon carbide power devices with variable dopant concentrations. A manufacturing process for a vertical conduction power device includes growing an epitaxial layer from a layer of semiconductor material including a lattice structure having spatial symmetry, the epitaxial layer having a lattice structure having spatial symmetry and a first conductivity; forming a body region in the epitaxial layer, the body region having a second conductivity opposite to the first conductivity; and forming a current diffusion layer in the epitaxial layer between the body regions. Forming the body region includes performing a body channelized ion implantation using a body mask. Forming the current diffusion layer includes: forming a shallow damaged region in the body region through a body mask such that the lattice structure is changed in the shallow damaged region; and performing current diffusion channelization ion implantation using the shallow damaged region as an implantation mask.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Italian Patent Application No. 102023000016734, filed on August 4, 2023, entitled “PROCESSO DI FABBRICAZIONE PERDISPOSITIVIDIPOTENZA IN CARBURO DI SILICIO CON CONCENTRAZIONE DIDROGANTEVARIABILE”, which is hereby incorporated by reference to the maximum extent permitted by law. Technical Field

[0003] Example embodiments of the present disclosure relate to a fabrication process for a silicon carbide power device having a variable dopant concentration. Background Art

[0004] It is well known that semiconductor materials with a wide bandgap (e.g. greater than 1.1 eV), low on-state resistance, high thermal conductivity, high operating frequency and high charge carrier saturation velocity enable electronic devices (such as diodes and transistors) with performance higher than that of silicon, in particular for power applications (i.e. for operating voltages, e.g. comprised between 600 V and 1300 V, or under specific operating conditions such as high temperatures).

[0005] In detail, it is known to obtain such electronic devices starting from wafers of silicon carbide (SiC), one of its polytypes, such as 3C-SiC, 4H-SiC and 6H-SiC, which are distinguished by the characteristics listed above. The electronic power devices that can be obtained using semiconductors of the SiC type can be, for example, vertical conduction MOSFETs or JFETs.

[0006] Ion implantation is the current comprehensive technology for introducing dopants into silicon carbide. In fact, due to the low diffusivity of SiC compared to other semiconductor materials (such as silicon), dopant diffusion may not be a convenient technology to use. Epitaxial growth may not be an effective alternative, especially for locally confined doping.

[0007] It is well known that, in addition to the energy and ion type used, the crystal structure of SiC also affects the depth profile obtained during implantation. In fact, the so-called channelization can significantly increase the penetration depth of dopant ions in crystalline materials compared to amorphous targets. This phenomenon can occur if the direction of the incident ion beam is essentially parallel to the main crystal axes or planes within a well-defined and contained range (i.e., within the so-called "critical channelization angle"). In these directions, the energy loss per path length of the ions is reduced to a smaller extent, with the benefit that the ions can move deeper in the target. In fact, when implants are performed along the crystal axes using SiC technology, the distance that the deepest channelized ions can penetrate is many times the range expected for a corresponding random implant, given the same implant energy used.

[0008] In order to form locally confined implantation areas (both in terms of shape and in terms of doping profile), it is known to use a hard implantation mask, for example of silicon oxide (SiO2), configured to locally mask the SiC die or chip during implantation. However, the Applicant has found that the use of a hard mask may give rise to problems of planarity of the layer to which the mask is applied, after removal of the mask itself. In fact, the hard mask may induce lattice stresses on the SiC substrate.

[0009] Furthermore, the use of hard masks may be incompatible, i.e., may be difficult to scale, as the density of elementary cells that can be obtained in the same die increases progressively, leading to a reduction in the size of the elementary cells ("shrinkage" in the technical term), i.e., to a reduction in the "pitch" of the device, with the aim of increasing the current that can be extracted from the power device in use. In fact, given the shrinkage of the elementary cells and their consequent mutual proximity, processes based on the use of masks may present problems of alignment between areas belonging to layers arranged on the die to one another, with the possibility of undesired electrical phenomena arising due to layouts not complying with design specifications. Not least, the use of implantation masks to define areas of the SiC die with a variable doping profile may be complicated for the purpose of parameterizing the electrical characteristics of the device (such as on-state resistance, high electric field shielding of the gate area, etc.). Summary of the invention

[0010] It is therefore an object of various embodiments of the present disclosure to overcome or at least alleviate the disadvantages and limitations of the prior art.

[0011] According to various embodiments of the present disclosure, there is provided a manufacturing process for a silicon carbide power device with variable doping concentration, as defined in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to better understand the various embodiments of the present disclosure, preferred embodiments of the present disclosure are provided by way of non-limiting examples with reference to the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view of a power device according to an embodiment of the present disclosure;

[0014] FIG. 2A to FIG. 2I is a cross-sectional view of a semiconductor wafer in successive processing steps of a manufacturing process according to one embodiment of the present disclosure;

[0015] Figure 3 About FIG. 2A to FIG. 2I A simplified block diagram of the process;

[0016] Figure 4 is a cross-sectional view of a power device according to various embodiments of the present disclosure;

[0017] Figure 5 Shows Figure 4 Magnified details of

[0018] Figure 6 is a simplified block diagram of a manufacturing process according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Figure 1 1 shows a portion of a power device manufactured according to one embodiment of the present invention and is designated by the number 1. The power device 1 is, for example, a MOSFET, in particular a power MOSFET, more specifically a vertical conduction MOSFET obtained using silicon carbide (SiC) technology, and is accommodated in a die or chip not shown in the drawings. In the following, the power device 1 will therefore also be referred to as a "MOSFET" in an interchangeable manner, and this does not mean a loss of generality.

[0020] Figure 1 In its cross-sectional view, MOSFET 1 is shown in a reference system of mutually orthogonal axes X, Y, Z.

[0021] MOSFET 1 includes a plurality of basic cells, only one of which is illustrated in the drawing, which are identical to one another and are arranged in the same die so as to share a drain terminal D, a gate terminal G and a source terminal S; ie, the basic cells are electrically connected in parallel to one another.

[0022] The MOSFET 1 is formed in a body 2 of semiconductor material. The top of the body 2 is defined by a front side 2a and the bottom is defined by a back side 2b, the front side and the back side being opposite to each other in the Z-axis direction. The body 2 may comprise a substrate or a substrate on which one or more epitaxial layers are grown, and is made of silicon carbide, one of its polytypes, here the 4H-SiC polytype.

[0023] In one embodiment, in particular, the body 2 includes a substrate 10, the bottom of which is defined by a back side 2b, a first epitaxial layer 12 on the substrate 10, and a second epitaxial layer 22 (the second epitaxial layer 22 extends above the first epitaxial layer 12), and the top of the substrate 10 is defined by a front side 2a.

[0024] The substrate 10 is made of a single crystalline semiconductor material (eg, silicon carbide in one of its polytypes (here, polytype 4H-SiC)) and has a spatially symmetric lattice structure; the first epitaxial layer 12 and the second epitaxial layer 22 are made of the same material and retain the same crystal structure.

[0025] A drift region 101, a first current diffusion layer (hereinafter referred to as “first CSL”) 30 and a plurality of deep body regions 15 ( Figure 1 Two of them are shown in the figure). A second current diffusion layer (hereinafter referred to as “second CSL”) 40, a plurality of shallow body regions 20 ( Figure 1 Two of them are shown in FIG. 1 ) and a plurality of source regions 25 ( Figure 1 Two of them are shown in Figure 1).

[0026] Figure 1 The body 2 of semiconductor material, i.e. the substrate 10 and the drift region 101, has a first conductivity, for example, N-type. The deep body region 15 has a second conductivity opposite to the first conductivity, i.e., P-type, and has a first doping level (or dopant concentration) P1. The first CSL 30 is N-type and has a second doping level N1. The shallow body region 20 is P-type and has a third doping level P2. The second CSL 40 is N-type and has a fourth doping level N2. The first doping level P1 and the third doping level P2 may be different from each other, and similarly, the second doping level N1 and the fourth doping level N2 may also be different from each other. In any case, the first doping level P1 and the second doping level N1 are selected so that when the total volume of the deep body region 15 and the first CSL 30 is considered, the first total charge QP1 in the deep body region 15 is significantly greater than the second total charge QN1 in the first CSL 30. Typically, the first total charge QP1 in the deep body region 15 is at least five times greater than the second total charge QN1 in the first CSL 30. Finally, the plurality of source regions 25 have a first conductivity.

[0027] In the first epitaxial layer 12, adjacent deep body regions 15 are separated by portions of a first CSL 30 along the axis X, and in the second epitaxial layer 22, adjacent shallow body regions 20 are separated by portions of a second CSL 40 along the axis X. In addition, each shallow body region 20 at least partially covers and contacts a corresponding deep body region 15, and the second CSL 40 at least partially covers and contacts the first CSL 30.

[0028] Each source region 25 extends from the front side 2a and is at least partially contained in the corresponding shallow body region 20. At least one of the source regions 25 of each unit cell includes a body contact region 28 extending from the front side 2a as far as the corresponding shallow body region 20. Furthermore, each source region 25 and the second CSL 40 laterally delimit a channel region 27 in the corresponding shallow body region 20.

[0029] The deep body region 15 , the shallow body region 20 , the source region 25 , and the body contact region 28 extend in a direction parallel to the Y-axis in the form of strips.

[0030] The superposition of the first epitaxial layer 12 and the second epitaxial layer 22 makes it possible that in use, that is, when the voltage (V GS ) is greater than the basic unit's turn-on threshold voltage (V TH ), a current can flow between the source terminal S and the drain terminal D, through each channel region 27, the second CSL 40 and the first CSL 30, and the drift region 101. The first CSL 30 and the second CSL 40 actually form enrichment layers, which have the function of locally adjusting the resistance encountered by the charge carriers (and more generally, improving the value of the on-state resistance of the MOSFET 1), and the drift region 101 forms a drift layer for the charge carriers in use.

[0031] 2, and more generally Figure 1 The MOSFET 1 in FIG. 1 is obtained by forming the manufacturing process of various embodiments of the present disclosure, and the consecutive steps of the manufacturing process are as follows: FIG. 2A to FIG. 2I is illustrated in Figure 3 The process is schematically illustrated in the flow chart.

[0032] Figure 2AA cross-sectional view of a silicon carbide (4H-SiC polytype) wafer 100 is shown, here with a first conductivity (N-type) and a first surface 100a and a second surface 100b opposite to each other in the direction of the axis Z. The wafer 100 initially comprises a substrate 10 on which a first epitaxial layer 12 is formed by a first epitaxial growth (first step S1), for example with a thickness comprised between 1 μm and 60 μm along the axis Z. The crystal or lattice structure of the first epitaxial layer 12 is achieved by ion implantation using the channelization phenomenon.

[0033] The deep body region 15 and subsequently the first CSL 30 are formed by channeling ion implantation. A channeling implant is obtained when the ion beam during implantation is aligned with a channeling direction: for example, in SiC, a 000-1 direction or an 11-23 direction. Typically, the substrate is cut from an ingot grown in the 000-1 direction, with a surface tilt (due to the cutting of the wafer) of 4° for a substrate of 150 mm or 200 mm diameter. To perform a channeling implant on a 000-1 wafer, the ion beam during implantation is directed with a tilt of 4°, and for a wafer grown in the 11-23 direction, the ion beam during implantation is directed with a tilt of 13° or 21°.

[0034] refer to Figure 2B , Figure 2B A second step S2 of the manufacturing process is identified, a deep body mask 105 is applied on the first surface 100a of the wafer 100. The deep body mask 105 exposes a portion of the wafer 100 that is to form a deep body region 15. Using the deep body mask 105, a first channeling ion implantation of dopant ions is performed (here indicated by arrows 110, tilted with respect to the axis Z to indicate the channeling implantation), the dopant ions being of P type, i.e. corresponding to a second conductivity opposite to the first conductivity of the wafer 100. The first channeling ion implantation is performed using ions of, for example, aluminum (Al) or boron (B) and an implantation energy comprised between 20 keV and 2000 keV. The deep body region 15 is thus defined, having a first thickness T1 comprised between 0.5 and 5 μm along the Z axis starting from the first surface 100a, having a first dimension L1 comprised between 1 and 10 μm along the X axis, and having an order of magnitude of 1×10 17 Up to 1×10 19 Atom / cm 3 The first doping level P1 of .

[0035] According to one embodiment, the wafer 100 subsequently undergoes an annealing step for activating the dopant ions and reducing lattice defects that may be caused by the implantation.

[0036] In the third step S3 ( Figure 2C), the deep body mask 105 is used to create a plurality of first intentionally damaged regions (also referred to as "IDRs") 50 for the purpose of self-aligned formation of the first CSL 30, as described below. The first damaged regions 50 are surface regions of the wafer 100, and if the deep body mask 105 is used again, the first damaged regions 50 are obtained in regions corresponding to the corresponding deep body regions 15.

[0037] The applicant has in fact discovered that the channeling effect can be altered by intentionally damaging the surface area of ​​the wafer 100. The damage can be achieved, for example, by first random ion implantation of a non-reactive or non-doping species (i.e., a non-channeling implantation) (at Figure 2C This is obtained by causing damage to the crystal lattice of the wafer 100 without locally changing its conductive properties. Chemical species suitable for this purpose include, for example, ions of silicon (Si), argon (Ar), germanium (Ge), helium (He).

[0038] Thus, according to one aspect of the present disclosure, the first damaged regions 50 are formed at the first surface 100a and are aligned with (along the axis X and the axis Y) and confined in the corresponding deep body regions 15 so as to locally alter or inhibit channelization in a subsequent implantation step to form the first CSL 30. Each first damaged region 50 extends from the first surface 100a to a maximum depth in the wafer 100, for example, comprised between 0.05 and 0.2 μm (including extreme values). The thickness (depth along the axis Z) of each first damaged region 50 may be uniform or may vary between a minimum of 0.05 μm and a maximum of 0.2 μm. Figure 2C As illustrated in , since the deep body mask 105 is also used in the third step S3 , the extension of each first damaged region 50 along the axis X is substantially equal to the first size L1 of the corresponding deep body region 15 .

[0039] In order to form the first damaged region 50, a 13 Atom / cm 2 The implantation is performed at an implant dose and energy sufficient to cause atoms to be displaced from the crystal structure to a desired depth (e.g., energy in the range of 30-300 keV). The damage-causing implant is performed in the absence of channeling conditions, and annealing of the wafer 100 during the process is avoided to avoid removing the resulting damage.

[0040] According to another embodiment, the first damaged area 50 is obtained by one or more steps of localized etching of the first surface 100a through the deep body mask 105 at the deep body area 15. For example, a RIE (Reactive Ion Etching) process with the characteristics of physical etching can be used, that is, plasma bombardment with Ar ions. The depth that can be obtained is, for example, equal to 0.1 μm.

[0041] The lattice structure of the wafer 100 in the first damaged region 50 is different from the lattice structure of the undamaged region of the wafer 100. Specifically, in the case where it is damaged, the wafer 100 has an amorphous structure or a disordered crystal structure or a lattice structure in the case where there is no spatial symmetry in the portion of the wafer 100 where there is no intentional damage.

[0042] Once the deep body mask 105 has been removed, the first damaged region 50 extends over a portion of the first epitaxial layer 12 where no Figure 1 In other words, the first damaged region 50 is formed in a portion complementary to a portion of the wafer 100 into which the first CSL 30 is to be implanted (third step S3). Figure 2D It relates to a fourth step S4 of the manufacturing process and in fact shows how the first damaged region 50 acts as an implantation mask for a second channeling ion implantation (here indicated by arrow 130, tilted with respect to the axis Z to indicate the channeling implantation) of dopant ions of N type (i.e. corresponding to the first conductivity).

[0043] In detail, the entire wafer 100 is exposed to the second channeling ion implantation, but the first CSL 30 is actually obtained only in the portion of the wafer 100 without surface damage, i.e. outside the deep body region 15. In this way, the deep body region 15 is shielded from the influence of the second channeling ion implantation, and at the same time, the first CSL 30 is defined in the first epitaxial layer 12 in a self-aligned manner relative to the deep body region 15, as far as the desired depth determined by the implantation conditions.

[0044] The second channeling ion implantation (arrow 130) is performed, for example, using phosphorus (P) or nitrogen (N) ions and an implantation energy comprised between 20 keV and 2000 keV. These parameters define a second doping level N1 between the plurality of deep body regions 15, for example 10 17 Atom / cm 3and a depth along the axis Z starting from the first surface 100a, which in the MOSFET 1 is, for example, equal to the first thickness T1 of the deep body region 15. Specifically, the first doping level P1 of the deep body region 15 and the second doping level N1 of the first CSL 30 are also selected in relation to the total volume of the deep body region 15 and the first CSL 30, such that a first total charge QP1 in the deep body region 15 is at least five times greater than a second total charge QN1 in the first CSL 30.

[0045] In this step, a thin implantation layer with a maximum thickness of 0.3 μm can be formed in the first damaged region 50. In other words, the CSL can be superficially confined in the damaged region. The applicant has found that the presence of such a thin CSL does not affect the operation of the MOSFET 1 relative to the covering layer formed in a subsequent step. However, as described below, and as applied in the manufacturing process forming the subject matter of various embodiments of the present disclosure, in order to prevent possible crystal defects in the layer covering the damaged region, the first damaged region 50 is selectively removed before the subsequent processing steps, for example by etching the wafer 100 in a hydrogen (H2) environment.

[0046] Therefore, the Figure 1 1. In particular, the drift region 101 itself is also defined in this way in the portion of the first epitaxial layer 12 that is not occupied by the first CSL 30 and the deep body region 15.

[0047] Next( Figure 2E , step S5), a second epitaxial layer 22 is formed on the wafer 100 by second epitaxial growth. Specifically, like the wafer 100, the second epitaxial layer 22 is made of silicon carbide (4H-SiC polytype), that is, a material capable of performing ion implantation by utilizing the channelization phenomenon, and has, for example, 1×10 15 Up to 1×10 17 Atom / cm 3 The second epitaxial layer 22 is grown to a second thickness T2 comprised between 0.1 and 3 μm, for example equal to 1.5 μm (measured starting from the first surface 100 a ).

[0048] Wafer 100 and second epitaxial layer 22 form a working wafer 118 which substantially corresponds to body 2 and extends between front side 2a and back side 2b of body 2. Working wafer 118 is processed as described for the steps following fifth step S5 in order to define the structures of MOSFET 1 present in second epitaxial layer 22.

[0049] refer to Figure 2F (Sixth step S6), a shallow body mask 125 is applied on the second epitaxial layer 22, and the shallow body mask 125 exposes the portion of the second epitaxial layer 22 where the shallow body region 20 is to be formed. Specifically, the shallow body mask 125 has openings at positions corresponding to the respective deep body regions 15 in the direction of the axis Z, and these openings do not have to have the same size. Using the shallow body mask 125, a third channeled ion implantation of dopant ions (here indicated by arrow 140, inclined with respect to the axis Z to indicate channeled implantation) is performed, and the dopant ions are of P-type, that is, corresponding to a second conductivity opposite to the first conductivity of the second epitaxial layer 22. The third channeled ion implantation is performed, for example, using ions of aluminum (Al) or boron (B) and an implantation energy included between 20 keV and 2000 keV. The shallow body region 20 thus defined has a depth equal to the second thickness T2 of the second epitaxial layer 22, a second dimension L2 included between 1 and 10 μm along the axis X, and a third doping level P2 on the order of 1×10 17 to 1×10 19 atoms / cm 3 .

[0050] In Figure 2F the working wafer 118, and thus in Figure 1 the MOSFET 1, the depth of the shallow body region 20 starting from the front face 2a corresponds to the thickness of the second epitaxial layer 22. In addition, the shallow body mask 125 aligns the shallow body regions 20 of the MOSFET 1 with the deep body regions 15 in a direction parallel to the axis Z. That being said, each shallow body region 20 covers and contacts the corresponding deep body region 15. The first dimension L1 and the second dimension L2 are different from each other, and specifically, the dimension of each shallow body region 20 along the axis X is smaller than the corresponding dimension of the corresponding deep body region 15.

[0051] The first dimension L1 and the second dimension L2 are design parameters of the MOSFET 1 corresponding to the electrical performance of the MOSFET 1, as described in more detail below. The first dimension L1 and the second dimension L2 can thus be selected, thereby adjusting the corresponding deep body mask 105 and shallow body mask 125 such that each deep body region 15 will optionally have a dimension along the X-axis greater than ( Figure 1 ), smaller than, or equal to the extent of the corresponding shallow body region 20 (L1 > L2, L1 < L2, or L1 = L2, respectively).

[0052] In the seventh step S7( Figure 2G), the shallow body mask 125 is used to create a plurality of second regions 70 that are intentionally damaged for the purpose of self-aligned formation of the second CSL 40. The second damaged regions 70 are surface regions of the second epitaxial layer 22 that are aligned (along the X-axis and the Y-axis) with and confined in the corresponding shallow body regions 20 so as to locally alter or inhibit channelization.

[0053] Such damage can be corrected, for example, by a second random (ie, non-channeling) ion implantation of a non-reactive or non-doping species (in Figure 2G The second epitaxial layer 22 is obtained by causing damage to the crystal lattice of the second epitaxial layer 22 without locally changing its conductive properties. Chemical species designed for this purpose include, for example, ions of silicon (Si), argon (Ar), germanium (Ge), helium (He).

[0054] In order to form the second damaged region 70, a 13 Atom / cm 2 The implantation dose is 1000 and the energy (for example, energy in the range of 30-300 keV) sufficient to cause atoms to be displaced from the crystal structure to the desired depth. Each second damaged region 70 extends from the front side 2a to a maximum depth in the second epitaxial layer 22, for example, between 0.05 and 0.2 μm (including extreme values).

[0055] Once the shallow bulk mask 125 has been removed, the damaged region 70 is no longer present in the second epitaxial layer 22. Figure 1 The second damaged region 70 extends above the portion of the second CSL 40 of the MOSFET 1. In other words, the second damaged region 70 is formed (seventh step S7) in a portion complementary to the portion of the second epitaxial layer 22 into which the second CSL 40 is to be implanted. Figure 2H It relates to the eighth step S8 of the manufacturing process and in fact shows how the second damaged region 70 acts as an implantation mask for a fourth channeling ion implantation (here indicated by arrow 160, tilted with respect to the axis Z to indicate the channeling implantation) of dopant ions, which are of N type, i.e. corresponding to the first conductivity.

[0056] In detail, the entire second epitaxial layer 22 is exposed to the fourth channeling ion implantation, but the formation of the second CSL 40 by channelization is actually obtained only in the portion of the epitaxial layer 22 without surface damage, i.e., outside the shallow body region 20. In this way, the shallow body region 20 is shielded from the fourth channeling ion implantation, and at the same time, the second CSL 40 is defined in the second epitaxial layer 22 in a self-aligned manner with respect to the plurality of shallow body regions 20.

[0057] The fourth channeling ion implantation (arrow 160) is performed, for example, using nitrogen or phosphorus ions and an implantation energy comprised between 20 keV and 2000 keV. The parameters define a fourth doping level N2 between the plurality of shallow body regions 20, for example, 10 17 Atom / cm 3 of the order of magnitude, or between 2 and 20 times the doping level of the portion of the semiconductor layer housing it; and a depth along the axis Z starting from the front side 2a, which in the MOSFET 1 is, for example, equal to the second thickness T2 of the shallow body region 20.

[0058] At the end of the fourth channeling ion implantation, the second CSL 40 of the MOSFET 1 covers and contacts the first CSL 30 , and at least partially covers and contacts the deep body region 15 .

[0059] The second damaged region 70 is then selectively removed, for example, by etching in a hydrogen environment (H2) of the working wafer 118 .

[0060] In one embodiment, Figure 4 Neutralization Figure 5 As illustrated in the enlarged detail of , the deep body region and the first CSL (here designated by 115 and 130, respectively) can be obtained by repeating the programming for a number of iterations Q, steps S1'-S4' being similar to the steps S1-S4 already described. In fact, in each iteration: a portion of the first epitaxial layer 12 is grown (S1', Figure 6 ); performing channeling ion implantation of dopant ions using the deep body mask 105 (S2 ', Figure 6 ), thereby obtaining a portion of the deep body region 115 having corresponding concentrations P11, ..., P1K, ..., P1Q; and forming an intentionally damaged region (not shown) on the surface of the corresponding portion of the deep body region 115 by one or more localized etching steps of the deep body mask 105 (S3', Figure 6 ); and using the damaged region as an implantation mask, a portion of the first CSL130 having a corresponding concentration of N11, ..., N1K, ..., N1Q is formed by channeling ion implantation (S4 ', Figure 6 The concentrations of the dopant species P11, ..., P1K, ..., P1Q and N11, ..., N1K, ..., N1Q may be selected according to design preference, in any case such that the first total charge QP1′ in the deep body region 115 is significantly greater than the second total charge QN1′ in the first CSL 130 (at Figure 4 ), typically at least five times the second total charge QN1′ in the first CSL 130. In addition, the concentrations of the dopant species P1K, ..., P1Q and N11, ..., N1K, ..., N1Q may be selected such that in each Kth portion ( Figure 5 ), a first total layer charge QP1K in a portion of the deep body region 115 is significantly greater than a second total layer charge QN1K in a portion of the first CSL 130 , typically at least five times greater than the second total layer charge QN1K in a portion of the first CSL 130 .

[0061] The process then continues with steps S5-S8 already described.

[0062] After the eighth step S8 of the process of manufacturing the body 2, the basic unit of the MOSFET 1 is formed. Fig.2I , where only one basic unit is illustrated, a source region 25 (having a first conductivity) and a body contact region 28 (having a second conductivity) are defined (if present) by formation techniques known in the art (such as implantation, diffusion, etc.).

[0063] Each source region 25 and each body contact region 28 extend from the front side 2a of the epitaxial layer 22 in the respective shallow body region 20 and extend to respective depths of, for example, 0.2 μm and 2 μm. The source region 25 has a doping level (denoted as N+) that is typically greater than the N doping level of the drift region 101 and is 1×10 18 Up to 1×10 20 Atom / cm 3 Each source region 25 extends along the X axis, for example, 2 μm. The body contact region 28 has a 1×10 18 Up to 1×10 20 Atom / cm 3 A doping level of the order of magnitude (labeled as P+).

[0064] therefore, Figure 1 The second layer 22 of the MOSFET 1 is completed, and in fact the entire body 2 is also completed.

[0065] Next, a plurality of gate regions 35 are formed on the front side 2a of the body 2 by deposition and lithography defined steps using typical techniques in the art. The gate regions 35 are each formed by: a gate insulating layer 36 (e.g., silicon oxide) in contact with the front side 2a of the body 2; a gate conductive layer 37 (e.g., a polysilicon layer) directly covering the gate insulating layer 36; and a passivation layer 38 covering the gate conductive layer 37 and sealing the gate conductive layer 37 together with the gate insulating layer 36. In detail, the gate insulating layer 36 of each gate region 35 extends over a corresponding portion of the second CSL 40, extends over two channel regions 27 adjacent to and delimiting the corresponding portion of the second CSL 40, and partially extends over two source regions 25 adjacent to the corresponding channel region 27. The gate conductive layers 37 of the gate regions 35 are electrically connected in parallel in a manner not shown here, thus forming the gate terminal G of the MOSFET 1.

[0066] The MOSFET 1 further comprises a source metallization region 26, e.g. of a metallic material and / or a metal silicide, which forms a source terminal S of the MOSFET 1 and extends over the front side 2a of the body 2 in direct electrical contact with the source region 25 and with a body contact region 28. The body contact region 28 is in fact used to bias the shallow body region 20 and therefore the deep body region 15 at the potential of the source terminal S.

[0067] Finally, MOSFET 1 includes a drain metallization region 11 of a conductive material (e.g., metal or silicide), which extends over the back side 2b of the body 2 (in the opposite direction to the source metallization region 26), is in direct electrical contact with the substrate 10, and forms the drain terminal D of MOSFET 1.

[0068] The MOSFET 1 manufactured according to the process of various embodiments of the present disclosure exhibits improved electrical performance. The use of limited implantation energy (possibly due to the channelization phenomenon) makes it possible to obtain a reduced lateral dispersion of the dopant ions and thus obtain a concentration profile of the dopant ions in the body 2 that can be controlled and consistent with that established at the design stage. In addition, since the first layer 12 and the second layer 22 are defined using contained implantation energies, a thin mask can be used, which makes it easier to obtain greater lateral definition.

[0069] The technique of resorting to intentionally damaged regions (IDR), performed under random implantation conditions (i.e. without channelization) on already implanted regions (here, for example, obtained by means of a channelized implantation), makes it possible to further improve the lateral definition, in particular because the regions formed in a step subsequent to the damage can be self-aligned with respect to already existing regions, which already present, for example, different doping levels or opposite doping levels. By locally modifying or suppressing the channelization by means of the damage, it is possible to practically choose at will the extension of the region to be formed in a subsequent step (by means of the channelization) and to protect the already existing region from the subsequent channelized implantation, thereby maintaining its desired doping level. In fact, the surface damaged regions act as an implantation mask with respect to the subsequent channelized implantation.

[0070] In this way, the doping level within an epitaxially grown layer (here silicon carbide) can be defined precisely and with low production costs (implantation energy involved, self-alignment), the profile of the epitaxially grown layer being variable both along the dimensions of the layer itself (here, for example, in the XY plane) and in the direction of superposition of the layers (here along the Z axis).

[0071] In MOSFET 1, this results in greater flexibility in defining the junction between the body region and the drain region and in controlling the concentration of the conductive channel, and has an overall advantage in the scalability of MOSFET 1 in a shrinking direction and therefore in increasing the number of basic units.

[0072] The first size L1 and the second size L2, such as the first thickness T1 and the second thickness T2 and the first doping level P1 and the third doping level P2, are actually design parameters of the MOSFET 1 corresponding to the electrical performance of the MOSFET 1. In detail, the deep body region 15 and the shallow body region 20 form an overall body structure, which has the function of shielding the layers covering the body 2 (especially the gate insulating layer 36) relative to the strong electric field of the body 2. Therefore, the improved shielding can lead to a reduced on-voltage of the power device.

[0073] The presence of the deep body region 15 means that when the MOSFET 1 is in the off state and the voltage (V DS ) is high (e.g., even above 400 V), a higher value of the electric field is obtained at a depth at a certain distance from the front side 2a in the body 2. This causes the electric field to exhibit lower values ​​in shallower parts of the body 2 (here in the second CSL 40), especially near the gate insulating layer 36. Therefore, the MOSFET 1 exhibits reliable performance.

[0074] The first dimension L1 and the second dimension L2, as well as the first thickness T1 and the second thickness T2 and the first doping level P1 and the third doping level P2 are selected so as to provide the main structure with a shape (in MOSFET 1, for example, the shape of an inverted T) and a doping distribution that can be used to obtain desired electrical parameters (such as, precisely, shielding with respect to the field), which is also related to the size of the single basic unit.

[0075] At the same time, the first CSL 30 and the second CSL 40 also form a current diffusion structure, the size of the current diffusion structure (relative to the shape and size of the main structure) and its doping distribution can be flexibly selected by means of the process according to various embodiments of the present disclosure. In particular, the different dopant concentrations between different CSLs enable effective adjustment of the channel concentration and thus effectively adjust the electrical parameters of the device, thereby further counteracting undesirable phenomena such as shrinkage of the main area in use and uncontrolled changes in the on-state resistance.

[0076] Finally, it is evident that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure, as defined in the appended claims.

[0077] For example, the body structure may have a shape different from that illustrated. The deep body region may have a smaller extension (along axis X) than the shallow body region; in this case, the shallow body region at least partially covers the first CSL, being in contact with the first CSL. Alternatively, the deep body region and the shallow body region may have the same extension (along axis X).

[0078] In a variation of the manufacturing process (not shown), the channeling ion implantation of the first CSL 30 and the second CSL 40 defines respective depths that are less than or greater than the aforementioned first thickness T1 and second thickness T2.

Claims

1. A method for manufacturing a vertical conduction power device, comprising: forming a layer, the layer comprising a semiconductor material, the semiconductor material having a lattice structure, the lattice structure having spatial symmetry, the layer growing a first epitaxial layer, the first epitaxial layer having the lattice structure having spatial symmetry and a first conductivity; forming a first body region in the first epitaxial layer, the first body region having a second conductivity, the second conductivity being opposite to the first conductivity; as well as forming a first current spreading layer in the first epitaxial layer between the first body regions, the first current spreading layer having the first conductivity; The forming of the first main body region comprises: performing a first body channeling ion implantation using the first body mask; and The forming of the first current diffusion layer comprises: forming a first shallow damaged region in the first body region through the first body mask so that the lattice structure is changed in the first shallow damaged region; and A first current spreading channeling ion implantation is performed using the first shallow damaged region as an implantation mask.

2. The manufacturing method according to claim 1, wherein forming the first shallow damaged region comprises: Do one of the following: Non-channeling random ion implantation of a non-reactive species or a non-dopant ion species selected from the group consisting of: silicon, argon, germanium, helium; and First chemical etching. 3 . The manufacturing method of claim 1 , wherein the first doping level of the first body region and the second doping level of the first current spreading layer are selected such that a first total charge in the first body region is at least five times a second total charge in the first current spreading layer.

4. The manufacturing method according to claim 1, further comprising: forming the first epitaxial layer, and growing a second epitaxial layer, wherein the second epitaxial layer has the spatially symmetric lattice structure and the first conductivity; forming a second body region in the second epitaxial layer, the second body region having the second conductivity; as well as forming a second current diffusion layer between the second body regions of the second epitaxial layer, the second current diffusion layer having the first conductivity; The forming of the second main body region comprises: performing a second body channeling ion implantation using a second body mask; and The forming of the second current diffusion layer comprises: forming a second shallow damaged region in the second body region through the second body mask so that the lattice structure is changed in the second shallow damaged region of the second body region; and A second current spreading channeling ion implantation is performed using the second shallow damaged region of the second body region as an implantation mask. 5 . The manufacturing method according to claim 4 , wherein the second body mask has openings at positions corresponding to the respective first body regions.

6. The manufacturing method according to claim 4, further comprising: The first shallow damaged region is removed before growing the second epitaxial layer.

7. The manufacturing method according to claim 4, further comprising: The second shallow damaged area is removed. 8 . The manufacturing method according to claim 4 , wherein the second body region extends in depth until penetrating the second epitaxial layer and contacts the corresponding first body region. 9 . The manufacturing method according to claim 4 , wherein the second current diffusion layer extends in depth until penetrating the second epitaxial layer and contacts the first epitaxial layer. 10 . The manufacturing method according to claim 3 , wherein the first doping level of the first body region is different from a third doping level of the second body region, and / or the second doping level of the first current spreading layer is different from a fourth doping level of the second current spreading layer.

11. The manufacturing method according to claim 4, wherein forming the second shallow damaged region comprises: Do one of the following: a second non-channeling random ion implantation of a non-reactive species or a non-dopant ion species selected from the group consisting of: silicon, argon, germanium, helium; and Second chemical etching.

12. The manufacturing method according to claim 1, further comprising: Repeat iteratively: growing a portion of the first epitaxial layer, the portion of the first epitaxial layer having the lattice structure with spatial symmetry and the first conductivity; forming a portion of the first body region in a last grown portion of the first epitaxial layer, the portion of the first body region having the second conductivity; as well as forming a portion of the first current spreading layer between portions of the first body region of the last grown portion of the first epitaxial layer; wherein the portion of the first body region forming the last grown portion of the first epitaxial layer comprises: performing a corresponding body channeling ion implantation using the first body mask; and The portion forming the first current spreading layer includes: forming a shallow damaged region in the portion of the first body region of the last grown portion of the first epitaxial layer through the first body mask, such that the lattice structure is altered in the first shallow damaged region of the portion of the first body region of the last grown portion of the first epitaxial layer; and A corresponding current spreading channeling ion implantation is performed using the first shallow damaged region of the portion of the first body region of the last grown portion of the first epitaxial layer as an implantation mask.

13. The manufacturing method according to claim 1, wherein the semiconductor material comprises silicon carbide.

14. A vertical conduction power device, comprising: A substrate, the substrate comprising a semiconductor material, the semiconductor material having a lattice structure, and the lattice structure having spatial symmetry; A first epitaxial layer, the first epitaxial layer is arranged on the substrate and has the lattice structure with spatial symmetry and a first conductivity; a first body region, the first body region being in the first epitaxial layer, the first body region having a second conductivity, the second conductivity being opposite to the first conductivity; as well as A first current diffusion layer is provided in the first epitaxial layer between the first body regions, and has the first electrical conductivity. 15 . The power device of claim 14 , wherein the first doping level of the first body region and the second doping level of the first current spreading layer are selected such that a first total charge in the first body region is at least five times a second total charge in the first current spreading layer.

16. The power device according to claim 14, further comprising: a second epitaxial layer, the second epitaxial layer being arranged on the first epitaxial layer and having the spatially symmetric lattice structure and the first conductivity; a second body region, the second body region being in the second epitaxial layer, the second body region having the second conductivity; as well as a second current diffusion layer, the second current diffusion layer being between the second body regions of the second epitaxial layer, the second current diffusion layer having the first conductivity; The second main body region extends through the second current diffusion layer in a direction perpendicular to a surface of the second current diffusion layer and is located at a position corresponding to and in contact with the corresponding first main body region.

17. The power device of claim 14, wherein the semiconductor material comprises silicon carbide.

Images