Manufacturing method of grid electrode of semi-floating gate transistor
The control gate and floating gate of the semi-floating gate transistor are removed by one-step etching, which solves the problem of gate structure defects in the prior art, and achieves the effect of cost reduction and structural improvement.
Patent Information
- Application Number
- CN202411464820.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-18
AI Technical Summary
In the prior art, the gate of the semi-floating gate transistor is prone to structural defects, resulting in the inability to form the desired gate structure.
The process cost is reduced by removing unnecessary parts of the control gate and floating gate by forming the tunneling field effect transistor gate in one step, saving a photocopy mask.
The emergence of structural defects is effectively avoided, and a semi-floating gate transistor gate that meets the requirements is formed, reducing process costs.
Smart Images
Figure CN119486170A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a gate of a semi-floating gate transistor. Background Art
[0002] Semi-floating gate transistor is an alternative concept of DRAM devices. Different from the usual 1T1C structure, semi-floating gate device consists of a floating gate transistor, an embedded tunneling transistor and a PN junction. The floating gate of the floating gate transistor is written and erased through the channel and PN junction of the embedded tunneling transistor.
[0003] The gate of a semi-floating gate transistor is composed of three parts: a floating gate, a control gate, and a tunneling field effect transistor gate. In the existing process, after forming a floating gate and a control gate on a substrate, a tunneling field effect transistor gate material layer and a first mask layer are formed in sequence, and then the first mask layer is used as a mask to etch the tunneling field effect transistor gate material layer to form the tunneling field effect transistor gate while exposing the top of the control gate; then, a second mask layer is formed, and the second mask layer is used as a mask to remove unnecessary parts of the control gate and the floating gate by etching. Due to the influence of the process window, the part of the second mask layer formed on the control gate has a problem of poor line roughness (LWR), and there is a serious residue problem at the removal of the second mask layer after the etching of the control gate and the floating gate is completed, which ultimately leads to the inability to form the gate structure required for the semi-floating gate transistor. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for manufacturing a gate of a semi-floating gate transistor, so as to solve the problem that the gate of the semi-floating gate transistor in the prior art is prone to structural defects.
[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for manufacturing a gate of a semi-floating gate transistor, comprising:
[0006] Step 1, providing a substrate, and forming a floating gate and a control gate on the substrate;
[0007] Step 2, forming a first mask layer to define the pattern of the middle removed portion of the control gate and the floating gate;
[0008] Step 3, forming a tunneling field effect transistor gate material layer and a second mask layer in sequence;
[0009] Step 4: etching the tunneling field effect transistor gate material layer, the control gate and the floating gate in sequence, and removing the second mask layer and the first mask layer after the etching is completed.
[0010] Preferably, a gate insulating layer is formed under the floating gate.
[0011] Preferably, the material of the gate insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride or zirconium oxide.
[0012] Preferably, an inter-gate dielectric layer is formed between the floating gate and the control gate.
[0013] Preferably, the inter-gate dielectric layer is an ON layer or an ONO layer.
[0014] Preferably, the material of the tunneling field effect transistor gate material layer includes polysilicon.
[0015] Preferably, the first mask layer and the second mask layer are made of the same material.
[0016] Preferably, the material of the first mask layer and the second mask layer includes silicon nitride.
[0017] Preferably, in step four, the second mask layer and the first mask layer are removed by dry etching or wet etching.
[0018] Preferably, the wet etching solution includes hot phosphoric acid.
[0019] As described above, the method for manufacturing the gate of a semi-floating gate transistor provided in the present application has the following beneficial effects: compared with the prior art, the gate of a tunneling field effect transistor is formed by etching in one step while removing unnecessary parts of the control gate and the floating gate, thereby saving a mask and reducing the process cost, and the semi-floating gate transistor gate formed will not have structural defects. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1A-1E It is a schematic diagram of a cross-sectional structure of a device formed after completing various steps of preparing a gate of a semi-floating gate transistor according to the prior art;
[0022] Figure 2 A flow chart showing a method for manufacturing a gate of a semi-floating gate transistor provided by an embodiment of the present application;
[0023] Figure 3A-3D Shown is a schematic diagram of a device cross-sectional structure formed after each step is completed in the method for manufacturing a gate of a semi-floating gate transistor provided in an embodiment of the present application. DETAILED DESCRIPTION
[0024] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0029] The process steps for preparing the gate of a semi-floating gate transistor according to the prior art are as follows:
[0030] Step a, such as Figure 1A As shown, a floating gate 101 and a control gate 102 are formed on a substrate 100;
[0031] Step b, such as Figure 1B As shown, a tunneling field effect transistor gate material layer 103 and a first mask layer 105 are formed in sequence;
[0032] Step c, such as Figure 1C As shown, the tunneling field effect transistor gate material layer 103 is etched using the first mask layer 105 as a mask until the control gate 102 is exposed;
[0033] Step d, such as Figure 1D As shown, after removing the first mask layer 105, a second mask layer 106 is formed;
[0034] Step e, such as Figure 1E As shown, after the control gate 102 and the floating gate 101 are sequentially etched using the second mask layer 106 as a mask, the second mask layer 106 is removed.
[0035] Due to the influence of the process window, the part of the second mask layer 106 formed on the control gate 102 has a problem of poor line roughness, which affects the etching accuracy when implementing step e. There is residue after removing the second mask layer 106, which ultimately makes it impossible to form the gate structure required for the semi-floating gate transistor.
[0036] In order to solve this problem, the present application provides a method for manufacturing a gate of a semi-floating gate transistor.
[0037] See also Figure 2 , which shows a flow chart of a method for manufacturing a gate of a semi-floating gate transistor provided in an embodiment of the present application.
[0038] like Figure 2 As shown, the method for manufacturing the gate of the semi-floating gate transistor includes the following steps:
[0039] Step 1, providing a substrate, and forming a floating gate and a control gate on the substrate;
[0040] Step 2, forming a first mask layer to define the pattern of the middle removed portion of the control gate and the floating gate;
[0041] Step 3, forming a tunneling field effect transistor gate material layer and a second mask layer in sequence;
[0042] Step 4: etching the tunneling field effect transistor gate material layer, the control gate and the floating gate in sequence, and removing the second mask layer and the first mask layer after the etching is completed.
[0043] In step one, if Figure 3A As shown, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 300 may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate 300 according to the type of device structure formed on the substrate 300, so the type of the substrate 300 should not limit the protection scope of the present invention.
[0044] As an example, the steps of forming a floating gate 301 and a control gate 302 on a substrate 300 include: after forming a groove in the substrate 300, forming a gate insulating layer (not shown in the figure); forming a first gate material layer, an inter-gate dielectric material layer and a second gate material layer in sequence; etching the second gate material layer, the inter-gate dielectric material layer and the first gate material layer in sequence to form a control gate 302, an inter-gate dielectric layer 310 and a floating gate 301.
[0045] Exemplarily, the material of the gate insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and the like, the material of the first gate material layer and the second gate material layer includes polysilicon, and the inter-gate dielectric material layer can be a silicon oxide layer and a silicon nitride layer (ON layer) stacked from bottom to top or a silicon oxide layer, a silicon nitride layer and a silicon oxide layer (ONO layer) stacked from bottom to top.
[0046] In step 2, if Figure 3B As shown, a first mask layer 303 is formed to define patterns of the control gate 302 and the middle removed portions of the floating gate 301 .
[0047] As an example, the steps of forming the first mask layer 303 include: forming a mask material layer, an anti-reflective coating and a photoresist layer on the substrate 300 in sequence; after forming a pattern of the first mask layer 303 in the photoresist layer by a photolithography process, etching the anti-reflective coating and the mask material layer in sequence; after etching is terminated, removing the photoresist layer and the anti-reflective coating.
[0048] Exemplarily, the material of the first mask layer 303 includes silicon nitride.
[0049] In step three, if Figure 3C As shown, a tunneling field effect transistor gate material layer 305 and a second mask layer 306 are formed in sequence.
[0050] As an example, the tunneling field effect transistor gate material layer 305 is formed by a deposition process, and the material of the tunneling field effect transistor gate material layer 305 includes polysilicon. The deposition process is preferably a conformal deposition process.
[0051] As an example, the steps of forming the second mask layer 306 include: forming a mask material layer, an anti-reflective coating and a photoresist layer on the tunneling field effect transistor gate material layer 305; after forming a pattern of the second mask layer 306 in the photoresist layer through a photolithography process, etching the anti-reflective coating and the mask material layer in sequence; after etching is terminated, removing the photoresist layer and the anti-reflective coating.
[0052] Exemplarily, the material of the second mask layer 306 includes silicon nitride.
[0053] In step 4, if Figure 3DAs shown, the tunneling field effect transistor gate material layer 305, the control gate 302 and the floating gate 301 are etched in sequence, and the second mask layer 306 and the first mask layer 303 are removed after the etching is completed.
[0054] As an example, the etching is dry etching, and the second mask layer 306 and the first mask layer 303 are removed by another dry etching or wet etching.
[0055] Exemplarily, the wet etching solution includes hot phosphoric acid.
[0056] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0057] In summary, the manufacturing method of the semi-floating gate transistor gate provided by the present application forms the tunneling field effect transistor gate by etching in one step while removing the unnecessary parts of the control gate and the floating gate, thereby saving a photomask and reducing the process cost, and the semi-floating gate transistor gate formed will not have structural defects. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0058] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.
Claims
1. A method for manufacturing a gate of a semi-floating gate transistor, characterized in that: The method comprises: Step 1, providing a substrate, and forming a floating gate and a control gate on the substrate; Step 2, forming a first mask layer to define the pattern of the middle removed portion of the control gate and the floating gate; Step 3, forming a tunneling field effect transistor gate material layer and a second mask layer in sequence; Step 4: etching the tunneling field effect transistor gate material layer, the control gate and the floating gate in sequence, and removing the second mask layer and the first mask layer after the etching is completed.
2. The method according to claim 1, characterized in that A gate insulating layer is formed under the floating gate.
3. The method according to claim 2, characterized in that The material of the gate insulating layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride or zirconium oxide.
4. The method according to claim 1, characterized in that: An inter-gate dielectric layer is formed between the floating gate and the control gate.
5. The method according to claim 4, characterized in that The inter-gate dielectric layer is an ON layer or an ONO layer.
6. The method according to claim 1, characterized in that The material of the tunneling field effect transistor gate material layer includes polysilicon.
7. The method according to claim 1, characterized in that The first mask layer and the second mask layer are made of the same material.
8. The method according to claim 7, characterized in that The material of the first mask layer and the second mask layer includes silicon nitride.
9. The method according to claim 1, characterized in that: In the step four, the second mask layer and the first mask layer are removed by dry etching or wet etching.
10. The method according to claim 9, characterized in that The wet etching solution includes hot phosphoric acid.