Semiconductor power device

Abstract

The embodiment of the invention provides a semiconductor power device. The semiconductor power device comprises a substrate, an epitaxial layer, a gate electrode, a gate oxide layer and Schottky metal. The epitaxial layer comprises a well region arranged on one side of the groove; the source region is arranged on one side, facing the top surface of the epitaxial layer, of the well region; the first shielding region is positioned on one side, far away from the trench, of the source region and the well region; the second shielding region is positioned on one side, far away from the source region and the well region, of the groove; the third shielding region is positioned on one side, far away from the source region and the well region, of the second shielding region; the first, second and third shielding areas are arranged at intervals; the epitaxial layer further comprises a first sub-region located between the second shielding region and the third shielding region; the Schottky metal is arranged on the top surface of the epitaxial layer, is respectively connected with the second shielding region, the third shielding region and the first sub-region, and is insulated from the gate electrode. According to the embodiment of the invention, the gate oxide layer can be protected, the reliability of the device is improved, the reverse recovery speed can be improved, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor power device. Background Art

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a metal-oxide-semiconductor field-effect transistor, among which silicon carbide MOSFET is more widely used than silicon-based devices with the same voltage resistance level due to its high voltage resistance and low on-resistance. However, compared with silicon, silicon carbide MOSFET has a higher critical breakdown electric field, so the electric field strength of the gate oxide layer in silicon carbide MOSFET is also very high, especially when the device is converted from planar type to trench type, the reliability problem caused by the high field strength of the gate oxide layer increases sharply. Summary of the invention

[0003] Therefore, in order to overcome at least some of the defects and shortcomings in the prior art, an embodiment of the present invention provides a semiconductor power device that can protect the gate oxide layer, improve device reliability, increase reverse recovery speed, and reduce switching losses.

[0004] An embodiment of the present invention provides a semiconductor power device, comprising: a substrate; an epitaxial layer, arranged on the substrate, a concave groove is formed on the side of the epitaxial layer away from the top surface of the substrate; the epitaxial layer comprises: a well region, arranged on one side of the groove; a source region, arranged on the side of the well region facing the top surface of the epitaxial layer; a first shielding region, located on the side of the source region and the well region away from the groove; a second shielding region, located on the side of the groove away from the source region and the well region; a third shielding region, located on the side of the second shielding region away from the source region and the well region; the first shielding region, the second shielding region and the third shielding region are arranged at intervals from each other; the epitaxial layer also comprises a first sub-region located between the second shielding region and the third shielding region; a gate electrode, arranged in the groove; a gate oxide layer, arranged in the groove and isolated between the gate electrode and the epitaxial layer; a Schottky metal, arranged on the top surface of the epitaxial layer and connected to the second shielding region, the first sub-region and the third shielding region respectively; the Schottky metal is insulated from the gate electrode.

[0005] In some embodiments, the Schottky metal includes a main portion and an extension portion, the main portion covers the top surface of the epitaxial layer and is respectively connected to the second shielding region, the first sub-region and the third shielding region, and the extension portion extends from one end of the main portion close to the groove into the groove along the depth direction of the groove; the extension portion is insulated from the gate electrode by the gate oxide layer, and the side of the extension portion facing away from the gate electrode is connected to the second shielding region; the end of the second shielding region close to the substrate also extends to the bottom end of the extension portion and is connected to the bottom end of the extension portion.

[0006] In some embodiments, the gate oxide layer includes a first sublayer located between the gate electrode and the source region and the well region and a second sublayer located between the gate electrode and the extension, and a thickness of the second sublayer is greater than a thickness of the first sublayer.

[0007] In some embodiments, a distance from one end of the second shielding region close to the substrate to the substrate is smaller than a distance from the bottom of the trench to the substrate.

[0008] In some embodiments, the second shielding region extends from one end close to the substrate to the bottom of the trench toward the side of the substrate; and the minimum distance between the second shielding region and the first shielding region is smaller than the minimum distance between the side of the gate electrode away from the first shielding region and the first shielding region.

[0009] In some embodiments, a minimum distance between the second shielding region and the first shielding region is smaller than a minimum distance between the trench and the first shielding region.

[0010] In some embodiments, the sum of the width of the second shielding region on the side of the trench facing away from the source region and the well region and the width of the third shielding region is the first width, the width of the first sub-region is the second width, and the ratio of the first width to the second width is 0.7 to 0.8.

[0011] In some embodiments, an ohmic contact layer is further included, and the ohmic contact layer is disposed between the Schottky metal and the epitaxial layer.

[0012] In some embodiments, the Schottky metal is titanium or an alloy of titanium.

[0013] In some embodiments, a source metal is further included, wherein the source metal is disposed on a side of the epitaxial layer away from the substrate, and the source metal is respectively connected to the Schottky metal, the source region and the first shielding region; and the gate electrode is insulated from the source metal.

[0014] The above-mentioned embodiments of the present invention have at least one or more of the following beneficial effects: by setting shielding areas (including the first shielding area, the second shielding area and the third shielding area) on both sides of the groove, the distribution of the electric field lines can be changed when the semiconductor power device is powered on, so that the gate oxide layer below the gate electrode can be protected and the reliability can be improved. The gd capacitance (capacitance between the gate and the drain) of the device can be reduced, the switching speed of the device can be increased, and the switching loss can be reduced. In addition, Schottky metal is set to be connected to the second shielding area, the first sub-area and the third shielding area respectively, and a Schottky diode structure can be formed on one side of the groove, and the region in the epitaxial layer is fully utilized while the Schottky diode is integrated in the trench MOSFET device, so that a faster reverse recovery speed can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] Figure 1 A schematic structural diagram of a semiconductor power device provided by an embodiment of the present invention.

[0017] Figure 2 A schematic diagram of a structure obtained in a step in a process for preparing a semiconductor power device provided in an embodiment of the present invention.

[0018] Figure 3 for Figure 2 Schematic representation of the resulting structure one step later.

[0019] Figure 4 for Figure 3 Schematic representation of the resulting structure one step later.

[0020] Figure 5 for Figure 4 Schematic representation of the resulting structure one step later.

[0021] Figure 6 for Figure 5 Schematic representation of the resulting structure one step later.

[0022] Figure 7 for Figure 6 Schematic representation of the resulting structure one step later.

[0023] Figure 8 for Figure 7 Schematic representation of the resulting structure one step later.

[0024] Fig. 9 for Figure 8 Schematic representation of the resulting structure one step later.

[0025] Fig.10 for Fig. 9 Schematic representation of the resulting structure one step later.

[0026] Fig.11 for Fig.10 Schematic representation of the resulting structure one step later.

[0027] Fig.12 for Fig.11 Schematic representation of the resulting structure one step later.

[0028] Fig.13 A schematic structural diagram of a semiconductor power device provided in another embodiment of the present invention.

[0029] [Description of Reference Numerals]

[0030] 10. substrate; 20. epitaxial layer; 21. drift region; 22. trench; 23. well region; 24. source region; 25. first shielding region; 26. second shielding region; 27. third shielding region; 28. first sub-region; 30. gate electrode; 40. gate oxide layer; 41. first sub-layer; 42. second sub-layer; 50. Schottky metal; 51. main body; 52. extension; 60. source metal; 70. field oxide layer; 80. ohmic contact layer; 20a. epitaxial layer material; 26a. first injection region; 30a. gate electrode material; 40a. first oxide layer material; 40b. second oxide layer material; 70a. third oxide layer material. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0035] like Figure 1 As shown, an embodiment of the present invention provides a semiconductor power device, specifically a trench MOSFET device. The semiconductor power device provided by this embodiment includes a substrate 10 , an epitaxial layer 20 , a gate electrode 30 , a gate oxide layer 40 and a Schottky metal 50 .

[0036] The epitaxial layer 20 is arranged on the substrate 10, and a concave groove 22 is formed on the side of the top surface of the epitaxial layer 20 away from the substrate 10. The epitaxial layer 20 includes a well region 23, a source region 24, a first shielding region 25, a second shielding region 26, a third shielding region 27 and a first sub-region 28. The well region 23 is arranged on one side of the groove 22. The source region 24 is arranged on the side of the well region 23 facing the top surface of the epitaxial layer 20. The first shielding region 25 is located on the side of the source region 24 and the well region 23 away from the groove 22. The second shielding region 26 is located on the side of the groove 22 away from the source region 24 and the well region 23. The third shielding region 27 is located on the side of the second shielding region 26 away from the source region 24 and the well region 23. The first shielding region 25, the second shielding region 26 and the third shielding region 27 are arranged at intervals from each other. The first sub-region 28 is located in the first sub-region 28 between the second shielding region 26 and the third shielding region 27.

[0037] The gate electrode 30 is disposed in the trench 22 . The gate oxide layer 40 is disposed in the trench 22 and isolated between the gate electrode 30 and the epitaxial layer 20 .

[0038] The Schottky metal 50 is disposed on the top surface of the epitaxial layer 20 and is respectively connected to the second shielding region 26, the first sub-region 28, and the third shielding region 27. The Schottky metal 50 is insulated from the gate electrode 30.

[0039] The semiconductor power device provided in this embodiment is specifically a silicon carbide MOSFET device. The substrate 10 is a silicon carbide substrate. The epitaxial layer 20 also includes a drift region 21, and the well region 23, the source region 24, the first shielding region 25, the second shielding region 26 and the third shielding region 27 are all ion implantation regions obtained by ion implantation in the bulk material of the epitaxial layer 20. The first sub-region 28 has the same material and doping type as the drift region 21. The semiconductor power device of this embodiment can be divided into an N-type field effect transistor or a P-type field effect transistor according to whether the doping type of the drift region 21 is N-type doping or P-type doping. For example, if the drift region 21 is N-type doped, the semiconductor power device is an N-type field effect transistor. When the drift region 21 is N-type doped, the source region 24 is also N-type doped, and the well region 23 is P-type doped. When the drift region 21 is P-type doped, the source region 24 is also P-type doped, and the well region 23 is N-type doped. Specifically in this embodiment, the drift region 21 is N-type doped, the source region 24 is an N+ (N-type heavily doped) injection region, the well region 23 is a P- (P-type lightly doped) injection region, and the first shielding region 25, the second shielding region 26 and the third shielding region 27 are P+ (P-type heavily doped) injection regions.

[0040] The gate electrode 30 is, for example, a polysilicon (poly) layer, and the gate oxide layer 40 can be a silicon oxide material. The Schottky metal 50 can be titanium or a titanium alloy. The Schottky metal 50 and the gate electrode 30 can be insulated by the gate oxide layer 40, or other insulating materials can be provided to achieve the insulation effect. A drain is provided on the side of the bottom surface of the substrate 10 away from the epitaxial layer 20, for example, and the electrical properties of the drain correspond to the electrical properties of the drift region 21. When the drift region 21 is N-type doped, the drain is an N electrode.

[0041] In this embodiment, by respectively setting the first shielding area 25, the second shielding area 26 and the third shielding area 27, a depletion area can be formed between the shielding areas (including the first shielding area 25, the second shielding area 26 and the third shielding area 27) on both sides of the groove 22 when the reverse bias is depleted, thereby changing the distribution of the electric field line when the semiconductor power device is powered on, so that the highest electric field will not reach the bottom of the gate oxide layer 40, and the gate oxide layer 40 below the gate electrode 30 can be protected, thereby improving reliability. In addition, the gd capacitance (capacitance between the gate and the drain) of the device can be reduced, the switching speed of the device can be improved, and the switching loss can be reduced. In addition, the Schottky metal 50 is respectively connected to the second shielding area 26, the first sub-area 28 and the third shielding area 27, and a JBS (Junction Barrier Schottky) type Schottky diode structure can be formed on one side of the groove 22, and the region in the epitaxial layer 20 located on the side of the groove 22 away from the well area 23 and the source area 24 is fully utilized. At the same time, the Schottky diode is integrated in the trench MOSFET device, which can have a faster reverse recovery speed. In this embodiment, the pn combined Schottky junctions appear alternately below the Schottky metal 50. When reverse biased, the depletion regions of the pn junctions on both sides of the Schottky contact portion expand in the N-type epitaxial layer and form a pinch-off barrier. This barrier layer can shield the high electric field, reduce the electric field strength at the metal-semiconductor interface, and suppress the barrier lowering effect and tunneling leakage current caused by the high electric field.

[0042] In some embodiments, the present embodiment further includes a source metal 60, which is disposed on a side of the epitaxial layer 20 away from the substrate 10, and the source metal 60 is respectively connected to the Schottky metal 50, the source region 24 and the first shielding region 25. The gate electrode 30 is insulated from the source metal 60. The source metal 60 may be, for example, an aluminum alloy material. Figure 1 As shown in the figure, a field oxide layer 70 is also provided between the source metal 60 and the gate electrode 30, and the field oxide layer 70 can be made of the same material as the gate oxide layer 40. In some embodiments, the field oxide layer 70 and the gate oxide layer 40 can be combined to realize the insulation between the Schottky metal 50 and the gate electrode 30 to prevent GS (source and gate) leakage. The field oxide layer 70 has an opening located on the Schottky metal 50, and the source metal 60 is connected to the Schottky metal 50 through the opening. The width of the opening can be equal to the width between the second shielding area 26 and the third shielding area 27.

[0043] In some embodiments, the Schottky metal 50 includes a main body 51 and an extension 52, wherein the main body 51 covers the top surface of the epitaxial layer 20 and is respectively connected to the second shielding region 26, the first sub-region 28, and the third shielding region 27. The extension 52 extends from one end of the main body 51 close to the groove 22 along the depth direction of the groove 22 into the groove 22. The extension 52 is insulated from the gate electrode 30 by the gate oxide layer 40, and the side of the extension 52 facing away from the gate electrode 30 is connected to the second shielding region 26. The end of the second shielding region 26 close to the substrate 10 also extends to the bottom end of the extension 52 and is connected to the bottom end of the extension 52. In this embodiment, by extending the extension 52 of the Schottky metal 50 into the groove, the gd capacitance can be reduced, and the leakage current can be further reduced. Among them, one end of the second shielding area 26 close to the substrate 10 extends to the bottom end of the extension part 52 and is connected to the bottom end of the extension part 52, that is, the second shielding area 26 also includes a part extending between the extension part 52 and the drift area 21, which can increase the contact area between the Schottky metal 50 and the second shielding area 26 while preventing leakage.

[0044] In some embodiments, the gate oxide layer 40 includes a first sublayer 41 located between the gate electrode 30 and the source region 24 and the well region 23, and a second sublayer 42 located between the gate electrode 30 and the extension 52, and the thickness of the second sublayer 42 is greater than the thickness of the first sublayer 41. For example, the thickness of the first sublayer 41 is 0.04 to 0.06 microns, and the thickness of the second sublayer 42 is 0.5 to 0.7 microns. Specifically, the thickness of the first sublayer 41 is 0.05 microns, and the thickness of the second sublayer is 0.5 microns. That is, the first sublayer 41 is thinner and the second sublayer 42 is thicker. That is, the gate oxide between the gate electrode 30 and the well region 23 is thinner, which can ensure a lower turn-on voltage; the gate oxide between the gate electrode 30 and the Schottky metal 50 is thicker, which can better prevent leakage.

[0045] In some embodiments, the distance from one end of the second shielding region 26 close to the substrate 10 to the substrate 10 is less than the distance from the bottom of the groove 22 to the substrate 10. That is, the bottom of the second shielding region 26 is lower than the bottom of the groove 22, which can better ensure that a depletion region is formed between the second shielding region 26 and the first shielding region 25 to protect the gate oxide layer 40. The bottom of the first shielding region 25 is, for example, flush with the bottom of the second shielding region 26, that is, the distance between the bottom of the first shielding region 25 and the substrate 10 is equal to the distance between the second shielding region 26 and the substrate 10. In some embodiments, the bottom of the third shielding region 27 is, for example, flush with the bottom of the first shielding region 25 (and / or the second shielding region 26), that is, the distance between the bottom of the third shielding region 27 and the substrate 10 is equal to the distance between the first shielding region 25 (and / or the second shielding region 26) and the substrate 10.

[0046] In some embodiments, the end of the second shielding region 26 close to the substrate 10 extends to the bottom of the trench 22 and faces the side of the substrate 10. And the minimum distance between the second shielding region 26 and the first shielding region 25 is less than the minimum distance between the side of the gate electrode 30 away from the first shielding region 25 and the first shielding region 25. Figure 1 As shown in the figure, the minimum distance between the second shielding area 26 and the first shielding area 25 is the distance between the rightmost edge of the second shielding area 26 and the leftmost edge of the first shielding area 25, and the maximum distance between the gate electrode 30 and the first shielding area 25 is the distance between the leftmost edge of the gate electrode 30 and the leftmost edge of the first shielding area 25. That is, the second shielding area 26 at least extends to the bottom of the gate electrode 30, which can improve the protection effect on the bottom of the gate oxide layer 40.

[0047] In some embodiments, the minimum distance between the second shielding region 26 and the first shielding region 25 is smaller than the minimum distance between the trench 22 and the first shielding region 25. Figure 1 In the orientation shown in FIG. 1 , that is, the distance from the rightmost edge of the second shielding area 26 to the leftmost edge of the first shielding area 25 is less than the distance from the rightmost edge of the groove 22 to the leftmost edge of the first shielding area 25. That is, the portion of the second shielding area 26 extending to the bottom of the groove 22 does not exceed the side of the groove 22 close to the first shielding area 25, so that the second shielding area 26 and the first shielding area 25 maintain a suitable distance to prevent the problem of excessive current density caused by the distance between the two being too close.

[0048] In some embodiments, the sum of the width of the second shielding region 26 located on the side of the trench 22 facing away from the source region 24 and the well region 23 and the width of the third shielding region 27 is the first width, the width of the first sub-region 28 is the second width, and the ratio of the first width to the second width is 0.7 to 0.8. The width of the second shielding region 26 located on the side of the trench 22 facing away from the source region 24 and the well region 23 is as follows: Figure 1 As shown in D1, the width of the third shielding area 27 is as follows Figure 1 As shown in D2, the first width is the sum of D1 and D2. The width of the first sub-area 28 (i.e., the second width, i.e., the spacing distance between the second shielding area 26 and the third shielding area 27) is as shown in Figure 1 As shown in D3. That is, (D1+D2) / D3=0.7-0.8. In some specific embodiments, the ratio of the first width to the second width is 3:4. The range of the ratio of the first width to the second width can ensure a better protection effect on the gate oxide layer 40 while ensuring that the function of the formed Schottky diode is better, thereby obtaining suitable comprehensive performance.

[0049] In some embodiments, reference Fig.13The power semiconductor device provided in this embodiment further includes an ohmic contact layer 80, which is disposed between the Schottky metal 50 and the epitaxial layer 20. The ohmic contact layer 80 may be made of nickel or a nickel alloy to achieve good conduction between the Schottky metal 50 and the second shielding region 26, the first sub-region 28, and the third shielding region 27.

[0050] The semiconductor power device provided by the above embodiment of the present invention can be manufactured through the following process.

[0051] Step S1: growing an epitaxial layer material 20a on the substrate 10. After step S1, Figure 2 The structure shown.

[0052] Step S2: perform ion implantation on the epitaxial layer material 20a to form a well region 23, a source region 24, a first shielding region 25, a first implantation region 26a and a third shielding region 27. After step S2 is completed, the following is obtained: Figure 3 The structure shown.

[0053] Step S3: A trench 22 is formed on the top of the epitaxial material layer 20a. The first implantation region 26a located in the trench 22 is removed to form a second shielding region 26. The structure obtained in step S3 can be referred to Figure 4 As shown, an epitaxial layer 20 having trenches 22 is obtained.

[0054] Step S4: forming a first oxide layer material 40a in the trench 22. Figure 5 As shown, the first oxide layer material 40 a covers the sidewalls and bottom wall of the trench 22 .

[0055] Step S5: forming a gate electrode material 30a on the first oxide layer material 40a in the trench 22. Figure 6 The gate electrode material 30 a and the first oxide layer material 40 a are shown filling the trench 22 .

[0056] Step S6: remove the first oxide layer material 40a and the gate electrode material 30a away from the source region 24 and the well region 23, and the remaining portion of the gate electrode material 30a forms the gate electrode 30. The structure obtained in step S6 can refer to Figure 7 As shown, a separation space is formed between the gate electrode 30 and the second shielding region 26 .

[0057] Step S7: forming a second oxide layer material 40b. Figure 8 As shown, the second oxide layer material 40 b fills between the gate electrode 30 and the second shielding region 26 , and covers the top surface of the epitaxial layer 20 .

[0058] Step S8: removing part of the second oxide layer material 40b. Fig. 9, so that the second shielding region 26, the first sub-region 28 and the third shielding region 27 are exposed outside the second oxide layer material 40a away from the surface of the substrate 10, and the second oxide layer material 40b is retained to cover the portion of the side of the gate electrode 30 facing away from the source region 24 and the well region 23 and the portion covering the top of the gate electrode 30; and a spacing space is formed between the second shielding region 26 facing the side of the gate electrode 30 and the second oxide layer material 40b.

[0059] Step S9: forming a Schottky metal 50. Fig.10 , so that the Schottky metal 50 covers the surface of the second shielding region 26 , the first sub-region 28 and the third shielding region 27 away from the substrate 10 , and extends to the side of the second shielding region 26 facing the gate electrode 30 .

[0060] Step S10: forming a third oxide layer material 70a. Fig.11 The third oxide layer material 70 a covers the surface of the Schottky metal 50 away from the substrate 10 and covers the remaining portion of the second oxide layer material 40 a .

[0061] Step S11: removing part of the third oxide layer material 70a to obtain the field oxide layer 70. Fig.12 The field oxide layer 70 exposes a portion of the surface of the Schottky metal 50 and a portion of the surface of the source region 24 and the first shielding region 25 .

[0062] Step S12: forming a source metal 60. Figure 1 , so that the source metal 60 is connected to the Schottky metal 50 , the source region 24 and the first shielding region 25 respectively.

[0063] Of course, the above steps are only a specific way to obtain a semiconductor power device implemented in the present invention, and this embodiment is not limited thereto.

[0064] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A semiconductor power device, characterized in that: include: A substrate (10); An epitaxial layer (20) is arranged on the substrate (10), and a concave groove (22) is formed on a side of the epitaxial layer (20) away from the top surface of the substrate (10); the epitaxial layer (20) comprises: a well region (23) arranged on one side of the groove (22); A source region (24) is arranged on a side of the well region (23) facing the top surface of the epitaxial layer (20); a first shielding region (25) is located on a side of the source region (24) and the well region (23) away from the groove (22); a second shielding region (26) is located on a side of the groove (22) away from the source region (24) and the well region (23); a third shielding region (27) is located on a side of the second shielding region (26) away from the source region (24) and the well region (23); the first shielding region (25), the second shielding region (26) and the third shielding region (27) are arranged at intervals from each other; the epitaxial layer (20) further comprises a first sub-region (28) located between the second shielding region (26) and the third shielding region (27); A gate electrode (30) is disposed in the groove (22); A gate oxide layer (40) is disposed in the trench (22) and isolated between the gate electrode (30) and the epitaxial layer (20); A Schottky metal (50) is arranged on the top surface of the epitaxial layer (20) and is respectively connected to the second shielding region (26), the first sub-region (28) and the third shielding region (27); the Schottky metal (50) is insulated from the gate electrode (30).

2. The semiconductor power device according to claim 1, characterized in that: The Schottky metal (50) comprises a main body (51) and an extension (52), wherein the main body (51) covers the top surface of the epitaxial layer (20) and is respectively connected to the second shielding region (26), the first sub-region (28) and the third shielding region (27), and the extension (52) extends from one end of the main body (51) close to the groove (22) along the depth direction of the groove (22) into the groove (22); the extension (52) is insulated from the gate electrode (30) by the gate oxide layer (40), and the side of the extension (52) facing away from the gate electrode (30) is connected to the second shielding region (26); the end of the second shielding region (26) close to the substrate (10) also extends to the bottom end of the extension (52) and is connected to the bottom end of the extension (52).

3. The semiconductor power device according to claim 2, characterized in that: The gate oxide layer (40) comprises a first sublayer (41) located between the gate electrode (30) and the source region (24) and the well region (23), and a second sublayer (42) located between the gate electrode (30) and the extension portion (52), wherein the thickness of the second sublayer (42) is greater than the thickness of the first sublayer (41).

4. The semiconductor power device according to claim 1, characterized in that: The distance between the end of the second shielding region (26) close to the substrate (10) and the substrate (10) is smaller than the distance between the bottom of the groove (22) and the substrate (10).

5. The semiconductor power device according to claim 4, characterized in that: One end of the second shielding region (26) close to the substrate (10) extends to the bottom of the groove (22) and faces the side of the substrate (10); and the minimum distance between the second shielding region (26) and the first shielding region (25) is smaller than the minimum distance between the side of the gate electrode (30) away from the first shielding region (25) and the first shielding region (25).

6. The semiconductor power device according to claim 5, characterized in that: The minimum distance between the second shielding area (26) and the first shielding area (25) is smaller than the minimum distance between the groove (22) and the first shielding area (25).

7. The semiconductor power device according to claim 1, characterized in that: The sum of the width of the second shielding region (26) located on the side of the trench (22) facing away from the source region (24) and the well region (23) and the width of the third shielding region (27) is the first width, the width of the first sub-region (28) is the second width, and the ratio of the first width to the second width is 0.7 to 0.

8.

8. The semiconductor power device according to claim 1, characterized in that: It also includes an ohmic contact layer (80), wherein the ohmic contact layer (80) is disposed between the Schottky metal (50) and the epitaxial layer (20).

9. The semiconductor power device according to claim 1, characterized in that: The Schottky metal (50) is titanium or a titanium alloy.

10. The semiconductor power device according to claim 1, characterized in that: It also includes a source metal (60), which is arranged on a side of the epitaxial layer (20) away from the substrate (10), and the source metal (60) is respectively connected to the Schottky metal (50), the source region (24) and the first shielding region (25); the gate electrode (30) is insulated from the source metal (60).

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