IGBT with improved turn-off loss and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides an IGBT with improved turn-off loss, a preparation method thereof, and a chip thereof. A drift region including a P-type drift region and an N-type drift region is provided, and a vertical portion of the P-type drift region is provided to be formed in parallel with the N-type drift region on an N-type buffer layer, and a horizontal portion of the P-type drift region is located on the upper side and / or the lower side of the N-type drift region. A carrier storage layer is formed on the drift region, so that the structure formed by the P-type drift region and the N-type drift region can reduce the effective doping concentration of the device, have a faster electric field expansion speed, and thus discharge holes faster, thereby reducing the turn-off loss of the device, and solving the problem that the IGBT device will affect the turn-off speed, turn-off loss, and on-state voltage when extracting holes.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to an IGBT with improved turn-off loss, a preparation method thereof, and a chip. Background Art

[0002] Insulate-Gate Bipolar Transistor (IGBT) is a gate-controlled bipolar device. Due to the presence of minority carriers, a large number of holes are injected when it is turned on. Therefore, it has low operating loss, large current and high voltage resistance. It is widely used in medium-frequency and high-power fields such as electric vehicles and household appliances.

[0003] However, when the IGBT is turned off, it needs to extract a large number of holes generated when it is turned on. The hole extraction path and extraction speed will greatly affect the device's turn-off speed and turn-off loss, which will inevitably affect the device's on-voltage. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide an IGBT with improved turn-off loss, a preparation method thereof, and a chip, aiming to reduce the impact of the IGBT device on the turn-off speed, turn-off loss, and on-state voltage during hole extraction.

[0005] A first aspect of an embodiment of the present application provides an IGBT with improved turn-off loss, comprising:

[0006] A P-type substrate and an N-type buffer layer, wherein the N-type buffer layer is formed on the front side of the P-type substrate;

[0007] A drift region, the drift region comprising a P-type drift region and an N-type drift region, the vertical portion of the P-type drift region being formed on the N-type buffer layer in parallel with the N-type drift region, and the horizontal portion of the P-type drift region being located on the upper side and / or the lower side of the N-type drift region;

[0008] A carrier storage layer formed on the drift region;

[0009] A P-type base region, formed on the carrier storage layer;

[0010] An N-type doping region and a P-type doping region are formed on the P-type base region;

[0011] A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on a vertical portion of the P-type drift region, and the gate dielectric layer wraps the gate polysilicon layer;

[0012] A collector and an emitter, wherein the emitter contacts the N-type doping region and the P-type doping region, and the collector is formed on the back side of the P-type substrate.

[0013] In some embodiments, a partial area of ​​the N-type drift region is disposed opposite to a partial area of ​​the gate polysilicon layer.

[0014] In some embodiments, the width of the N-type drift region gradually decreases in a direction from the collector to the emitter.

[0015] In some embodiments, the width of the vertical portion of the P-type drift region gradually decreases in a direction from the gate polysilicon layer to the collector.

[0016] In some embodiments, the thickness of the P-type drift region is at least twice the thickness of the N-type drift region.

[0017] In some embodiments, a doping concentration of N-type doping ions in the N-type drift region is less than a doping concentration of N-type doping ions in the N-type buffer layer.

[0018] In some embodiments, when the horizontal portion of the P-type drift region is located on the upper side of the N-type drift region, the horizontal portion of the P-type drift region contacts the carrier storage layer, a PN junction is formed between the carrier storage layer and the P-type base region, a PN junction is formed between the carrier storage layer and the P-type drift region, and the doping concentration of P-type doped ions in the P-type drift region is less than the doping concentration of P-type doped ions in the P-type base region.

[0019] In some embodiments, the doping concentration of P-type doping ions in the P-type doping region is greater than the doping concentration of P-type doping ions in the P-type base region, and a PN junction is formed between the P-type base region and the N-type doping region.

[0020] A second aspect of the embodiment of the present application further provides a method for preparing an IGBT with improved turn-off loss, the method comprising:

[0021] A drift region is formed by epitaxy on the front side of the N-type substrate; the drift region includes a P-type drift region and an N-type drift region, a vertical portion of the P-type drift region is formed on the N-type buffer layer in parallel with the N-type drift region, and a horizontal portion of the P-type drift region is located on the upper side and / or the lower side of the N-type drift region;

[0022] forming a gate dielectric layer and a gate polysilicon layer on the vertical portion of the P-type drift region, wherein the gate dielectric layer wraps the gate polysilicon layer;

[0023] forming a carrier storage layer in an area adjacent to the gate dielectric layer; wherein the carrier storage layer is formed on the drift region;

[0024] forming a P-type base region on the carrier storage layer;

[0025] forming an N-type doping region and a P-type doping region on the P-type base region;

[0026] Implanting N-type doping ions on the back side of the N-type substrate to form an N-type buffer layer, and implanting P-type doping ions on the back side of the N-type buffer layer to form a P-type substrate;

[0027] An emitter electrode contacting the N-type doping region and the P-type doping region is formed, and a collector electrode is formed on the back side of the P-type substrate.

[0028] A third aspect of the embodiments of the present application further provides a chip, comprising an IGBT with improved turn-off loss as described in any of the above embodiments.

[0029] The beneficial effects of the embodiments of the present application are as follows: by setting the drift region to include a P-type drift region and an N-type drift region, the vertical portion of the P-type drift region is formed on the N-type buffer layer in parallel with the N-type drift region, the horizontal portion of the P-type drift region is located on the upper side and / or the lower side of the N-type drift region, and the carrier storage layer is formed on the drift region, so that the structure formed by the P-type drift region and the N-type drift region can reduce the effective doping concentration of the device, so that the device has a faster electric field expansion speed, and thus faster discharge of holes, reducing the turn-off loss of the device, and solving the problem that the IGBT device will affect the turn-off speed, turn-off loss and on-state voltage when extracting holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a A first structural schematic diagram of an IGBT with improved turn-off loss provided in an embodiment of the present application;

[0031] Figure 1b A second structural schematic diagram of an IGBT with improved turn-off loss provided in an embodiment of the present application;

[0032] Figure 1c A third structural schematic diagram of an IGBT with improved turn-off loss provided in an embodiment of the present application;

[0033] Figure 1d A fourth structural schematic diagram of an IGBT with improved turn-off loss provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a comparative structure provided in an embodiment of the present application;

[0035] Figure 3 A comparison diagram of device parameters of a conventional structure, a comparative structure, and an improved structure provided by an embodiment of the present application;

[0036] Figure 4 A comparison chart of output characteristic curve simulation results of a conventional structure, a comparative structure, and an improved structure provided in an embodiment of the present application;

[0037] Figure 5 A comparison diagram of transfer characteristic curve simulation results of a conventional structure, a comparative structure, and an improved structure provided in an embodiment of the present application;

[0038] Figure 6 A comparison chart of simulation results of the hole density of the comparative structure under different voltages provided in the embodiment of the present application and the hole density of the improved structure provided in the embodiment of the present application;

[0039] Figure 7 A comparison diagram of simulation results of electric field distribution of a conventional structure, a comparative structure, and an improved structure provided in an embodiment of the present application;

[0040] Figure 8 A comparison chart of switching characteristic curve simulation results of a conventional structure, a comparative structure, and an improved structure provided in an embodiment of the present application;

[0041] Fig. 9 It is a schematic flow chart of a method for preparing an IGBT with improved turn-off loss provided in an embodiment of the present application;

[0042] Fig.10 It is a schematic diagram of forming a vertical portion of an N-type drift region and a P-type drift region on an N-type substrate provided by an embodiment of the present application;

[0043] Fig.11 is a schematic diagram of a horizontal portion of a P-type drift region formed according to an embodiment of the present application;

[0044] Fig.12 It is a schematic diagram of forming a gate dielectric layer and a gate polysilicon layer provided in an embodiment of the present application;

[0045] Fig.13 is a schematic diagram of forming a carrier storage layer provided in an embodiment of the present application;

[0046] Fig.14 It is a schematic diagram of forming a P-type base region, an N-type doped region, a P-type doped region, an N-type buffer layer and a P-type substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0049] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0051] IGBT is a bipolar device that generates a large number of holes when it is turned on, which need to be extracted when it is turned off. The hole extraction path and extraction speed will greatly affect the turn-off speed and turn-off loss, which will inevitably affect the on-state voltage of the device.

[0052] In order to solve the above technical problems, the embodiment of the present application provides an IGBT with improved turn-off loss, see Figure 1a , Figure 1b and Figure 1c As shown, the IGBT with improved turn-off loss in this embodiment includes: a P-type substrate 110, an N-type buffer layer 120, a drift region 13, a carrier storage layer 210, a P-type base region 220, an N-type doped region 230, a P-type doped region 240, a gate dielectric layer 250, a gate polysilicon layer 260, a collector 310 and an emitter 320.

[0053] The drift region 13 includes a P-type drift region 130 and an N-type drift region 140 . The vertical portion of the P-type drift region 130 is formed on the N-type buffer layer 120 in parallel with the N-type drift region 140 , and the horizontal portion of the P-type drift region 130 is located above and / or below the N-type drift region 140 .

[0054] Specifically, Figure 1a , which is a first structural schematic diagram of an IGBT for improving turn-off loss provided by an embodiment of the present application, wherein the horizontal portion of the P-type drift region 130 of the IGBT device is located on the upper side of the N-type drift region 140. Furthermore, when the horizontal portion of the P-type drift region 130 is located on the upper side of the N-type drift region 140, the P-type drift region 130 is in contact with the carrier storage layer.

[0055] like Figure 1b , which is a second structural schematic diagram of an IGBT for improving turn-off loss provided by an embodiment of the present application, wherein the horizontal portion of the P-type drift region 130 of the IGBT device is located below the N-type drift region 140. Furthermore, when the horizontal portion of the P-type drift region 130 is located below the N-type drift region 140, the N-type drift region 140 is in contact with the carrier storage layer.

[0056] like Figure 1c As shown, it is a third structural schematic diagram of an IGBT for improving turn-off loss provided by an embodiment of the present application, in which the horizontal portion of the P-type drift region 130 of the IGBT device is located on the upper side and the lower side of the N-type drift region 140. Moreover, when the horizontal portion of the P-type drift region 130 is located on the upper side and the lower side of the N-type drift region 140, the horizontal portion of the P-type drift region 130 located on the upper side of the N-type drift region 140 contacts the carrier storage layer. The horizontal portion of the P-type drift region 130 located on the lower side of the N-type drift region 140 contacts the N-type buffer layer 120.

[0057] The carrier storage layer 210 in the embodiment of the present application is formed on the drift region (i.e., on the N-type drift region 140, or on the horizontal portion of the P-type drift region 130), the P-type base region 220 is formed on the carrier storage layer 210, the N-type doped region 230 and the P-type doped region 240 are formed on the P-type base region 220, the gate dielectric layer 250 is formed on the vertical portion of the P-type drift region 130, and the gate dielectric layer 250 wraps the gate polysilicon layer 260, the emitter 320 is in contact with the N-type doped region 230 and the P-type doped region 240, and the collector 310 is formed on the back side of the P-type substrate 110.

[0058] In the embodiment of the present application, the drift region structure of the traditional IGBT is improved so that the drift region of the improved IGBT includes not only the N-type drift region 140 but also the P-type drift region 130, and the vertical portion of the P-type drift region 130 is formed on the N-type buffer layer 120 in parallel with the N-type drift region 140, and the horizontal portion of the P-type drift region 130 is located on the upper side and / or the lower side of the N-type drift region 140, so that the structure formed by the P-type drift region 130 and the N-type drift region 140 can reduce the effective doping concentration of the device, which is beneficial to improving the electric field expansion speed of the device, thereby accelerating the discharge of holes, reducing the turn-off loss of the device, reducing the influence of hole extraction of the IGBT device on the turn-off speed, turn-off loss and on-state voltage, improving the turn-off speed and on-state voltage of the IGBT device, and reducing the turn-off loss of the IGBT device.

[0059] In the embodiment of the present application, the carrier storage layer 210 is formed on the drift region 13, which is beneficial to blocking the outflow of holes when the device is turned on, thereby reducing the conduction loss of the device.

[0060] In some embodiments, the N-type ion doping concentration of the carrier storage layer 210 is greater than the N-type ion doping concentration of the N-type drift region 140 .

[0061] In some embodiments, the N-type ion doping concentration of the carrier storage layer 210 is at least 10 times the N-type ion doping concentration of the N-type drift region 140 .

[0062] In some embodiments, the vertical portion where the P-type drift region 130 contacts the N-type drift region 140 in the device forms a super junction structure with the N-type drift region 140, and the distance between the super junction structure and the N-type buffer layer 120 can be set as needed (for example, Figure 1c In the device structure shown, the thickness of the horizontal portion of the P-type drift region 130 located below the N-type drift region 140 can be set as required).

[0063] In the embodiment of the present application, a super junction structure is introduced into the device by setting a P-type drift region 130 and an N-type drift region 140, thereby reducing the effective doping concentration of the device. When the device is turned off, the electric field expansion speed is accelerated, and a voltage-resistant layer is quickly established, thereby increasing the switching speed of the device and reducing the on-state voltage drop of the device.

[0064] In some embodiments, Figure 1a , Figure 1b and Figure 1c As shown, a partial area of ​​the N-type drift region 140 is disposed opposite to a partial area of ​​the gate polysilicon layer 260 .

[0065] like Figure 1a As shown, the N-type drift region 140 is located on one side of the P-type drift region 130, and the gate polysilicon layer 260 is located on the other side of the P-type drift region 130. The sum of the width of the N-type drift region 140 and the width of the gate polysilicon layer 260 is greater than the total width of the P-type drift region 130, so that a partial area of ​​the N-type drift region 140 and a partial area of ​​the gate polysilicon layer 260 are arranged opposite to each other, that is, there is a partial overlap in the projections of the N-type drift region 140 and the gate polysilicon layer 260 in the direction from the collector 310 to the emitter 320.

[0066] In some embodiments, the width of the N-type drift region 140 gradually decreases in a direction from the collector 310 to the emitter 320 .

[0067] For example, the N-type drift region 140 may be in a trapezoidal, triangular or pyramidal structure. The present application does not limit the specific structure of the N-type drift region 140 .

[0068] In some embodiments, the interface between the N-type drift region 140 and the P-type drift region 130 can be a trapezoidal interface, and the N-type drift region 140 is a stepped structure whose width gradually decreases in the direction from the collector 310 to the emitter 320. The shape of the P-type drift region 130 matches the shape of the N-type drift region 140, thereby increasing the interface area between the N-type drift region 140 and the P-type drift region 130, which is beneficial to reducing the effective doping concentration of the device. When the device is turned off, the electric field expansion speed is accelerated, and the voltage-resistant layer is quickly established, thereby improving the switching speed of the device, and the on-state voltage drop of the device can be reduced.

[0069] In some embodiments, Figure 1d As shown, a plurality of P-type doping point regions 131 may be provided at the interface between the N-type drift region 140 and the P-type drift region 130 , and the concentration of the P-type doping ions in the plurality of P-type doping point regions is greater than the doping concentration of the P-type drift region 130 .

[0070] In some embodiments, a plurality of P-type doping point regions at the interface between the N-type drift region 140 and the P-type drift region 130 are arranged in sequence.

[0071] In some embodiments, a plurality of P-type doping point regions at the interface between the N-type drift region 140 and the P-type drift region 130 are evenly spaced.

[0072] In this embodiment, by setting a P-type doping point region with a higher doping concentration at the interface position between the N-type drift region 140 and the P-type drift region 130, it is beneficial to have a faster electric field expansion speed inside the device, and accelerate the discharge of holes, reducing the turn-off loss of the device. In addition, by setting the P-type doping point region, the lateral depletion between the P column and the N column in the lateral direction of the super junction can also reduce the effective doping concentration, increase the expansion speed of the electric field, and accelerate the discharge of holes. The device structure proposed in this application reduces the influence of hole extraction of the IGBT device on the turn-off speed, turn-off loss and on-voltage, improves the turn-off speed and on-voltage of the IGBT device, reduces the turn-off loss of the IGBT device, and solves the technical problems of slow turn-off speed, high turn-off loss and low on-voltage of the IGBT device in the prior art.

[0073] In some embodiments, the width of the vertical portion of the P-type drift region 130 gradually decreases in a direction from the gate polysilicon layer 260 to the collector 310 .

[0074] For example, the P-type drift region 130 layer may be in an inverted trapezoidal, inverted triangular or inverted pyramidal structure. The present application does not limit the specific structure of the P-type drift region 130 .

[0075] In some embodiments, the thickness of the vertical portion of the P-type drift region 130 is at least twice the thickness of the N-type drift region 140 .

[0076] In this embodiment, the drift region structure of the conventional IGBT is improved so that the drift region of the improved IGBT includes a P-type drift region 130 and an N-type drift region 140, and the P-type drift region 130 is an L-type structure, the vertical portion of the P-type drift region 130 and the N-type drift region 140 are formed in parallel on the N-type buffer layer 120, and the horizontal portion of the P-type drift region 130 is located on the N-type drift region 140; the width of the N-type drift region 140 gradually decreases in the direction from the collector 310 to the emitter 320; the P-type drift region 130 is an L-type structure, and the vertical portion of the P-type drift region 130 and the N-type drift region 140 are formed in parallel on the N-type buffer layer 120, and the horizontal portion of the P-type drift region 130 is located on the N-type drift region 140; the width of the N-type drift region 140 gradually decreases in the direction from the collector 310 to the emitter 320; The width of the vertical portion of the gate polysilicon layer 260 gradually decreases in the direction from the gate polysilicon layer 260 to the collector 310; the carrier storage layer 210 is formed on the horizontal portion of the P-type drift region 130 and is arranged opposite to the N-type drift region 140; the P-type base region 220 is formed on the carrier storage layer 210, so that the effective doping concentration of the IGBT device proposed in the present application is lower than that of the comparative structure under the same voltage, and the electric field expansion speed is faster, thereby accelerating the discharge of holes and reducing the turn-off loss of the device. In addition, the lateral depletion between the P column and the N column in the lateral direction of the super junction can also reduce the effective doping concentration, increase the expansion speed of the electric field, and accelerate the discharge of holes. The device structure proposed in the present application reduces the influence of hole extraction of the IGBT device on the turn-off speed, turn-off loss and on-voltage, improves the turn-off speed and on-voltage of the IGBT device, reduces the turn-off loss of the IGBT device, and solves the technical problems of slow turn-off speed, high turn-off loss and low on-voltage of the IGBT device in the prior art.

[0077] In some embodiments, the doping concentration of the N-type doping ions in the N-type drift region 140 is less than the doping concentration of the N-type doping ions in the N-type buffer layer 120 .

[0078] In some embodiments, a PN junction is formed between the carrier storage layer 210 and the P-type base region 220 , and a PN junction is formed between the carrier storage layer 210 and the P-type drift region 130 , and the doping concentration of the P-type doped ions in the P-type drift region 130 is less than the doping concentration of the P-type doped ions in the P-type base region 220 .

[0079] In some embodiments, the doping concentration of the P-type doping ions in the P-type doping region 240 is greater than the doping concentration of the P-type doping ions in the P-type base region 220 , and a PN junction is formed between the P-type base region 220 and the N-type doping region 230 .

[0080] In order to better illustrate the improved structure proposed in the embodiment of the present application (hereinafter referred to as Figure 1a The innovation of the structure shown in the figure is as an example), the embodiment of the present application provides a comparative structure, such as Figure 2The figure shows a schematic diagram of a comparative structure provided in an embodiment of the present application, the comparative structure includes a P-type substrate 110', an N-type buffer layer 120', a P-type drift region 130', an N-type drift region 140', a carrier storage layer 210', a P-type base region 220', an N-type doped region 230', a P-type doped region 240', a gate dielectric layer 250', a gate polysilicon layer 260', a collector 310' and an emitter 320'. The difference between the comparative structure and the conventional structure is that the N-type drift region is changed to a structure of an N-type drift region 140' and a P-type drift region 130', that is, it includes not only an N-type drift region 140', but also a P-type drift region 130' disposed on the N-type drift region 140'. Compared with the improved structure in the embodiment of the present application ( Figure 1a Compared with the structure shown in the figure, the N-type drift region 140' and the P-type drift region 130' in the comparative structure are parallel to each other and stacked on the N-type buffer layer 120'. The P-type drift region 130 in the present application is an L-type structure. The vertical portion of the P-type drift region 130 is formed on the N-type buffer layer 120 in parallel with the N-type drift region 140, and the horizontal portion of the P-type drift region 130 is located on the N-type drift region 140.

[0081] The following is a comparison of the traditional structure (not shown in the figure) and the comparative structure ( Figure 2 The structure shown in the figure) and the improved structure proposed in the embodiment of the present application ( Figure 1a The performance of the structure shown is compared with that of the

[0082] Specific, combined Figure 3 From the parameter diagram in the figure, we can see that compared with the traditional structure, the contrast structure ( Figure 2 Although the structure shown in FIG. 1 improves the turn-off loss, it inevitably affects the conduction voltage drop. The improved structure ( Figure 1a The structure shown in the figure) has the same conduction voltage drop as the traditional structure on the basis of reducing the turn-off loss. It can be seen that the improved structure proposed in this embodiment has a better improvement effect than the comparative structure, and improves the turn-off loss of the device by increasing the hole extraction speed when the device is turned off, without affecting other parameters of the device. Among them, Figure 3 In V CES is the breakdown voltage between collector and emitter, V GEth is the gate threshold voltage, V on is the device on-state voltage, E on is the device conduction loss, E off is the device turn-off loss, V GEis the voltage between the gate and the emitter, ICE is the current between the collector and the emitter, V CE is the voltage between the collector and the emitter, Vgmax is the maximum gate voltage, Rgon is the gate on-resistance, and Rgoff is the gate off-resistance.

[0083] Combination Figure 4 The output characteristic curves in the figure show that the traditional structure, the comparative structure and the improved structure ( Figure 1a When the voltage between the collector 310 and the emitter 320 of the conventional structure, the comparative structure and the improved structure is 15V, the output characteristic curves are consistent when the voltage between the gate and the emitter 320 increases from 0V to 15V. Figure 4 Where Ic is the collector current and Vg is the gate voltage.

[0084] Combination Figure 5 From the transfer characteristic curves in the figure, we can see that the traditional structure, the comparison structure and the improved structure ( Figure 1a When the voltage between the gate and the emitter 320 of the conventional structure, the comparative structure and the improved structure is 15V, when the voltage between the collector 310 and the emitter 320 is increased from 0V to 15V, the transfer characteristic curves of the conventional structure and the improved structure are consistent, while the on-state voltage drop of the comparative structure is significantly increased. Therefore, the improved structure ( Figure 1a Compared with the comparative structure, the structure shown in the figure has better performance, while improving the device turn-off loss, it does not affect other parameters of the device. Figure 5 Where Ic is the current of the collector 310 , and Vc is the voltage of the collector 310 .

[0085] Combination Figure 6 As shown, by comparing the hole density under different voltages, it can be seen that the improved structure ( Figure 1a The structure shown in the figure) can more easily overcome the potential barrier in the structure, generate a large number of holes, and then produce a conductivity modulation effect, making the device conductive. Figure 6 V GE is the voltage between the gate and the emitter, V CE The voltage between the collector and the emitter.

[0086] Combination Figure 7 The electric field distribution shown in FIG. 1 shows that the improved structure ( Figure 1aThe breakdown voltage of the structure shown in the figure is not significantly changed compared with the traditional structure, but the electric field distribution of the improved structure in the implementation of the present application is improved, and the electric field in its drift region is more uniform. The electric field of the N-type drift region 140 of the traditional structure gradually decreases, and when it reaches its depletion region, it is difficult to increase the withstand voltage of the device. In the improved structure in this embodiment, when the thickness of the drift region gradually increases, its electric field tends to be constant, so that the improved structure can withstand a higher withstand voltage. Among them, Figure 7 The abscissa Y in is the thickness of the drift zone.

[0087] Combination Figure 8 As shown in the switching characteristic curve, the improved structure ( Figure 1a Compared with the conventional structure and the comparative structure, the improved structure provided by the embodiment of the present application has a faster electric field expansion speed under the same voltage, can discharge holes faster, reduce turn-off loss, and the lateral depletion between the P column and the N column in the lateral direction of the super junction can also reduce the effective doping concentration, increase the expansion speed of the electric field, and accelerate the discharge of holes. Among them, Figure 8 Where Ic is the collector current and Vc is the collector voltage.

[0088] By the above Figures 3 to 8 It can be seen from the comparison that the improved structure proposed in this embodiment improves the turn-off loss of the device by increasing the hole extraction speed when the device is turned off, compared with the comparative structure and the traditional structure, without affecting other parameters of the device.

[0089] The present application also provides a method for preparing an IGBT with improved turn-off loss, see Fig. 9 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0090] In step S100 , a drift region is formed by epitaxial growth on the front side of an N-type substrate, and the drift region includes a P-type drift region and an N-type drift region.

[0091] In the embodiment of the present application, the vertical portion of the P-type drift region is formed on the N-type buffer layer in parallel with the N-type drift region, and the horizontal portion of the P-type drift region is located on the upper side and / or lower side of the N-type drift region.

[0092] See also Figure 1a , Fig.10 and Fig.11 As shown, when the horizontal portion of the P-type drift region is located on the upper side of the N-type drift region, the N-type drift region 140 can be formed by epitaxially growing on the front side of the N-type substrate, and a partial area of ​​the N-type drift region 140 is etched to fill the P-type doping material to form a vertical portion of the P-type drift region, and then the P-type drift region 130 is continued to be epitaxially grown, so that the P-type drift region 130 is an L-type structure.

[0093] See also Fig.11 As shown, in this embodiment, the vertical portion of the P-type drift region 130 of the L-type structure is parallel to the N-type drift region 140 , and the horizontal portion of the P-type drift region 130 of the L-type structure is located on the upper side of the N-type drift region 140 .

[0094] In one embodiment, the thickness of the vertical portion of the P-type drift region 130 is at least twice the thickness of the N-type drift region 140 .

[0095] See also Fig.10 As shown, one side of the N-type drift region 140 is etched to the N-type substrate to form the P-type drift region 130 , so that the P-type drift region 130 and the N-type drift region 140 are formed on the front side of the N-type substrate.

[0096] In one embodiment, see Fig.10 As shown, the etching width is less than half of the width of the N-type substrate.

[0097] In one embodiment, the N-type substrate and the N-type drift region 140 have the same N-type doping ion doping concentration.

[0098] In step S200 , a gate dielectric layer 250 and a gate polysilicon layer 260 are formed on the vertical portion of the P-type drift region 130 .

[0099] See also Fig.12 As shown, in this embodiment, a gate dielectric material can be first deposited on the vertical portion of the P-type drift region 130, and then a groove can be formed by etching the gate dielectric material, and a gate polysilicon material can be deposited in the groove to form a gate polysilicon layer 260, and then the surface of the gate polysilicon layer 260 can be oxidized to obtain a gate dielectric layer 250 that wraps the gate polysilicon layer 260.

[0100] In step S300 , a carrier storage layer 210 is formed in a region adjacent to the gate dielectric layer 250 .

[0101] See also Fig.13 As shown, in this embodiment, the carrier storage layer 210 can be formed by depositing a single crystal silicon material and performing N-type doping ion implantation on the single crystal silicon material, or by directly depositing N-type silicon material to form the carrier storage layer 210. The carrier storage layer 210 is formed on the drift region 13.

[0102] In some embodiments, the order of step S200 and step S300 can be adjusted as needed. For example, step S300 can be performed first and then step S200.

[0103] In some embodiments, the width of the carrier storage layer 210 is smaller than the width of the N-type drift region 140 .

[0104] In some embodiments, a portion of the N-type drift region 140 is disposed opposite to a portion of the gate polysilicon layer 260 .

[0105] In step S400 , a P-type base region 220 is formed on the carrier storage layer 210 .

[0106] See also Fig.14 As shown, in this embodiment, the width of the P-type base region 220 is the same as the width of the carrier storage layer 210, and the thickness of the P-type base region 220 is the same as the thickness of the carrier storage layer 210. The P-type base region 220 and the carrier storage layer 210 are both in contact with the gate dielectric layer 250.

[0107] In step S500 , an N-type doping region 230 and a P-type doping region 240 are formed on the P-type base region 220 .

[0108] See also Fig.14 As shown, in this embodiment, the width of the N-type doping region 230 is the same as the width of the P-type doping region 240, and the thickness of the N-type doping region 230 is the same as the thickness of the P-type doping region 240. The sum of the width of the N-type doping region 230 and the width of the P-type doping region 240 is equal to the width of the P-type base region 220. The N-type doping region 230 is located between the gate dielectric layer 250 and the P-type doping region 240, and the N-type doping region 230 is in contact with the gate dielectric layer 250.

[0109] In step S600 , N-type dopant ions are implanted on the back side of the N-type substrate to form an N-type buffer layer 120 , and P-type dopant ions are implanted on the back side of the N-type buffer layer 120 to form a P-type substrate 110 .

[0110] See also Fig.14 As shown, in this embodiment, the N-type buffer layer 120 is in contact with the P-type drift region 130 and the N-type drift region 140, and the thickness of the N-type buffer layer 120 is the same as the thickness of the P-type substrate 110, and the sum of the thickness of the N-type buffer layer 120 and the thickness of the P-type substrate 110 is equal to the thickness of the N-type substrate.

[0111] In step S700 , an emitter 320 contacting the N-type doping region 230 and the P-type doping region 240 is formed, and a collector 310 is formed on the back side of the P-type substrate 110 .

[0112] In some embodiments, the doping concentration of the N-type doping ions in the N-type drift region 140 is less than the doping concentration of the N-type doping ions in the N-type buffer layer 120 .

[0113] In some embodiments, a PN junction is formed between the carrier storage layer 210 and the P-type base region 220 , and a PN junction is formed between the carrier storage layer 210 and the P-type drift region 130 , and the doping concentration of the P-type doped ions in the P-type drift region 130 is less than the doping concentration of the P-type doped ions in the P-type base region 220 .

[0114] In some embodiments, the doping concentration of the P-type doping ions in the P-type doping region 240 is greater than the doping concentration of the P-type doping ions in the P-type base region 220 , and a PN junction is formed between the P-type base region 220 and the N-type doping region 230 .

[0115] An embodiment of the present application also provides a chip, comprising an IGBT with improved turn-off loss as in any of the above embodiments.

[0116] In this embodiment, the chip includes a chip substrate, on which one or more IGBTs with improved turn-off loss are arranged. The IGBT with improved turn-off loss can be prepared by the preparation method in any of the above embodiments, or the IGBT with improved turn-off loss in any of the above embodiments can be arranged on the chip substrate.

[0117] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit with the IGBT for improving turn-off loss.

[0118] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0119] The beneficial effects of the embodiments of the present application are as follows: by arranging the vertical portion of the P-type drift region and the N-type drift region to be formed in parallel on the N-type buffer layer, the horizontal portion of the P-type drift region is located on the upper side and / or the lower side of the N-type drift region, and the carrier storage layer is formed on the drift region, so that the structure formed by the P-type drift region and the N-type drift region can reduce the effective doping concentration of the device, so that the device has a faster electric field expansion speed, and thus faster discharge of holes, reducing the turn-off loss of the device, and solving the problem that the IGBT device will affect the turn-off speed, turn-off loss and on-state voltage when extracting holes.

[0120] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0121] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0122] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0124] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An IGBT with improved turn-off loss, characterized in that: include: A P-type substrate and an N-type buffer layer, wherein the N-type buffer layer is formed on the front side of the P-type substrate; A drift region, wherein the drift region includes a P-type drift region and an N-type drift region, the P-type drift region is an L-shaped structure, a vertical portion of the P-type drift region is formed on the N-type buffer layer in parallel with the N-type drift region, and a horizontal portion of the P-type drift region is located at a lower side of the N-type drift region; A carrier storage layer formed on the drift region; A P-type base region, formed on the carrier storage layer; An N-type doping region and a P-type doping region are formed on the P-type base region; A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on a vertical portion of the P-type drift region, and the gate dielectric layer wraps the gate polysilicon layer; A collector and an emitter, the emitter is in contact with the N-type doped region and the P-type doped region, the collector is formed on the back side of the P-type substrate; the N-type drift region is located on one side of the P-type drift region, the gate polysilicon layer is located on the other side of the P-type drift region, the sum of the width of the N-type drift region and the width of the gate polysilicon layer is greater than the total width of the P-type drift region; the projections of the N-type drift region and the gate polysilicon layer in the direction from the collector to the emitter partially overlap.

2. The IGBT with improved turn-off loss according to claim 1, characterized in that: A partial area of ​​the N-type drift region is arranged opposite to a partial area of ​​the gate polysilicon layer.

3. The IGBT with improved turn-off loss according to claim 1, characterized in that: The width of the N-type drift region gradually decreases in a direction from the collector to the emitter.

4. The IGBT with improved turn-off loss according to claim 3, characterized in that: The width of the vertical portion of the P-type drift region gradually decreases in a direction from the gate polysilicon layer to the collector.

5. The IGBT with improved turn-off loss according to claim 1, characterized in that: The thickness of the vertical portion of the P-type drift region is at least twice the thickness of the N-type drift region.

6. The IGBT with improved turn-off loss according to claim 1, characterized in that: The doping concentration of N-type doping ions in the N-type drift region is lower than the doping concentration of N-type doping ions in the N-type buffer layer.

7. The IGBT with improved turn-off loss according to any one of claims 1 to 6, characterized in that: When the horizontal portion of the P-type drift region is located on the upper side of the N-type drift region, the horizontal portion of the P-type drift region contacts the carrier storage layer, a PN junction is formed between the carrier storage layer and the P-type base region, a PN junction is formed between the carrier storage layer and the P-type drift region, and the doping concentration of P-type doped ions in the P-type drift region is less than the doping concentration of P-type doped ions in the P-type base region.

8. The IGBT with improved turn-off loss according to any one of claims 1 to 6, characterized in that: The doping concentration of P-type doping ions in the P-type doping region is greater than the doping concentration of P-type doping ions in the P-type base region, and a PN junction is formed between the P-type base region and the N-type doping region.

9. A method for preparing an IGBT with improved turn-off loss, characterized in that: The preparation method comprises: Epitaxially forming a drift region on the front side of an N-type substrate; the drift region includes a P-type drift region and an N-type drift region; forming a gate dielectric layer and a gate polysilicon layer on the vertical portion of the P-type drift region, wherein the gate dielectric layer wraps the gate polysilicon layer; forming a carrier storage layer in an area adjacent to the gate dielectric layer; wherein the carrier storage layer is formed on the drift region; forming a P-type base region on the carrier storage layer; forming an N-type doping region and a P-type doping region on the P-type base region; N-type doping ions are implanted on the back side of the N-type substrate to form an N-type buffer layer, and P-type doping ions are implanted on the back side of the N-type buffer layer to form a P-type substrate; the P-type drift region is an L-shaped structure, the vertical portion of the P-type drift region is formed on the N-type buffer layer in parallel with the N-type drift region, and the horizontal portion of the P-type drift region is located at the lower side of the N-type drift region; the N-type drift region is located on one side of the P-type drift region, the gate polysilicon layer is located on the other side of the P-type drift region, and the sum of the width of the N-type drift region and the width of the gate polysilicon layer is greater than the total width of the P-type drift region; An emitter is formed in contact with the N-type doped region and the P-type doped region, and a collector is formed on the back side of the P-type substrate; the projection of the N-type drift region and the gate polysilicon layer in the direction from the collector to the emitter partially overlaps.

10. A chip, characterized in that: The invention comprises an IGBT with improved turn-off loss as claimed in any one of claims 1 to 8.

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