Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: a substrate; a channel layer and a barrier layer located on one side of the substrate; a first doped III-V semiconductor layer located on a side of the barrier layer away from the substrate; the first doped III-V semiconductor layer comprises a first through groove and a second through groove; an etching barrier layer and a second doped III-V semiconductor layer located on a side of the first doped III-V semiconductor layer away from the substrate; the first through groove and the second through groove are located on both sides of the etching barrier layer and the second doped III-V semiconductor layer, respectively; a source electrode located on a side of the first through groove away from the second doped III-V semiconductor layer; a drain electrode located on a side of the second through groove away from the second doped III-V semiconductor layer; and a gate electrode located on a side of the second doped III-V semiconductor layer away from the substrate. The present invention can effectively reduce the damage to the barrier layer caused during etching, and can be close to zero damage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] For existing gallium nitride (GaN) high electron mobility transistors (HEMTs), a doped III-V semiconductor layer is disposed on the barrier layer, and the doped III-V semiconductor layer may be a P-type gallium nitride layer (P-GaN). The doped III-V semiconductor layer needs to be etched, but etching the doped III-V semiconductor layer will cause serious loss of the barrier layer, affecting the performance of the GaN HEMT device. Summary of the invention

[0003] The present invention provides a semiconductor device and a preparation method thereof, so as to solve the problem of serious barrier layer loss of the existing GaN HEMT device.

[0004] In a first aspect, the present invention provides a semiconductor device, the semiconductor device comprising:

[0005] substrate;

[0006] A channel layer and a barrier layer located on one side of the substrate;

[0007] A first doped III-V semiconductor layer located on a side of the barrier layer away from the substrate; the first doped III-V semiconductor layer comprises a first through groove and a second through groove; the first doped III-V semiconductor layer is also provided with a first opening and a second opening;

[0008] An etch stop layer and a second doped III-V semiconductor layer located on a side of the first doped III-V semiconductor layer away from the substrate; the first through groove and the second through groove are located on both sides of the etch stop layer and the second doped III-V semiconductor layer, respectively;

[0009] A source electrode is located at a side of the first through groove away from the second doped III-V semiconductor layer; a portion of the source electrode is located at the first opening and connected to the barrier layer;

[0010] A drain electrode is located at a side of the second through groove away from the second doped III-V semiconductor layer; a portion of the drain electrode is located at the second opening and connected to the barrier layer;

[0011] The gate is located on a side of the second doped III-V group semiconductor layer away from the substrate.

[0012] Optionally, the semiconductor device further includes: a first protective layer and a second protective layer;

[0013] The first protective layer is located on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate, the first protective layer comprises a third through groove and a fourth through groove, a vertical projection of the third through groove on the substrate coincides with a vertical projection of the first through groove on the substrate, and a vertical projection of the fourth through groove on the substrate coincides with a vertical projection of the second through groove on the substrate;

[0014] The second protection layer is located at a side of the first protection layer away from the substrate, and is located in the first through groove, the second through groove, the third through groove and the fourth through groove;

[0015] The first protective layer is also provided with a third opening and a fourth opening, and the second protective layer is also provided with a fifth opening and a sixth opening; the vertical projections of the third opening and the fifth opening on the substrate coincide with the vertical projection of the first opening on the substrate, and the vertical projections of the fourth opening and the sixth opening on the substrate coincide with the vertical projection of the second opening on the substrate; part of the source is located at the first opening, the third opening and the fifth opening and is connected to the barrier layer, and part of the drain is located at the second opening, the fourth opening and the sixth opening and is connected to the barrier layer.

[0016] Optionally, the thickness of the second doped III-V semiconductor layer is greater than the thickness of the first doped III-V semiconductor layer, and the thickness of the first doped III-V semiconductor layer is between 0.1 nm and 2 nm.

[0017] Optionally, the thickness of the second doped III-V semiconductor layer is greater than the thickness of the etch stop layer, and the thickness of the etch stop layer is greater than the thickness of the first doped III-V semiconductor layer.

[0018] Optionally, the first doped III-V semiconductor layer and the second doped III-V semiconductor layer are both P-type gallium nitride layers; the etching stop layer is Al x Ga 1-x N layers, where 0.1≤x≤1.

[0019] Optionally, the width of the first through groove and the second through groove is between 0.5um and 4um.

[0020] In a second aspect, the present invention provides a method for preparing a semiconductor device, the method comprising:

[0021] providing a substrate;

[0022] forming a channel layer and a barrier layer in sequence on one side of the substrate;

[0023] forming a first doped III-V semiconductor layer on a side of the barrier layer away from the substrate;

[0024] forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate;

[0025] forming a second doped III-V semiconductor layer on a side of the etch stop layer away from the substrate;

[0026] Etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer;

[0027] Etching the etching stop layer outside the area covered by the second doped III-V semiconductor layer;

[0028] Etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer;

[0029] forming a source electrode on a side of the first through groove away from the second doped III-V group semiconductor layer;

[0030] forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer;

[0031] A gate is formed on a side of the second doped III-V group semiconductor layer away from the substrate.

[0032] Optionally, forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate comprises:

[0033] Al is formed on the side of the first doped III-V semiconductor layer away from the substrate. x Ga 1-x N layers, where 0.1≤x≤1.

[0034] Optionally, etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer includes:

[0035] forming a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate;

[0036] Etching a portion of the first protective layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove;

[0037] Etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer includes:

[0038] Parts of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer are etched to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0039] Optionally, forming a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate comprises:

[0040] forming a first sub-protective layer on a side of the first doped III-V group semiconductor layer and the second doped III-V group semiconductor layer away from the substrate;

[0041] A second subprotecting layer is formed on a side of the first subprotecting layer away from the substrate.

[0042] Optionally, after etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove, the method comprises:

[0043] A second protection layer is formed on a side of the first protection layer away from the substrate, and the second protection layer fills the first through-groove and the third through-groove as well as the second through-groove and the fourth through-groove.

[0044] Optionally, forming a second protective layer on a side of the first protective layer away from the substrate includes:

[0045] forming a third sub-protective layer on a side of the first protective layer away from the substrate;

[0046] A fourth sub-protecting layer is formed on a side of the third sub-protecting layer away from the substrate.

[0047] Optionally, a source electrode is formed on a side of the first through groove away from the second doped III-V semiconductor layer, and a drain electrode is formed on a side of the second through groove away from the second doped III-V semiconductor layer, comprising:

[0048] Etching the second protective layer to form a fifth opening and a sixth opening, etching the first protective layer to form a third opening connected to the fifth opening and a fourth opening connected to the sixth opening, and etching the first doped III-V semiconductor layer to form a first opening connected to the third opening and a second opening connected to the fourth opening;

[0049] A source electrode is formed in the first opening, the third opening and the fifth opening; the third through groove is located between the source electrode and the second doped III-V semiconductor layer;

[0050] A drain is formed in the second opening, the fourth opening and the sixth opening; and the fourth through groove is located between the drain and the second doped III-V group semiconductor layer.

[0051] Optionally, after forming a second doped III-V semiconductor layer on a side of the etch stop layer away from the substrate, the method further comprises:

[0052] forming a Schottky contact region in a middle region of a side of the second doped III-V group semiconductor layer away from the substrate;

[0053] A gate is formed on a side of the second doped III-V group semiconductor layer away from the substrate, comprising:

[0054] A gate is formed on a side of the Schottky contact region away from the substrate.

[0055] The technical solution of the embodiment of the present invention is that a first doped III-V semiconductor layer, an etch barrier layer and a second doped III-V semiconductor layer are stacked on the side of the barrier layer away from the substrate. In the process of forming a GaN HEMT semiconductor device, when etching the second doped III-V semiconductor layer, the etch barrier layer can be used as an etch stop layer, so that the etching of the second doped III-V semiconductor layer stops at the etch barrier layer. After the etching process of the second doped III-V semiconductor layer is completed, the etch barrier layer needs to be etched. At this time, the first doped III-V semiconductor layer can play the role of an etch stop layer, thereby effectively reducing the loss of the barrier layer in the entire etching process. At the same time, when forming the first through groove and the second through groove, the etching area of ​​the first doped III-V semiconductor layer is small, and at the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer and the barrier layer can be selected to etch the first doped III-V semiconductor layer, so the loss of the barrier layer is greatly reduced. The technical solution of the embodiment of the present invention adopts an etching barrier layer and a first doped III-V semiconductor layer as an etching stop layer, and a first through groove and a second through groove are provided to disconnect the three electrodes. Compared with the existing GaN HEMT device, the barrier layer damage caused during the etching process can be effectively reduced, and the damage can be close to zero, which is beneficial to improving device performance and enhancing product competitiveness.

[0056] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0058] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0060] Figure 3-Figure 11 It is a structural diagram corresponding to each step in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0061] Fig.12 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0062] Fig.13 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0063] Figure 14-17 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0064] Fig.18 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0065] Fig.19 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0066] Fig. 20 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0067] Fig.21 and Fig. 22 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0068] Fig.23 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0069] Fig.24 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0070] Fig.25 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0071] Fig.26 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0072] Figure 27-Figure 33 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0073] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0074] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0075] Figure 1 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, such as Figure 1 As shown, the semiconductor device includes: a substrate 1. A channel layer 2 and a barrier layer 3 located on one side of the substrate 1. A first doped III-V semiconductor layer 4 located on the side of the barrier layer 3 away from the substrate 1; the first doped III-V semiconductor layer 4 includes a first through groove 41 and a second through groove 42. The first doped III-V semiconductor layer 4 is also provided with a first opening 43 and a second opening 44. An etch stop layer 5 and a second doped III-V semiconductor layer 6 located on the side of the first doped III-V semiconductor layer 4 away from the substrate 1; the first through groove 41 and the second through groove 42 are respectively located on both sides of the etch stop layer 5 and the second doped III-V semiconductor layer 6. A source electrode 7 located on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6. A portion of the source electrode 7 is located at the first opening 43 and connected to the barrier layer 3. A drain electrode 8 located on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6. A portion of the drain electrode 8 is located at the second opening 44 and connected to the barrier layer 3. A gate electrode 9 is located at a side of the second doped III-V semiconductor layer 6 away from the substrate 1.

[0076] Specifically, Figure 1, a structure of a GaN HEMT semiconductor device is shown, the GaN HEMT semiconductor device comprises a stacked substrate 1, a channel layer 2 and a barrier layer 3, the substrate 1 can be a Si substrate, a sapphire substrate or a GaN substrate. The channel layer 2 can be made of intrinsic GaN, and the barrier layer 3 can be made of AlGaN material.

[0077] The barrier layer 3 further includes a first doped III-V semiconductor layer 4, an etch stop layer 5 and a second doped III-V semiconductor layer 6 stacked on the side away from the substrate 1. Exemplarily, the first doped III-V semiconductor layer 4 may include a P-type gallium nitride layer, and the second doped III-V semiconductor layer 6 may also include a P-type gallium nitride layer. The etch stop layer 5 is located on the side of the second doped III-V semiconductor layer 6 close to the substrate 1. In the process of forming the GaN HEMT semiconductor device, the second doped III-V semiconductor layer 6 needs to be patterned. Only the second doped III-V semiconductor layer 6 corresponding to the region of the gate 9 is retained by photolithography and etching. When etching the second doped III-V semiconductor layer 6, the etch stop layer 5 can be used as an etch stop layer, so that the etching of the second doped III-V semiconductor layer 6 stops at the etch stop layer 5. Exemplarily, the etch stop layer 5 can be made of Al x Ga 1-x N, wherein 0.1≤x≤1. After the second doped III-V semiconductor layer 6 is etched, the etching stop layer 5 needs to be etched, and at this time, the first doped III-V semiconductor layer 4 can act as an etching stop layer, thereby effectively reducing the loss of the barrier layer 3 during the entire etching process.

[0078] The first doped III-V semiconductor layer 4 needs to be provided with a first through groove 41 and a second through groove 42. The first through groove 41 can isolate the gate 9 from the source 7 and the source 7 from the drain 8, and the second through groove 42 can isolate the gate 9 from the drain 8 and the source 7 from the drain 8. After forming the first through groove 41 and the second through groove 42, the leaked barrier layer 3 can be subjected to interface enhancement treatment to passivate etching defects. Since the etching area of ​​the first doped III-V semiconductor layer 4 is small when the first through groove 41 and the second through groove 42 are formed, a gas with a relatively large removal rate of the first doped III-V semiconductor layer 4 and the barrier layer 3 can be selected to etch the first doped III-V semiconductor layer 4, so the loss of the barrier layer 3 is greatly reduced. When forming the source electrode 7 and the drain electrode 8, it is also necessary to form a first opening 43 and a second opening 44 on the first doped III-V semiconductor layer 4. Similar to the formation of the first through groove 41 and the second through groove 42, the etching area of ​​the first doped III-V semiconductor layer 4 is smaller during the formation of the first opening 43 and the second opening 44. At the same time, a gas with a relatively high removal rate of the first doped III-V semiconductor layer 4 and the barrier layer 3 can be selected to etch the first doped III-V semiconductor layer 4, thereby greatly reducing the loss of the barrier layer 3.

[0079] The GaN HEMT semiconductor device may further include a Schottky contact region 12, which is located on a side of the second doped III-V semiconductor layer 6 away from the substrate 1, and the gate 9 is located on a side of the Schottky contact region 12 away from the substrate 1. Exemplarily, the material of the Schottky contact region 12 may be titanium nitride.

[0080] The technical solution of the embodiment of the present invention is that a first doped III-V semiconductor layer, an etch barrier layer and a second doped III-V semiconductor layer are stacked on the side of the barrier layer away from the substrate. In the process of forming a GaN HEMT semiconductor device, when etching the second doped III-V semiconductor layer, the etch barrier layer can be used as an etch stop layer, so that the etching of the second doped III-V semiconductor layer stops at the etch barrier layer. After the etching process of the second doped III-V semiconductor layer is completed, the etch barrier layer needs to be etched. At this time, the first doped III-V semiconductor layer can play the role of an etch stop layer, thereby effectively reducing the loss of the barrier layer in the entire etching process. At the same time, when forming the first through groove and the second through groove, the etching area of ​​the first doped III-V semiconductor layer is small, and at the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer and the barrier layer can be selected to etch the first doped III-V semiconductor layer, so the loss of the barrier layer is greatly reduced. The technical solution of the embodiment of the present invention adopts an etching barrier layer and a first doped III-V semiconductor layer as an etching stop layer, and a first through groove and a second through groove are provided to disconnect the three electrodes. Compared with the existing GaN HEMT device, the barrier layer damage caused during the etching process can be effectively reduced, and the damage can be close to zero, which is beneficial to improving device performance and enhancing product competitiveness.

[0081] Optionally, based on the above embodiments, continue to refer to Figure 1 The semiconductor device further includes: a first protective layer 10 and a second protective layer 11. The first protective layer 10 is located on the side of the first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6 away from the substrate 1. The first protective layer 10 includes a third through groove 103 and a fourth through groove 104. The vertical projection of the third through groove 103 on the substrate 1 coincides with the vertical projection of the first through groove 41 on the substrate 1. The vertical projection of the fourth through groove 104 on the substrate 1 coincides with the vertical projection of the second through groove 42 on the substrate 1. The second protective layer 11 is located on the side of the first protective layer 10 away from the substrate 1, and is located in the first through groove 41, the second through groove 42, the third through groove 103 and the fourth through groove 104. The first protective layer 10 is also provided with a third opening 105 and a fourth opening 106, and the second protective layer 11 is also provided with a fifth opening 113 and a sixth opening 114. The vertical projections of the third opening 105 and the fifth opening 113 on the substrate 1 coincide with the vertical projection of the first opening 43 on the substrate 1, and the vertical projections of the fourth opening 106 and the sixth opening 114 on the substrate 1 coincide with the vertical projection of the second opening 44 on the substrate 1. Part of the source 7 is located at the first opening 43, and the third opening 105 and the fifth opening 113 are connected to the barrier layer 3. Part of the drain 8 is located at the second opening 44, and the fourth opening 106 and the sixth opening 114 are connected to the barrier layer 3.

[0082] Specifically, the GaN HEMT semiconductor device may further include a first protective layer 10 and a second protective layer 11. The first protective layer 10 may include a first sub-protective layer 101 and a second sub-protective layer 102. Exemplarily, the first sub-protective layer 101 may include an aluminum nitride layer, and the second sub-protective layer 102 may include a silicon nitride layer. A first doped III-V semiconductor layer 4 may be formed on the entire surface of the barrier layer 3, and a first protective layer 10 may be formed on the side of the first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6 away from the substrate 1. The first protective layer 10 is used to protect the second doped III-V semiconductor layer 6 and the Schottky contact region 12 and other film layers from etching damage when the first doped III-V semiconductor layer 4 is etched to form the first through groove 41 and the second through groove 42. When the first doped III-V semiconductor layer 4 is etched to form the first through-groove 41 and the second through-groove 42 , the first protective layer 10 is firstly etched to form the third through-groove 103 and the fourth through-groove 104 .

[0083] A second protective layer 11 is formed on the side of the first protective layer 10 away from the substrate 1, and the second protective layer 11 is also filled in the first through groove 41, the second through groove 42, the third through groove 103 and the fourth through groove 104. The second protective layer 11 may include a third sub-protective layer 111 and a fourth sub-protective layer 112. Exemplarily, the third sub-protective layer 111 may include an aluminum nitride layer, and the fourth sub-protective layer 112 may include a silicon nitride layer. The second protective layer 11 can protect the exposed barrier layer 3 by filling each through groove. When forming the source 7 and the drain 8, it is necessary to etch the second protective layer 11 to form the fifth opening 113 and the sixth opening 114, etch the first protective layer 10 to form the third opening 105 and the fourth opening 106, and etch the first doped III-V semiconductor layer 4 to form the first opening 43 and the second opening 44. The first opening 43, the third opening 105 and the fifth opening 113 are located on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6, and the second opening 44, the fourth opening 106 and the sixth opening 114 are located on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6. When the first opening 43 and the second opening 44 are formed, the etching area of ​​the first doped III-V semiconductor layer 4 is small, and at the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer 4 and the barrier layer 3 can be selected to etch the first doped III-V semiconductor layer 4, so compared with the prior art, the loss of the barrier layer 3 can be greatly reduced.

[0084] Optionally, based on the above embodiments, continue to refer to Figure 1 The thickness of the second doped III-V semiconductor layer 6 is greater than the thickness of the first doped III-V semiconductor layer 4 , and the thickness of the first doped III-V semiconductor layer 4 is between 0.1 nm and 2 nm.

[0085] Specifically, the thickness of the first doped III-V semiconductor layer 4 needs to be set very thin to prevent the two-dimensional electron gas (2DEG) below the region outside the gate 9 from being interrupted.

[0086] Optionally, based on the above embodiments, continue to refer to Figure 1 The thickness of the second doped III-V semiconductor layer 6 is greater than the thickness of the etch stop layer 5 , and the thickness of the etch stop layer 5 is greater than the thickness of the first doped III-V semiconductor layer 4 .

[0087] Specifically, the thicknesses of the first doped III-V semiconductor layer 4, the etch stop layer 5, and the second doped III-V semiconductor layer 6 can be set to increase in sequence, that is, the first doped III-V semiconductor layer 4 is the thinnest, the second doped III-V semiconductor layer 6 is the thickest, and the thickness of the etch stop layer 5 is between the thicknesses of the first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6. When setting the thicknesses of the first doped III-V semiconductor layer 4, the etch stop layer 5, and the second doped III-V semiconductor layer 6, it is ensured that the etch stop layer 5 and the first doped III-V semiconductor layer 4 can effectively block over-etching, and the second doped III-V semiconductor layer 6 can effectively optimize the gate performance.

[0088] Optionally, based on the above embodiments, continue to refer to Figure 1 The first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6 are both P-type gallium nitride layers; the etching stop layer 5 is Al x Ga 1-x N layers, where 0.1≤x≤1.

[0089] Specifically, the first doped III-V semiconductor layer 4 may include a P-type gallium nitride layer, and the second doped III-V semiconductor layer 6 may also include a P-type gallium nitride layer. x Ga 1-x N, where 0.1≤x≤1.

[0090] Optionally, based on the above embodiments, continue to refer to Figure 1 The width of the first through groove 41 and the second through groove 42 is between 0.5um and 4um.

[0091] Specifically, the first doped III-V semiconductor layer 4 needs to be provided with a first through groove 41 and a second through groove 42 , wherein the first through groove 41 can isolate the gate 9 from the source 7 and the source 7 from the drain 8 , and the second through groove 42 can isolate the gate 9 from the drain 8 and the source 7 from the drain 8 .

[0092] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 3-Figure 11 is a structural diagram corresponding to each step in a method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 2 As shown, the preparation method comprises:

[0093] S100: providing a substrate.

[0094] Specifically, Figure 3 As shown, a substrate 1 is first provided, and the substrate 1 can be a Si substrate, a sapphire substrate or a GaN substrate.

[0095] S110: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0096] Specifically, Figure 4 As shown, a channel layer 2 is first formed on one side of a substrate 1, and a barrier layer 3 is formed on a side of the channel layer 2 away from the substrate 1. The channel layer 2 may be made of intrinsic GaN, and the barrier layer 3 may be made of AlGaN material.

[0097] S120: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0098] Specifically, Figure 5 As shown, a first doped III-V semiconductor layer 4 is formed on a side of the barrier layer 3 away from the substrate 1 . Exemplarily, the first doped III-V semiconductor layer 4 may include a P-type gallium nitride layer.

[0099] S130: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0100] Specifically, Figure 6 As shown, an etching stop layer 5 is formed on a side of the first doped III-V group semiconductor layer 4 away from the substrate 1 .

[0101] S140: forming a second doped III-V group semiconductor layer on a side of the etch stop layer away from the substrate.

[0102] Specifically, Figure 7 As shown, a second doped III-V semiconductor layer 6 is formed on a side of the etch stop layer 5 away from the substrate 1 . Exemplarily, the second doped III-V semiconductor layer 6 may also include a P-type gallium nitride layer.

[0103] S150: etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0104] Specifically, Figure 8As shown, in the process of forming the GaN HEMT semiconductor device, the second doped III-V semiconductor layer 6 needs to be patterned, and only the second doped III-V semiconductor layer 6 corresponding to the gate area is retained by photolithography and etching. The etch barrier layer 5 is located on the side of the second doped III-V semiconductor layer 6 close to the substrate 1. When the second doped III-V semiconductor layer 6 is etched, the etch barrier layer 5 can be used as an etch stop layer, so that the etching of the second doped III-V semiconductor layer 6 stops at the etch barrier layer 5.

[0105] S160: etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0106] Specifically, Fig. 9 As shown, after the second doped III-V semiconductor layer 6 is etched, the etch barrier layer 5 needs to be etched. At this time, the first doped III-V semiconductor layer 4 can act as an etching stop layer, thereby effectively reducing the loss of the barrier layer 3 during the entire etching process.

[0107] S170: etching partial regions on both sides of the second doped III-V group semiconductor layer to form a first through groove and a second through groove in the first doped III-V group semiconductor layer.

[0108] Specifically, Fig.10 As shown, the first doped III-V semiconductor layer 4 on both sides of the second doped III-V semiconductor layer 6 is regionally etched to form a first through groove 41 and a second through groove 42. After the first through groove 41 and the second through groove 42 are formed, the leaked barrier layer 3 can be subjected to interface enhancement treatment to passivate etching defects. The first through groove 41 can isolate the gate and the source as well as the source and the drain, and the second through groove 42 can isolate the gate and the drain as well as the source and the drain. Since the etching area of ​​the first doped III-V semiconductor layer 4 is small when the first through groove 41 and the second through groove 42 are formed, and at the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer 4 and the barrier layer 3 can be selected to etch the first doped III-V semiconductor layer 4, the loss of the barrier layer 3 is greatly reduced.

[0109] S180: forming a source electrode on a side of the first through groove away from the second doped III-V group semiconductor layer.

[0110] Specifically, Fig.11As shown, the ohmic contact position is defined, and a source electrode 7 is formed on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6. When forming the source electrode 7, a first opening 43 needs to be formed on the first doped III-V semiconductor layer 4. Similar to the formation of the first through groove 41 and the second through groove 42, the etching area of ​​the first doped III-V semiconductor layer 4 is smaller. At the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer 4 and the barrier layer 3 can be selected to etch the first doped III-V semiconductor layer 4, thereby greatly reducing the loss of the barrier layer 3.

[0111] S190: forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer.

[0112] For details, please refer to Fig.11 , define the ohmic contact position, form a drain electrode 8 on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6, and when forming the drain electrode 8, it is necessary to form a second opening 44 on the first doped III-V semiconductor layer 4. Similar to the formation of the first through groove 41 and the second through groove 42, the etching area of ​​the first doped III-V semiconductor layer 4 is smaller, and at the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer 4 and the barrier layer 3 can be selected to etch the first doped III-V semiconductor layer 4, thereby greatly reducing the loss of the barrier layer 3.

[0113] S191: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0114] For details, please refer to Fig.11 A gate 9 is formed on a side of the second doped III-V group semiconductor layer 6 away from the substrate 1 .

[0115] The technical solution of the embodiment of the present invention is to sequentially form a first doped III-V semiconductor layer, an etch barrier layer and a second doped III-V semiconductor layer on the side of the barrier layer away from the substrate. In the process of forming a GaN HEMT semiconductor device, when etching the second doped III-V semiconductor layer, the etch barrier layer can be used as an etch stop layer, so that the etching of the second doped III-V semiconductor layer stops at the etch barrier layer. After the etching process of the second doped III-V semiconductor layer is completed, the etch barrier layer needs to be etched. At this time, the first doped III-V semiconductor layer can play the role of an etch stop layer, thereby effectively reducing the loss of the barrier layer in the entire etching process. At the same time, when forming the first through groove and the second through groove, the etching area of ​​the first doped III-V semiconductor layer is small, and at the same time, a gas with a relatively large removal rate of the first doped III-V semiconductor layer and the barrier layer can be selected to etch the first doped III-V semiconductor layer, so the loss of the barrier layer is greatly reduced. The technical solution of the embodiment of the present invention sets an etching barrier layer and a first doped III-V semiconductor layer as an etching stop layer, and sets a first through groove and a second through groove to disconnect the three electrodes. Compared with the existing preparation process of GaN HEMT devices, the barrier layer damage caused by the etching process can be effectively reduced, and the damage can be close to zero, which is beneficial to improving device performance and enhancing product competitiveness.

[0116] Optionally, based on the above embodiments, Fig.12 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.12 As shown, the preparation method comprises:

[0117] S200: providing a substrate.

[0118] S210: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0119] S220: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0120] S230: forming an Al layer on a side of the first doped III-V semiconductor layer away from the substrate x Ga 1-x N layers, where 0.1≤x≤1.

[0121] Specifically, Figure 6 As shown, the etching stop layer 5 can be made of Al x Ga 1-x N, and the component ratio of Al and Ga can be set according to actual needs.

[0122] S240: forming a second doped III-V group semiconductor layer on a side of the etch stop layer away from the substrate.

[0123] S250: etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0124] S260: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0125] S270: etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer.

[0126] S280: forming a source electrode on a side of the first through groove away from the second doped III-V group semiconductor layer.

[0127] S290: forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer.

[0128] S291: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0129] Optionally, based on the above embodiments, Fig.13 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 14-17 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.13 As shown, the preparation method comprises:

[0130] S300: providing a substrate.

[0131] S310: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0132] S320: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0133] S330: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0134] S340: forming a second doped III-V semiconductor layer on a side of the etch stop layer away from the substrate.

[0135] S350: etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0136] S360: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0137] S370: Form a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate.

[0138] Specifically, Fig.14 As shown, after the etching stopper layer 5 is etched, a first protective layer 10 is formed on the side of the first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6 away from the substrate 1. The first protective layer 10 is used to protect the second doped III-V semiconductor layer 6 and other film layers from etching damage when the first doped III-V semiconductor layer 4 is etched to form the first through groove and the second through groove.

[0139] S380: etching a portion of the first protection layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove.

[0140] Specifically, Fig.15 As shown, partial regions of the first protection layer 10 on both sides of the second doped III-V group semiconductor layer 6 are etched to form a third through groove 103 and a fourth through groove 104 .

[0141] S390: etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0142] Specifically, Fig.16 As shown, the first doped III-V semiconductor layer 4 in the region corresponding to the third through groove 103 is etched to form a first through groove 41 , and the first doped III-V semiconductor layer 4 in the region corresponding to the fourth through groove 104 is etched to form a second through groove 42 .

[0143] S391: forming a source electrode on a side of the first through groove away from the second doped III-V semiconductor layer.

[0144] Specifically, Fig.17 As shown, at this time, the first protective layer 10 on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6 needs to be etched to form a third opening 105, and the first doped III-V semiconductor layer 4 on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6 needs to be etched to form a first opening 43 connected to the third opening 105, and a source 7 is formed in the first opening 43 and the third opening 105, and the source 7 can also extend to the outside of the third opening 105.

[0145] S392: forming a drain electrode on a side of the second through groove away from the second doped III-V semiconductor layer.

[0146] For details, please refer to Fig.17At this time, it is necessary to etch the first protective layer 10 on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6 to form a fourth opening 106, and etch the first doped III-V semiconductor layer 4 on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6 to form a second opening 44 connected to the fourth opening 106, and form a drain 8 in the second opening 44 and the fourth opening 106, and the drain 8 can also extend to the outside of the fourth opening 106.

[0147] S393: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0148] For details, please refer to Fig.17 At this time, the first protective layer 10 of the second doped III-V semiconductor layer 6 away from the substrate 1 needs to be etched to form a through groove, and a gate 9 is formed in the through groove. The gate 9 can also extend to the outside of the through groove.

[0149] Optionally, based on the above embodiments, Fig.18 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Fig.19 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.18 As shown, the preparation method comprises:

[0150] S400: providing a substrate.

[0151] S410: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0152] S420: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0153] S430: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0154] S440: forming a second doped III-V group semiconductor layer on a side of the etch stop layer away from the substrate.

[0155] S450: etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0156] S460: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0157] S470: Form a first sub-protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate.

[0158] Specifically, Fig.14 and Fig.19As shown, the first protective layer 10 may include a first sub-protective layer 101 and a second sub-protective layer 102. When forming the first protective layer 10, the first sub-protective layer 101 is first formed on the side of the first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6 away from the substrate 1. Exemplarily, the first sub-protective layer 101 may include an aluminum nitride layer, and the aluminum nitride layer may be formed on the side of the first doped III-V semiconductor layer 4 and the second doped III-V semiconductor layer 6 away from the substrate 1 by a process such as atomic layer deposition (ALD).

[0159] S480: forming a second sub-protection layer on a side of the first sub-protection layer away from the substrate.

[0160] Specifically, Fig.14 As shown, a second subprotective layer 102 is formed on a side of the first subprotective layer 101 away from the substrate 1. Exemplarily, the second subprotective layer 102 may include a silicon nitride layer. The silicon nitride layer may be formed on a side of the first subprotective layer 101 away from the substrate 1 by chemical vapor deposition (CVD).

[0161] S490: etching a portion of the first protection layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove.

[0162] S491: etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0163] S492: forming a source electrode on a side of the first through groove away from the second doped III-V group semiconductor layer.

[0164] S493: forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer.

[0165] S494: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0166] Optionally, Fig. 20 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Fig.21 and Fig. 22 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig. 20 As shown, the preparation method comprises:

[0167] S500: providing a substrate.

[0168] S510: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0169] S520: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0170] S530: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0171] S540: forming a second doped III-V group semiconductor layer on a side of the etch stop layer away from the substrate.

[0172] S550: Etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0173] S560: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0174] S570: Form a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate.

[0175] S580: etching a portion of the first protection layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove.

[0176] S590: etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0177] S591: forming a second protective layer on a side of the first protective layer away from the substrate, wherein the second protective layer fills the first through-groove and the third through-groove as well as the second through-groove and the fourth through-groove.

[0178] Specifically, Fig.21 As shown, a second protective layer 11 is formed on the side of the first protective layer 10 away from the substrate 1, and the second protective layer 11 is also filled in the first through groove 41, the second through groove 42, the third through groove 103 and the fourth through groove 104. The second protective layer 11 can protect the exposed barrier layer 3 by filling each through groove.

[0179] S592: forming a source electrode on a side of the first through groove away from the second doped III-V group semiconductor layer.

[0180] Specifically, Fig. 22As shown, at this time, the second protective layer 11, the first protective layer 10 and the first doped III-V semiconductor layer 4 on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6 need to be etched to form a fifth opening 113, a third opening 105 and a first opening 43, and a source 7 is formed in the fifth opening 113, the third opening 105 and the first opening 43. The source 7 can also extend to the outside of the fifth opening 113.

[0181] S593: forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer.

[0182] For details, please refer to Fig. 22 At this time, the second protective layer 11, the first protective layer 10 and the first doped III-V semiconductor layer 4 on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6 need to be etched to form a sixth opening 114, a fourth opening 106 and a second opening 44, and a drain 8 is formed in the sixth opening 114, the fourth opening 106 and the second opening 44, and the drain 8 can also extend to the outside of the sixth opening 114.

[0183] S594: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0184] For details, please refer to Fig. 22 At this time, the second protective layer 11 and the first protective layer 10 of the second doped III-V semiconductor layer 6 away from the substrate 1 need to be etched to form a through groove, and a gate 9 is formed in the through groove. The gate 9 can also extend to the outside of the through groove.

[0185] Optionally, Fig.23 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Fig.24 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.23 As shown, the preparation method comprises:

[0186] S600: providing a substrate.

[0187] S610: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0188] S620: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0189] S630: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0190] S640: forming a second doped III-V group semiconductor layer on a side of the etch stop layer away from the substrate.

[0191] S650: Etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0192] S660: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0193] S670: Form a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate.

[0194] S680: etching a portion of the first protection layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove.

[0195] S690: etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0196] S691: forming a third sub-protection layer on a side of the first protection layer away from the substrate.

[0197] Specifically, Fig.21 and Fig.24 As shown, the second protective layer 11 may include a third sub-protective layer 111 and a fourth sub-protective layer 112. When forming the second protective layer 11, the third sub-protective layer 111 is first formed on the side of the first protective layer 10 away from the substrate 1. Exemplarily, the third sub-protective layer 111 may include an aluminum nitride layer, and the aluminum nitride layer may be formed on the side of the first protective layer 10 away from the substrate 1 by a process such as atomic layer deposition (ALD).

[0198] S692: forming a fourth sub-protecting layer on a side of the third sub-protecting layer away from the substrate.

[0199] Specifically, Fig.21 As shown, a fourth sub-protective layer 112 is formed on a side of the third sub-protective layer 111 away from the substrate 1. Exemplarily, the fourth sub-protective layer 112 may include a silicon nitride layer. The silicon nitride layer may be formed on a side of the third sub-protective layer 111 away from the substrate 1 by chemical vapor deposition (CVD).

[0200] S693: forming a source electrode on a side of the first through groove away from the second doped III-V group semiconductor layer.

[0201] S694: forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer.

[0202] S695: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0203] Optionally, Fig.25 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.25 As shown, the preparation method comprises:

[0204] S700: providing a substrate.

[0205] S710: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0206] S720: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0207] S730: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0208] S740: forming a second doped III-V semiconductor layer on a side of the etch stop layer away from the substrate.

[0209] S750: Etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0210] S760: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0211] S770: Form a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate.

[0212] S780: etching a portion of the first protection layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove.

[0213] S790: etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0214] S791: forming a second protective layer on a side of the first protective layer away from the substrate, wherein the second protective layer fills the first through-groove and the third through-groove as well as the second through-groove and the fourth through-groove.

[0215] S792: Etch the second protective layer to form a fifth opening and a sixth opening, etch the first protective layer to form a third opening connected to the fifth opening, and a fourth opening connected to the sixth opening, and etch the first doped III-V semiconductor layer to form a first opening connected to the third opening, and a second opening connected to the fourth opening.

[0216] Specifically, Fig. 22As shown, the second protective layer 11, the first protective layer 10 and the first doped III-V semiconductor layer 4 on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6 are etched to form a fifth opening 113, a third opening 105 and a first opening 43, and the second protective layer 11, the first protective layer 10 and the first doped III-V semiconductor layer 4 on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6 are etched to form a sixth opening 114, a fourth opening 106 and a second opening 44.

[0217] S793: forming a source electrode in the first opening, the third opening and the fifth opening; the third through groove is located between the source electrode and the second doped III-V semiconductor layer.

[0218] Specifically, Fig. 22 As shown, the source electrode 7 is formed in the first opening 43 , the third opening 105 and the fifth opening 113 , and the source electrode 7 may also extend to the outside of the fifth opening 113 .

[0219] S794: forming a drain in the second opening, the fourth opening and the sixth opening; the fourth through groove is located between the drain and the second doped III-V semiconductor layer.

[0220] Specifically, Fig. 22 As shown, the drain 8 is formed in the second opening 44 , the fourth opening 106 and the sixth opening 114 , and the drain 8 may also extend to the outside of the sixth opening 114 .

[0221] S795: forming a gate on a side of the second doped III-V group semiconductor layer away from the substrate.

[0222] Optionally, Fig.26 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 27-Figure 33 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.26 As shown, the preparation method comprises:

[0223] S800: providing a substrate.

[0224] S810: forming a channel layer and a barrier layer in sequence on one side of the substrate.

[0225] S820: forming a first doped III-V group semiconductor layer on a side of the barrier layer away from the substrate.

[0226] S830: forming an etching stop layer on a side of the first doped III-V group semiconductor layer away from the substrate.

[0227] S840: forming a second doped III-V group semiconductor layer on a side of the etch stop layer away from the substrate.

[0228] S850: forming a Schottky contact region in a middle region of a side of the second doped III-V group semiconductor layer away from the substrate.

[0229] Specifically, Fig. 27 As shown, a Schottky contact region 12 is formed in the middle region of the second doped III-V semiconductor layer 6 on a side away from the substrate 1 . Exemplarily, the material of the Schottky contact region 12 may be titanium nitride.

[0230] S860: Etching the second doped III-V semiconductor layer located on both sides of the surface of the etching stop layer.

[0231] Specifically, Fig.28 As shown, the second doped III-V group semiconductor layer 6 located on both sides of the surface of the etching stop layer 5 is etched.

[0232] S870: Etching the etching stop layer outside the area covered by the second doped III-V group semiconductor layer.

[0233] Specifically, Fig.29 As shown, the etching stop layer 5 outside the area covered by the second doped III-V group semiconductor layer 6 is etched.

[0234] S880: Form a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate.

[0235] Specifically, Fig.30 As shown, a first protective layer 10 is formed on the side of the first doped III-V semiconductor layer 4, the second doped III-V semiconductor layer 6 and the Schottky contact region 12 away from the substrate 1. The first protective layer 10 is used to protect the second doped III-V semiconductor layer 6, the Schottky contact region 12 and other film layers from etching damage when the first doped III-V semiconductor layer 4 is etched to form a first through groove and a second through groove.

[0236] S890: etching a portion of the first protection layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove.

[0237] Specifically, Fig.31 As shown, a portion of the first protection layer 10 on both sides of the second doped III-V group semiconductor layer 6 is etched to form a third through groove 103 and a fourth through groove 104 .

[0238] S891: etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through-groove connected to the third through-groove and a second through-groove connected to the fourth through-groove.

[0239] For details, please refer to Fig.31, etching portions of the first doped III-V semiconductor layer 4 on both sides of the second doped III-V semiconductor layer 6 to form a first through groove 41 connected to the third through groove 103 , and a second through groove 42 connected to the fourth through groove 104 .

[0240] S892: forming a second protective layer on a side of the first protective layer away from the substrate, wherein the second protective layer fills the first through-groove and the third through-groove as well as the second through-groove and the fourth through-groove.

[0241] Specifically, Fig.32 As shown, a second protective layer 11 is formed on a side of the first protective layer 10 away from the substrate 1 , and the second protective layer 11 fills the first through-grooves 41 and the third through-grooves 103 as well as the second through-grooves 42 and the fourth through-grooves 104 .

[0242] S893: Etching the second protective layer to form a fifth opening and a sixth opening, etching the first protective layer to form a third opening connected to the fifth opening, and a fourth opening connected to the sixth opening, etching the first doped III-V semiconductor layer to form a first opening connected to the third opening, and a second opening connected to the fourth opening.

[0243] Specifically, Fig.33 As shown, the second protective layer 11, the first protective layer 10 and the first doped III-V semiconductor layer 4 on the side of the first through groove 41 away from the second doped III-V semiconductor layer 6 are etched to form a fifth opening 113, a third opening 105 and a first opening 43, and the second protective layer 11, the first protective layer 10 and the first doped III-V semiconductor layer 4 on the side of the second through groove 42 away from the second doped III-V semiconductor layer 6 are etched to form a sixth opening 114, a fourth opening 106 and a second opening 44. The second protective layer 11 and the first protective layer 10 on the side of the second doped III-V semiconductor layer 6 away from the substrate 1 are etched to form a seventh through groove 14.

[0244] S894: forming a source electrode in the first opening, the third opening and the fifth opening; the third through groove is located between the source electrode and the second doped III-V semiconductor layer.

[0245] S895: forming a drain in the second opening, the fourth opening and the sixth opening; and the fourth through groove is located between the drain and the second doped III-V semiconductor layer.

[0246] S896: forming a gate on a side of the Schottky contact region away from the substrate.

[0247] Specifically, Figure 1 and Fig.33 As shown, the gate 9 is formed in the seventh through groove 14 , that is, the gate 9 is formed on the side of the Schottky contact region 12 away from the substrate 1 , and the gate 9 may also extend to the outside of the seventh through groove 14 .

[0248] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0249] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; a channel layer and a barrier layer located on one side of the substrate; a first doped III-V semiconductor layer located at a side of the barrier layer away from the substrate; the first doped III-V semiconductor layer comprises a first through groove and a second through groove; the first doped III-V semiconductor layer is also provided with a first opening and a second opening; an etch stop layer and a second doped III-V semiconductor layer located on a side of the first doped III-V semiconductor layer away from the substrate; the first through groove and the second through groove are located on both sides of the etch stop layer and the second doped III-V semiconductor layer, respectively; A source electrode is located at a side of the first through groove away from the second doped III-V semiconductor layer; a portion of the source electrode is located at the first opening and connected to the barrier layer; A drain electrode is located at a side of the second through groove away from the second doped III-V semiconductor layer; a portion of the drain electrode is located at the second opening and connected to the barrier layer; a gate located on a side of the second doped III-V semiconductor layer away from the substrate; The first doped III-V semiconductor layer and the second doped III-V semiconductor layer are both P-type gallium nitride layers; the etching stop layer is Al x Ga 1-x N layers, where 0.1≤x≤1; The thickness of the second doped III-V semiconductor layer is greater than the thickness of the etch barrier layer, and the thickness of the etch barrier layer is greater than the thickness of the first doped III-V semiconductor layer; in the process of forming a semiconductor device, when the etch barrier layer is first etched, the first doped III-V semiconductor layer is used as an etching stop layer; and then partial areas on both sides of the second doped III-V semiconductor layer are etched to form the first through groove and the second through groove in the first doped III-V semiconductor layer.

2. The semiconductor device according to claim 1, wherein: Also includes: a first protective layer and a second protective layer; The first protective layer is located on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate, the first protective layer comprises a third through groove and a fourth through groove, a vertical projection of the third through groove on the substrate coincides with a vertical projection of the first through groove on the substrate, and a vertical projection of the fourth through groove on the substrate coincides with a vertical projection of the second through groove on the substrate; The second protection layer is located on a side of the first protection layer away from the substrate, and is located in the first through groove, the second through groove, the third through groove and the fourth through groove; The first protective layer is also provided with a third opening and a fourth opening, and the second protective layer is also provided with a fifth opening and a sixth opening; the vertical projections of the third opening and the fifth opening on the substrate coincide with the vertical projection of the first opening on the substrate, and the vertical projections of the fourth opening and the sixth opening on the substrate coincide with the vertical projection of the second opening on the substrate; part of the source electrode is located at the first opening, the third opening and the fifth opening and is connected to the barrier layer, and part of the drain electrode is located at the second opening, the fourth opening and the sixth opening and is connected to the barrier layer.

3. The semiconductor device according to claim 1, wherein: The thickness of the second doped III-V semiconductor layer is greater than the thickness of the first doped III-V semiconductor layer, and the thickness of the first doped III-V semiconductor layer is between 0.1 nm and 2 nm.

4. The semiconductor device according to claim 1, wherein: The width of the first through groove and the second through groove is between 0.5um and 4um.

5. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a channel layer and a barrier layer in sequence on one side of the substrate; forming a first doped III-V semiconductor layer on a side of the barrier layer away from the substrate; forming an etching stop layer on a side of the first doped III-V semiconductor layer away from the substrate; forming a second doped III-V semiconductor layer on a side of the etch stop layer away from the substrate; Etching the second doped III-V semiconductor layer located on both sides of the surface of the etch stop layer; Etching the etching stop layer outside the area covered by the second doped III-V semiconductor layer; Etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer; forming a source electrode on a side of the first through groove away from the second doped III-V semiconductor layer; forming a drain electrode on a side of the second through groove away from the second doped III-V group semiconductor layer; forming a gate on a side of the second doped III-V semiconductor layer away from the substrate; The first doped III-V semiconductor layer and the second doped III-V semiconductor layer are both P-type gallium nitride layers; the etching stop layer is Al x Ga 1-x N layers, where 0.1≤x≤1; The thickness of the second doped III-V semiconductor layer is greater than the thickness of the etch stop layer, and the thickness of the etch stop layer is greater than the thickness of the first doped III-V semiconductor layer.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: Forming an etching stop layer on a side of the first doped III-V semiconductor layer away from the substrate, comprising: An Al layer is formed on a side of the first doped III-V semiconductor layer away from the substrate. x Ga 1-x N layers, where 0.1≤x≤1.

7. The method for preparing a semiconductor device according to claim 5, characterized in that: Etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer comprises: forming a first protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate; Etching a portion of the first protective layer on both sides of the second doped III-V group semiconductor layer to form a third through groove and a fourth through groove; Etching partial regions on both sides of the second doped III-V semiconductor layer to form a first through groove and a second through groove in the first doped III-V semiconductor layer includes: Parts of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer are etched to form the first through-groove connected to the third through-groove and the second through-groove connected to the fourth through-groove.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: A first protective layer is formed on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate, comprising: forming a first sub-protective layer on a side of the first doped III-V semiconductor layer and the second doped III-V semiconductor layer away from the substrate; A second sub-protecting layer is formed on a side of the first sub-protecting layer away from the substrate.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: After etching a portion of the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form the first through-groove connected to the third through-groove and the second through-groove connected to the fourth through-groove, the method comprises: A second protection layer is formed on a side of the first protection layer away from the substrate, and the second protection layer fills the first through-groove and the third through-groove as well as the second through-groove and the fourth through-groove.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: Forming a second protective layer on a side of the first protective layer away from the substrate, comprising: forming a third sub-protective layer on a side of the first protective layer away from the substrate; A fourth sub-protecting layer is formed on a side of the third sub-protecting layer away from the substrate.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: A source electrode is formed on a side of the first through groove away from the second doped III-V semiconductor layer, and a drain electrode is formed on a side of the second through groove away from the second doped III-V semiconductor layer, comprising: Etching the second protective layer to form a fifth opening and a sixth opening, etching the first protective layer to form a third opening connected to the fifth opening and a fourth opening connected to the sixth opening, and etching the first doped III-V semiconductor layer to form a first opening connected to the third opening and a second opening connected to the fourth opening; A source electrode is formed in the first opening, the third opening and the fifth opening; the third through groove is located between the source electrode and the second doped III-V semiconductor layer; A drain is formed in the second opening, the fourth opening and the sixth opening; and the fourth through groove is located between the drain and the second doped III-V semiconductor layer.

12. The method for preparing a semiconductor device according to claim 5, characterized in that: After forming a second doped III-V semiconductor layer on a side of the etch stop layer away from the substrate, the method further comprises: forming a Schottky contact region in a middle region of a side of the second doped III-V semiconductor layer away from the substrate; A gate is formed on a side of the second doped III-V semiconductor layer away from the substrate, comprising: A gate is formed on a side of the Schottky contact region away from the substrate.

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