A silicon carbide trench power device and a method for preparing the same

Abstract

The present invention belongs to the field of semiconductor technology, and discloses a silicon carbide trench power device and a preparation method thereof, wherein a source trench is provided on the epitaxial structure of the silicon carbide trench power device; a low dielectric constant material is provided in the source trench as the contact area between the source of the device and the epitaxial structure. When the device is reversely withstand voltage, the area where the low dielectric constant material is located can reach the electric field peak before the gate, forming an electric field shielding area, thereby achieving the purpose of protecting the gate oxide of the device. In addition, since the dielectric strength of the low dielectric constant material is greater, when the device is reversely withstand voltage, it can have a higher breakdown field strength, thereby improving the withstand voltage capability of the silicon carbide trench power device, reducing leakage under reverse withstand voltage, and improving the reliability of the device in long-term operation.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a silicon carbide trench power device and a preparation method thereof. Background Art

[0002] The third generation semiconductor silicon carbide (SiC) has obvious advantages in high temperature, high voltage resistance and high current, and is more suitable for the production of high temperature, high frequency, radiation-resistant and high-power devices. SiC power devices are mainly divided into planar and trench types. Among them, trench SiC power devices have lower on-resistance and greater current density due to the lack of JFET (Junction Field-Effect Transistor) effect. They have the advantages of high integration, low on-resistance, small reverse capacitance, fast switching speed and small switching loss, and are more widely used than planar SiC power devices. However, trench SiC power devices have the problem of large electric field at the bottom of the gate trench and easy breakdown or injection of interface states, which limits their reliability in long-term applications.

[0003] In the prior art, in order to solve the above problems, a P+ injection region is usually set at the bottom of the gate trench. When the reverse withstand voltage is applied, the P+ injection region at the bottom of the gate trench is depleted to form a space charge region, which is used to protect the gate oxide at the bottom of the trench and play a role in high withstand voltage; or, there is also a method of protecting the device gate oxide by optimizing the dielectric layer in the gate trench. However, the long-term reliability of trench SiC power devices still needs to be further improved. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a silicon carbide trench power device and a preparation method thereof.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] A silicon carbide trench power device is provided with a source trench on its epitaxial structure; a low dielectric constant material is provided in the source trench as a contact area between the source of the device and the epitaxial structure.

[0007] Optionally, the low dielectric constant material includes: SiLK or methyl silsesquioxane MSQ.

[0008] Optionally, the gate trench of the silicon carbide trench power device is located at the center of the epitaxial structure; a source trench is provided at both ends of the epitaxial structure; the source trench includes an upper part and a lower part; wherein the source trench at the lower part is wider than the source trench at the upper part and is closer to the center of the epitaxial structure.

[0009] Optionally, the epitaxial structure is an N-epitaxial layer;

[0010] The silicon carbide trench power device comprises:

[0011] N+ substrate;

[0012] An N-epitaxial layer is superimposed on the N+ substrate, the center of the N-epitaxial layer is provided with the gate trench, and two ends of the N-epitaxial layer are provided with the source trench respectively; the depth of the source trench is greater than the depth of the gate trench; on the N-epitaxial layer between the gate trench and each of the source trenches, an N+ region and a P-type region are sequentially provided along the trench depth direction;

[0013] A first oxide dielectric layer, located at the bottom and sidewalls of the gate trench;

[0014] A low dielectric constant material is located in the two source trenches respectively and contacts the adjacent P-type regions;

[0015] A gate, located in the gate trench;

[0016] A second oxide dielectric layer, covering the two N+ regions and the gate;

[0017] The source electrode covers the second oxide dielectric layer and contacts the low dielectric constant material in the two source trenches.

[0018] Optionally, the gate is polysilicon; and the polysilicon fills the gate trench.

[0019] The present invention also provides a method for preparing a silicon carbide trench power device, comprising:

[0020] After the main body of the device is prepared and before the source electrode is to be prepared, a source electrode groove is etched on the epitaxial structure of the device;

[0021] Depositing a low dielectric constant material in the source trench as a contact region between the source of the device and the epitaxial structure;

[0022] Continue to complete the preparation of the source electrode.

[0023] Optionally, depositing a low dielectric constant material in the source trench comprises:

[0024] SiLK or methyl silsesquioxane MSQ is deposited in the source trench.

[0025] Optionally, the gate trench of the silicon carbide trench power device is located at the center of the epitaxial structure;

[0026] The step of etching a source trench on the epitaxial structure of the device comprises:

[0027] Using a dry etching process, an initial source trench is etched at both ends of the epitaxial structure of the device;

[0028] The current source trench is continuously etched downward using the wet etching process, so that the etched source trench includes an upper portion and a lower portion, and the lower source trench is wider than the upper source trench and closer to the center of the epitaxial structure.

[0029] The present invention also provides a method for preparing a silicon carbide trench power device, comprising:

[0030] Providing an N+ substrate;

[0031] epitaxially growing an N- epitaxial layer on the N+ substrate;

[0032] Etching a gate trench in the center of the N-epitaxial layer;

[0033] Generating a layer of oxide on the upper surface of the N-epitaxial layer, the bottom and sidewalls of the gate trench by a thermal oxidation process;

[0034] Depositing polysilicon until the gate trench is filled with polysilicon and the oxide is covered with polysilicon;

[0035] Removing polysilicon and oxide outside the gate trench; wherein the remaining oxide in the gate trench forms a first oxide dielectric layer;

[0036] A layer of oxide is generated on the surface of the device by a thermal oxidation process as a second oxide dielectric layer;

[0037] Using ion implantation technology, forming a P-type region and an N+ region on the N-epitaxial layer on both sides of the gate trench; wherein the N+ region on the N-epitaxial layer on each side of the gate trench is on the upper side and the P-type region is on the lower side;

[0038] Etching the N-epitaxial layer on both sides of the gate trench by dry etching process to form two initial source trenches;

[0039] Continue to etch the current source trench downward using the wet etching process, so that the etched source trench includes an upper portion and a lower portion, and the lower source trench is wider than the upper source trench and closer to the center of the N-epitaxial layer;

[0040] Depositing a low dielectric constant material in the etched source trench so that the low dielectric constant material forms contact with an adjacent P-type region;

[0041] A source electrode is prepared; wherein the source electrode covers the second oxide dielectric layer and contacts the low dielectric constant material in the two source electrode trenches.

[0042] The silicon carbide trench power device provided by the present invention is provided with a source trench, and a low dielectric constant material is provided inside the source trench. Thus, when the device withstands reverse voltage, the region where the low dielectric constant material is located can reach the electric field peak before the gate, forming an electric field shielding region, thereby achieving the purpose of protecting the gate oxide of the device. In addition, since the dielectric strength of the low dielectric constant material is greater, when the device withstands reverse voltage, it can have a higher breakdown field strength, thereby improving the withstand voltage capability of the silicon carbide trench power device, reducing leakage under reverse voltage withstand, and improving the reliability of the device in long-term operation.

[0043] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic structural diagram of a silicon carbide trench power device provided by an embodiment of the present invention;

[0045] Figure 2 It is a flow chart of a method for preparing a silicon carbide trench power device provided by an embodiment of the present invention;

[0046] Figure 3 yes Figure 2 A schematic diagram of the device structure obtained after step S2 in the method shown is executed;

[0047] Figure 4 yes Figure 2 A schematic diagram of the device structure obtained after step S3 in the method shown is executed;

[0048] Figure 5 yes Figure 2 A schematic diagram of the device structure obtained after step S4 in the method shown is executed;

[0049] Figure 6 yes Figure 2 A schematic diagram of the device structure obtained after step S5 in the method shown is executed;

[0050] Figure 7 yes Figure 2 A schematic diagram of the device structure obtained after step S7 in the method shown is executed;

[0051] Figure 8 yes Figure 2 A schematic diagram of the device structure obtained after step S8 in the method shown is executed;

[0052] Fig. 9 yes Figure 2 A schematic diagram of the device structure obtained after step S9 of the method is executed;

[0053] Fig.10 yes Figure 2A schematic diagram of the device structure obtained after step S10 in the method shown is executed;

[0054] Fig.11 yes Figure 2 A schematic diagram of the device structure obtained after step S11 in the method shown is executed;

[0055] Fig.12 yes Figure 2 A schematic diagram of the device structure obtained after step S12 in the method shown is executed.

[0056] Reference numerals:

[0057] 1. N+ substrate; 2. N- epitaxial layer; 3. gate trench; 4. first hard mask; 5. first oxide dielectric layer; 51. second oxide dielectric layer; 6. gate; 7. P-type region; 8. N+ region; 9. second hard mask; 10. source trench; 11. low dielectric constant material; 12. source. DETAILED DESCRIPTION

[0058] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0059] In order to further improve the long-term reliability of the trench silicon carbide power device, the embodiment of the present invention provides a silicon carbide trench power device, compared with the existing silicon carbide trench power device, such as Figure 1 As shown, the epitaxial structure of the silicon carbide trench power device provided by the embodiment of the present invention is provided with a source trench 10, and a low dielectric constant material 11 is provided in the source trench 10 as a contact area between the source 12 of the device and the epitaxial structure. In addition, the structure of the rest of the silicon carbide trench power device provided by the embodiment of the present invention can be the same as that of the existing silicon carbide trench power device, but is certainly not limited thereto, and examples will be given later.

[0060] Among them, the epitaxial structure is mainly a silicon carbide epitaxial layer; it should be noted that the trench mentioned in the silicon carbide trench power device refers to the gate trench 3, which is filled with the gate material. The source trench 10 in the embodiment of the present invention refers to the trench formed in the part where the source 12 and the epitaxial structure contact, and the source trench 10 is provided with a low dielectric constant material 11. The low dielectric constant material 11 refers to a material with a dielectric constant lower than 3.9. Exemplarily, the low dielectric constant material 11 arranged in the source trench 10 in the embodiment of the present invention may include: SiLK or methyl silsesquioxane (MSQ), of course, but is not limited to this. Here, SiLK is a polymer material widely used in the production of integrated circuits.

[0061] The silicon carbide trench power device provided in the embodiment of the present invention is provided with a source trench 10, and a low dielectric constant material 11 is provided inside the source trench 10. Therefore, when the device is reversely withstand voltage, the area where the low dielectric constant material 11 is located can reach the electric field peak before the gate, forming an electric field shielding area, thereby achieving the purpose of protecting the gate oxide of the device. In addition, since the dielectric strength of the low dielectric constant material 11 is greater, when the device is reversely withstand voltage, it can have a higher breakdown field strength, thereby improving the withstand voltage capability of the silicon carbide trench power device, reducing leakage under reverse withstand voltage, and improving the reliability of the device in long-term operation.

[0062] In the embodiment of the present invention, silicon carbide is used to form a silicon carbide trench power device, which can achieve the withstand voltage level of silicon-based IGBT (insulated gate bipolar transistor) devices through a simple structure, while avoiding the disadvantage of high energy consumption of silicon-based IGBT devices. Benefiting from silicon carbide materials, the silicon carbide trench power device has obvious advantages in high temperature, high withstand voltage and high current, and is more suitable for making high-temperature, high-frequency, radiation-resistant and high-power switching devices, so as to be better used in inverters, on-board chargers and fast charging piles for driving and controlling motors.

[0063] It is worth mentioning that, although the shielding area is set by element doping in the area where the source and the epitaxial structure contact, the high electric field borne by the gate oxide during reverse withstand voltage can also be transferred, thereby achieving the purpose of protecting the gate oxide, improving withstand voltage and reliability, but this increases the complexity of setting the process conditions, and it is necessary to consider the mutual influence with other doping process steps, so that the reliability of the device in long-term use is still subject to certain restrictions. In the embodiment of the present invention, by etching the source trench 10 on the epitaxial structure and additionally depositing the low dielectric constant material 11 in the source trench 10, the preparation process is simple, and there is no need to consider the mutual influence with other doping process steps, which has better application prospects.

[0064] In the embodiment of the present invention, there are various relative positional relationships between the gate trench 3 and the source trench 10 .

[0065] Exemplarily, in one implementation, the gate trench 3 is located at the center of the epitaxial structure; a source trench 10 is provided at both ends of the epitaxial structure; the source trench 10 includes an upper part and a lower part; wherein the lower source trench 10 is wider than the upper source trench 10 and closer to the center of the epitaxial structure.

[0066] In another implementation, the gate trench 3 is located at the center of the epitaxial structure; an annular source trench 10 is provided around the epitaxial structure; the annular source trench 10 also includes an upper part and a lower part; wherein the lower source trench 10 is wider than the upper source trench 10 and closer to the center of the epitaxial structure.

[0067] In a specific embodiment, Fig.12 As shown, the silicon carbide trench power device provided in an embodiment of the present invention may include: an N+ substrate 1, an N- epitaxial layer 2, a first oxide dielectric layer 5, a low dielectric constant material 11, a gate 6, a second oxide dielectric layer 51 and a source 12.

[0068] Among them, the N-epitaxial layer 2 is superimposed on the N+ substrate 1, and the N+ substrate 1 is the drain of the silicon carbide trench power device. A gate trench 3 is provided in the center of the N-epitaxial layer 2, and a source trench 10 is provided at both ends; the depth of the source trench 10 is greater than the depth of the gate trench 3; on the N-epitaxial layer 2 between the gate trench 3 and each source trench 10, an N+ region 8 and a P-type region 7 are provided in sequence along the trench depth direction.

[0069] The first oxide dielectric layer 5 is located at the bottom and sidewalls of the gate trench 3 . Exemplarily, the material of the first oxide dielectric layer 5 may be silicon dioxide, but is certainly not limited thereto.

[0070] The low dielectric constant material 11 is located in the two source trenches 10 respectively and contacts the adjacent P-type region 7. It can be understood that the low dielectric constant material 11 does not contact the adjacent N+ region 8.

[0071] The gate 6 is located in the gate trench 3. For example, the material of the gate 6 may be polysilicon, which fills the gate trench 3. Of course, the material of the gate 6 may also be gate metal.

[0072] The second oxide dielectric layer 51 covers the two N+ regions 8 and the gate 6 ; here, the material of the second oxide dielectric layer 51 is the same as that of the first oxide dielectric layer 5 .

[0073] The source electrode 12 covers the second oxide dielectric layer 51 and contacts the low dielectric constant material 11 in the two source trenches 10. Here, the source electrode 12 is a metal electrode.

[0074] Understandably, Fig.12 The specific structure of the silicon carbide trench power device shown is only an example and does not constitute a limitation on the embodiments of the present invention. Fig.12On the basis of the structure shown, it is possible to further set a P+ injection region at the bottom of the gate trench 3, and / or use a composite oxide dielectric layer as the oxide dielectric layer of the device. The composite oxide dielectric layer can be such a dielectric layer: a layer of low dielectric constant material is arranged in contact with the bottom and sidewall of the gate trench 3, and a layer of silicon dioxide is deposited on the surface of the low dielectric constant material. Alternatively, the composite oxide dielectric layer can also be such a dielectric layer: a thickened layer of low dielectric constant material is arranged at the bottom of the gate trench 3, and a layer of silicon dioxide is generated by oxidation on the sidewall of the gate trench 3, and the layer of silicon dioxide is in contact with the low dielectric constant material at the bottom of the gate trench 3 to form a composite oxide dielectric layer.

[0075] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a silicon carbide trench power device, the method comprising the following steps:

[0076] Step 1: After the main body of the device is prepared and before the source is prepared, a source trench is etched on the epitaxial structure of the device.

[0077] Here, the main body of the device includes its epitaxial structure, gate trench 3, gate 6, drain electrode and oxide dielectric layer. After completing the preparation of these structures, the source 12 should be prepared according to the existing conventional technology. Here, the embodiment of the present invention does not prepare the source 12 first, but first etches the source trench 10 on the epitaxial structure of the device.

[0078] Specifically, etching the source trench 10 on the epitaxial structure of the device includes: etching a source trench 10 at both ends of the epitaxial structure of the device using a dry etching process. Here, the cross-section of the source trench 10 from top to bottom can be the same.

[0079] Alternatively, in a preferred implementation, etching the source trench 10 on the epitaxial structure of the device may include:

[0080] (1) Using a dry etching process, an initial source trench is etched at both ends of the epitaxial structure of the device.

[0081] (2) Continue to etch the current source trench downward using the wet etching process, so that the etched source trench 10 includes an upper portion and a lower portion, and the lower source trench is wider than the upper source trench and closer to the center of the epitaxial structure.

[0082] In this implementation, the source trench 10 presents an L-shaped trench structure that is thin at the top and thick at the bottom, in which the lower portion of the source trench 10 is wider than the upper portion of the source trench 10 and is closer to the drain than the gate. In this way, the depletion region electric field during reverse withstand voltage is blocked by the low dielectric constant material 11 in the lower portion of the source trench 10 and will not extend to the bottom of the gate trench 3, thereby better protecting the oxide dielectric layer of the gate, that is, better protecting the device gate oxide.

[0083] Step 2: depositing a low dielectric constant material in the source trench as a contact area between the source of the device and the epitaxial structure;

[0084] Specifically, a low dielectric constant material such as SiLK or MSQ is deposited in the source trench 10 .

[0085] Step 3: Continue to complete the preparation of the source electrode.

[0086] Here, the source electrode 12 is a metal electrode, which can be prepared by a metal evaporation process or a magnetron sputtering process.

[0087] In a specific example, Figure 2 As shown, the process of preparing the silicon carbide trench power device proposed in the embodiment of the present invention may include the following steps:

[0088] S1. Provide an N+ substrate.

[0089] Specifically, an N+ substrate 1 with a suitable resistivity is selected so that the substrate can be used as a drain of the device later.

[0090] S2. epitaxially grow an N- epitaxial layer on an N+ substrate.

[0091] Specifically, an epitaxial layer having the same conductivity type as the N+ substrate 1, namely, an N-epitaxial layer 2, is formed on the N+ substrate 1. Figure 3 .

[0092] S3. Etching a gate trench in the center of the N-epitaxial layer.

[0093] Specifically, Figure 4 , a first hard mask 4 is formed on the N-epitaxial layer 2, a gate trench 3 is etched out by photolithography, etching and other processes, and then the first hard mask 4 is removed.

[0094] S4. A layer of oxide is formed on the upper surface of the N-epitaxial layer, the bottom and the sidewall of the gate trench by a thermal oxidation process.

[0095] Specifically, Figure 5 A layer of oxide, for example, a layer of silicon dioxide, is generated on the upper surface of the N-epitaxial layer 2, the bottom and the sidewall of the gate trench 3 through a thermal oxidation process.

[0096] S5. Deposit polysilicon until the gate trench is filled with polysilicon and the oxide is covered by polysilicon.

[0097] Specifically, polysilicon (Poly) is deposited on the current device by a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition (PECVD) process until the gate trench 3 is filled with polysilicon and the oxide is covered with polysilicon, such as Figure 6 .

[0098] S6, removing the polysilicon and oxide outside the gate trench; wherein the remaining oxide in the gate trench forms a first oxide dielectric layer.

[0099] Specifically, a chemical mechanical polishing process is used to remove the polysilicon and oxide outside the gate trench 3 , and the remaining oxide in the gate trench 3 forms the first oxide dielectric layer 5 .

[0100] S7. Generate a layer of oxide on the surface of the device through a thermal oxidation process as a second oxide dielectric layer.

[0101] Here, a thin layer of silicon dioxide can be formed on the surface of the device by a thermal oxidation process as the second oxide dielectric layer 51, such as Figure 7 .

[0102] S8. Use ion implantation technology to form a P-type region and an N+ region on the N-epitaxial layer on both sides of the gate trench; wherein the N+ region on the N-epitaxial layer on each side of the gate trench is on the upper side and the P-type region is on the lower side.

[0103] Specifically, Figure 8 , using ion implantation technology, P ion implantation and N+ ion implantation are performed in sequence on the second oxide dielectric layer 51 on the N- epitaxial layer 2 on both sides of the gate trench 3, and then annealing is performed to form a P-type region (pbody) 7 and an N+ region 8.

[0104] S9. Etch the N-epitaxial layer on both sides of the gate trench using a dry etching process to form two initial source trenches.

[0105] Specifically, a second hard mask 9 is formed on the N-epitaxial layer, and then an initial source trench 10 is etched out by photolithography, dry etching, etc. Fig. 9 .

[0106] S10, continue to etch the current source trench downward using the wet etching process, so that the etched source trench includes an upper portion and a lower portion, and the lower source trench is wider than the upper source trench and closer to the center of the N-epitaxial layer. Fig.10 .

[0107] S11 . Depositing a low dielectric constant material in the etched source trench so that the low dielectric constant material forms contact with the adjacent P-type region.

[0108] Specifically, a low dielectric constant material 11 is deposited in the etched source trench 10 so that the low dielectric constant material 11 is in contact with the adjacent P-type region 7, and then the low dielectric constant material 11 is etched back to a certain depth using a wet etching process so that the low dielectric constant material 11 is not in contact with the adjacent N+ region 8. Fig.11 .

[0109] S12, preparing a source electrode; wherein the source electrode covers the second oxide dielectric layer and contacts the low dielectric constant material in the two source electrode trenches. Fig.12 .

[0110] Here, the source 12 is a metal electrode. A source contact hole can be first prepared on the low dielectric constant material 11 in the two source trenches 10, and then a source metal is sputtered in the source contact hole using a magnetron sputtering process to form a metal electrode, namely the source 12, on the entire surface of the device.

[0111] The preparation method provided in the embodiment of the present invention is to prepare a source groove 10 in a silicon carbide trench power device, and prepare a low dielectric constant material 11 inside the source groove 10. As a result, when the prepared device is reversely withstand voltage, the area where the low dielectric constant material 11 is located can reach the electric field peak before the gate, forming an electric field shielding area, thereby achieving the purpose of protecting the gate oxide of the device. In addition, since the dielectric strength of the low dielectric constant material 11 is greater, when the device is reversely withstand voltage, it can have a higher breakdown field strength, thereby improving the withstand voltage capability of the silicon carbide trench power device, reducing leakage under reverse withstand voltage, and improving the reliability of the long-term operation of the device. In addition, the process of preparing the source groove 10 and depositing the low dielectric constant material 11 on the epitaxial structure in the embodiment of the present invention is simple, and there is no need to consider the mutual influence with other doping process steps, and has a better application prospect.

[0112] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0113] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0114] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0115] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0116] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0117] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A silicon carbide trench power device, characterized in that: A source trench is provided on the epitaxial structure of the silicon carbide trench power device; a low dielectric constant material is provided in the source trench as a contact area between the source of the device and the epitaxial structure; The gate trench of the silicon carbide trench power device is located at the center of the epitaxial structure; and a source trench is provided at both ends of the epitaxial structure; The source trench comprises an upper portion and a lower portion; wherein the source trench at the lower portion is wider than the source trench at the upper portion and is closer to the center of the epitaxial structure; the epitaxial structure is an N-epitaxial layer; The silicon carbide trench power device comprises: N+ substrate; An N-epitaxial layer is superimposed on the N+ substrate, the center of the N-epitaxial layer is provided with the gate trench, and two ends of the N-epitaxial layer are provided with the source trench respectively; the depth of the source trench is greater than the depth of the gate trench; on the N-epitaxial layer between the gate trench and each of the source trenches, an N+ region and a P-type region are sequentially provided along the trench depth direction; A first oxide dielectric layer, located at the bottom and sidewalls of the gate trench; A low dielectric constant material is located in the two source trenches respectively and contacts the adjacent P-type regions; the low dielectric constant material is a material having a dielectric constant lower than 3.9; A gate, located in the gate trench; A second oxide dielectric layer, covering the two N+ regions and the gate; The source electrode covers the second oxide dielectric layer and contacts the low dielectric constant material in the two source trenches.

2. The silicon carbide trench power device according to claim 1, characterized in that: The low dielectric constant material includes SiLK or methyl silsesquioxane MSQ.

3. The silicon carbide trench power device according to claim 1, characterized in that: The gate is made of polysilicon; the polysilicon fills the gate trench.

4. A method for preparing a silicon carbide trench power device, characterized in that: include: Providing an N+ substrate; epitaxially growing an N- epitaxial layer on the N+ substrate; Etching a gate trench in the center of the N-epitaxial layer; Generating a layer of oxide on the upper surface of the N-epitaxial layer, the bottom and sidewalls of the gate trench by a thermal oxidation process; Depositing polysilicon until the gate trench is filled with polysilicon and the oxide is covered with polysilicon; Removing polysilicon and oxide outside the gate trench; wherein the remaining oxide in the gate trench forms a first oxide dielectric layer; A layer of oxide is generated on the surface of the device by a thermal oxidation process as a second oxide dielectric layer; Using ion implantation technology, forming a P-type region and an N+ region on the N-epitaxial layer on both sides of the gate trench; wherein the N+ region on the N-epitaxial layer on each side of the gate trench is on the upper side and the P-type region is on the lower side; Etching the N-epitaxial layer on both sides of the gate trench by dry etching process to form two initial source trenches; Continue to etch the current source trench downward using the wet etching process, so that the etched source trench includes an upper portion and a lower portion, and the lower source trench is wider than the upper source trench and closer to the center of the N-epitaxial layer; Depositing a low dielectric constant material in the etched source trench so that the low dielectric constant material forms contact with the adjacent P-type region; the low dielectric constant material is a material with a dielectric constant lower than 3.9; A source electrode is prepared; wherein the source electrode covers the second oxide dielectric layer and contacts the low dielectric constant material in the two source electrode trenches.

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