Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises: an epitaxial wafer, comprising a substrate and an epitaxial layer located on the surface of the substrate; the epitaxial layer comprises an active region and a terminal region arranged in sequence; a cellular structure, located in the active region; a first multi-level groove, having a first step sidewall and a second step sidewall opposite to each other; the first step sidewall is adjacent to the cellular structure; the bottom of the first multi-level groove comprises a first bottom region adjacent to the first step sidewall and a second bottom region adjacent to the second step sidewall; a first-level field plate, comprising: a first dielectric layer, covering the surface of the first multi-level groove; a first field plate metal layer, covering the first dielectric layer located on the first step sidewall and the surface of the first bottom region; a second-level field plate, comprising: a second dielectric layer, covering at least the first field plate metal layer and the first dielectric layer located in the first multi-level groove; and a second field plate metal layer, covering at least part of the second dielectric layer on the surface of the second bottom region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The withstand voltage characteristic of semiconductor devices is a key performance indicator of semiconductor device performance. At present, most semiconductor devices adopt a solution of setting a field plate structure in the terminal area to improve the withstand voltage performance of semiconductor devices. The field plate structure can change the edge electric field distribution of semiconductor devices, and can introduce the electric field peak from the surface of the device into the body, avoiding excessive concentration of the electric field at the edge of the device, thereby improving the withstand voltage performance of semiconductor devices.

[0003] In the prior art, semiconductor devices generally use a planar field plate structure in the terminal region. However, the planar field plate structure has limited ability to adjust the edge electric field of the semiconductor device and has limited effect on improving the voltage resistance of the semiconductor device. Summary of the invention

[0004] In view of the above problems, the present application provides a semiconductor device and a method for manufacturing the same, so as to achieve the purpose of improving the withstand voltage performance of the semiconductor device. The specific scheme is as follows:

[0005] A first aspect of the present application provides a semiconductor device, comprising:

[0006] An epitaxial wafer, the epitaxial wafer comprising a substrate and an epitaxial layer located on the surface of the substrate; in a first direction, the epitaxial layer comprises an active region and a terminal region arranged in sequence; the first direction is parallel to the plane where the substrate is located;

[0007] Cellular structure, the cellular structure is located in the active area;

[0008] A first multi-level groove, the first multi-level groove having a first step sidewall and a second step sidewall opposite to each other; the first step sidewall is adjacent to the cellular structure; the bottom of the first multi-level groove includes a first bottom region adjacent to the first step sidewall and a second bottom region adjacent to the second step sidewall;

[0009] A first-level field plate, the first-level field plate comprising: a first dielectric layer covering the surface of the first multi-level trench; a first field plate metal layer covering the first dielectric layer located on the sidewall of the first step and the surface of the first bottom area;

[0010] The second-level field plate includes: a second dielectric layer, at least covering the first field plate metal layer and the first dielectric layer located in the first multi-level groove; a second field plate metal layer, the second field plate metal layer covers at least a portion of the second dielectric layer on the surface of the second bottom area, and has an overlapping area with the first field plate metal layer.

[0011] Optionally, in the above semiconductor device, the cell structure includes:

[0012] A first metal layer is used to form a Schottky contact with the epitaxial layer in the active region; the first metal layer also extends into the first multi-level trench to serve as a first field plate metal layer;

[0013] The second metal layer is used to cover at least a portion of the first metal layer in the active area to form a first electrode; the second metal layer also extends into the first multi-level trench to serve as a second field plate metal layer.

[0014] Optionally, in the above semiconductor device, a second multi-level trench is provided in the surface of the active region; and the surface of the second multi-level trench is covered with an isolation dielectric layer;

[0015] The first metal layer covers the isolation dielectric layer; the second metal layer fills the second multi-level trenches.

[0016] Optionally, in the above semiconductor device, the isolation dielectric layer and the first dielectric layer are a film of the same insulating material;

[0017] The insulating material film covers the surface of the first multi-level trench and the surface of the second multi-level trench, and exposes the surface of other regions of the epitaxial layer outside the first multi-level trench and the second multi-level trench.

[0018] Optionally, in the above semiconductor device, the isolation dielectric layer is a semiconductor film made of metal oxide, and the semiconductor film extends from the second multi-level trench to the first multi-level trench to serve as the first dielectric layer.

[0019] Optionally, in the above semiconductor device, the second field plate metal layer covers a portion of the second dielectric layer on the surface of the second bottom region, and has a distance from the second dielectric layer on the sidewall of the second step.

[0020] Optionally, in the above semiconductor device, the second field plate metal layer extends from the bottom of the first multi-level trench to the sidewall of the second step to cover at least a portion of the second dielectric layer on the surface of the sidewall of the second step.

[0021] Optionally, the semiconductor device further comprises: an ion implantation region located in the bottom surface of the first multi-level trench, the resistivity of the ion implantation region is greater than the resistivity of the epitaxial layer, or the ion implantation region can gather electrons to form a negative charge center.

[0022] Optionally, in the above semiconductor device, an ion implantation region is formed in the bottom surface of each of the first multi-level trenches.

[0023] Optionally, in the above semiconductor device, the bottom of the first multi-level trench has a plurality of separate ion implantation regions;

[0024] At the bottom of the first multi-level groove, the ion injection region below the continuous stacking region of the first dielectric layer and the first field plate metal layer has a first area ratio, and the ion injection region below the continuous stacking region of the first dielectric layer, the second dielectric layer and the second field plate metal layer has a second area ratio, and the first area ratio is greater than the second area ratio.

[0025] Optionally, in the above semiconductor device, the second field plate metal layer covers part of the second dielectric layer on the surface of the second bottom region, and has a distance from the second dielectric layer on the sidewall of the second step;

[0026] The ion implantation region below the gap has a third area ratio, and the third area ratio is greater than the first area ratio.

[0027] Optionally, in the above semiconductor device, the substrate is an n-type doped gallium oxide substrate, the epitaxial layer is an n-type doped gallium oxide epitaxial layer, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer.

[0028] A second aspect of the present application provides a method for preparing any of the above-mentioned semiconductor devices, comprising:

[0029] An epitaxial wafer is provided, wherein the epitaxial wafer comprises a substrate and an epitaxial layer located on the surface of the substrate; in a first direction, the epitaxial layer comprises an active region and a terminal region arranged in sequence; and the first direction is parallel to the plane where the substrate is located;

[0030] A cellular structure is formed in the active region, and a field plate structure is formed within the surface of the terminal region;

[0031] Wherein, a first multi-level trench is formed in the surface of the terminal region; the first multi-level trench has a first step sidewall and a second step sidewall opposite to each other; the first step sidewall is adjacent to the cellular structure; the bottom of the first multi-level trench includes a first bottom region adjacent to the first step sidewall and a second bottom region adjacent to the second step sidewall; the field plate structure includes a first field plate and a second field plate;

[0032] The first-level field plate includes: a first dielectric layer covering the surface of the first multi-level trench; a first field plate metal layer covering the first dielectric layer located on the sidewall of the first step and the surface of the first bottom area;

[0033] The second field plate comprises: a second dielectric layer covering at least the first field plate metal layer and the first dielectric layer in the first multi-level trench; and a second field plate metal layer covering at least part of the second dielectric layer on the surface of the second bottom region.

[0034] Optionally, in the above preparation method, a cellular structure is formed in the active area, and a field plate structure is formed in the surface of the terminal area, comprising:

[0035] Simultaneously forming a first multi-level trench in the surface of the termination region and a second multi-level trench in the surface of the active region;

[0036] forming a first dielectric layer covering the surface of the first multi-level trench and an isolation dielectric layer covering the second multi-level trench;

[0037] A first metal layer is formed, wherein the first metal layer forms a Schottky contact with the epitaxial layer in the active region; the first metal layer covers the isolation dielectric layer and also extends into the first multi-level trench to serve as a first field plate metal layer;

[0038] forming a second dielectric layer, wherein the second dielectric layer covers the first metal layer and the first dielectric layer in the first multi-level trench, and also covers a portion of the first metal layer outside the opening of the first multi-level trench;

[0039] forming a second metal layer, the second metal layer filling the second multi-level trench and electrically contacting the first metal layer to form a first electrode; the second metal layer also extends into the first multi-level trench to serve as a second field plate metal layer;

[0040] A passivation protection layer is formed, and the passivation protection layer fills the first multi-level trenches formed with the second-level field plates and exposes the cellular structure.

[0041] Optionally, in the above preparation method, before forming the first dielectric layer, the method further comprises:

[0042] Ion implantation is performed at the bottom of the first multi-level trench to form an ion implantation region in the bottom surface of the first multi-level trench, wherein the resistivity of the ion implantation region is greater than that of the epitaxial layer, or the ion implantation region can gather electrons to form a negative charge center.

[0043] By means of the above-mentioned technical scheme, in the semiconductor device and the preparation method thereof provided by the present application, a first multi-level groove is arranged in the terminal area, and a first-level field plate and a second-level field plate are formed based on the first multi-level groove. The two-level field plates can better introduce the surface electric field of the device into the interior of the device in the terminal area based on the first multi-level groove, avoid the concentration of the electric field in the edge area of ​​the device plane, and better improve the voltage resistance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0045] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0046] Figure 1 A Ga with a planar field plate structure 2 O 3 Cross-sectional view of the base power device in the terminal area;

[0047] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of the structure of a semiconductor device is provided for an embodiment of the present application;

[0050] Figure 5 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0051] Figure 6 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0052] Figure 7-10 A multi-level trench layout in an active area of ​​a semiconductor device provided in an embodiment of the present application;

[0053] Figure 11-Figure 20 A product structure diagram of different process steps of a semiconductor device manufacturing method provided in an embodiment of the present application.

[0054] Reference numerals:

[0055] 10-active area; 11-substrate; 12-epitaxial layer; 131-first insulating layer; 132-second insulating layer; 141-first field plate metal layer; 142-second field plate metal layer; 15-ion implantation area; 161-first electrode; 162-second electrode; 171-first dielectric layer; 172-isolation dielectric layer; 18-second dielectric layer; 19-passivation protection layer; 20-terminal area; 21-cellular structure; 22-first multi-level groove; 221-first step sidewall; 222-second step sidewall; 223-bottom; 223a-first bottom area; 223b-second bottom area; 23-second multi-level groove; 24-dielectric block; 25-second photoresist layer; 26-first photoresist layer; X-first direction; M1-first metal layer; M2-second metal layer; H-spacing. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0057] A power device is a semiconductor device used to handle high voltage and high current. In power devices, Baliga's figure-of-merit (BFOM) is an indicator used to indicate the applicability of semiconductor materials in power electronics, which is expressed as:

[0058] BFOM=εμE 3

[0059] Among them, ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor.

[0060] BFOM is roughly positively correlated with the sixth power of the bandgap width Eg. Therefore, a larger bandgap width means that wide bandgap semiconductors have lower power loss and higher conversion efficiency in power device applications, thereby achieving more excellent and ideal power electronics applications.

[0061] Among wide bandgap semiconductor materials, Ga 2 O 3 The material has a bandgap of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a BFOM value of up to 3400, which is about 4 times that of GaN and 10 times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga 2 O 3 The material has greater research significance and broader market application prospects.

[0062] Ga2 O 3 The material is easy to achieve n-type doping, but difficult to achieve p-type doping. 2 O 3 The p-type doping process is carried out in the material, which makes Ga 2 O 3 Compared with materials that can be bipolar doped, the application of materials in bipolar power devices is limited. 2 O 3 The terminal area of ​​the Ga-based power device cannot use p-type ion implantation to achieve a field limiting ring terminal structure or a JTE terminal structure like Si-based power devices and SiC-based power devices. 2 O 3 The terminal withstand voltage efficiency of basic power devices is limited and cannot fully utilize the advantages of gallium oxide materials.

[0063] In order to increase Ga 2 O 3 The withstand voltage performance of basic power devices is currently being tested using Figure 1 The flat terminal structure shown.

[0064] refer to Figure 1 , Figure 1 A Ga with a planar field plate structure 2 O 3 The cross-sectional view of the base power device in the terminal area, the power device includes: a substrate 11; an epitaxial layer 12 located on the surface of the substrate 11; a first insulating layer 131 located on the surface of the epitaxial layer 12, the first insulating layer 131 having a first opening exposing the epitaxial layer 12; an ion implantation region 15 formed in the surface of the epitaxial layer 12 exposed by the first opening; a first field plate metal layer 141 covering the ion implantation region 15 and the first insulating layer 131 covering the edges of the first opening; a second insulating layer 132 covering the first insulating layer 131 and the first field plate metal layer 141 located outside the first opening; the second insulating layer 132 having a second opening exposing the first field plate metal layer 141 in the first opening; a second field plate metal layer 142 covering the second insulating layer 132 and the first field plate metal layer 141 exposed by the second opening. The power device also includes an active region ( Figure 1 (not shown), the active region has a first electrode, and a second electrode 162 is provided on the lower surface of the substrate 11.

[0065] The first insulating layer 131 and the second insulating layer 132 may be silicon oxide layers, and the substrate 11 and the epitaxial layer 12 may be n-type doped Ga 2 O 3 .

[0066] exist Figure 1In the power device shown, the stacked region of the first field plate metal layer 141 and the first insulating layer 131 can form a first-level field plate; in the region outside the first field plate metal layer 141, the stacked region of the first insulating layer 131, the second insulating layer 132 and the second field plate metal layer 142 can form a second-level field plate. The power device can transfer the electric field at the contact edge of the metal layer and the gallium oxide to the insulating layer of the field plate through the two-level field plate structure in the terminal region, thereby alleviating the gallium oxide electric field concentration at the metal edge.

[0067] Figure 1 Although the power device shown in the figure can improve the withstand voltage performance to a certain extent by setting a planar field plate structure in the terminal area, the electric field strength in the active area cannot be reduced, especially the surface electric field strength in the active area. Although the surface electric field in the active area can be reduced to a certain extent by injecting elements such as nitrogen (N) into the active area and activating it to form a high resistance area, the barrier height formed by the PN junction is too small, and there will still be a large leakage. Therefore, planar gallium oxide devices will face the problem of reverse off state and large leakage current.

[0068] In order to solve the above problems, an embodiment of the present application provides a semiconductor device, which is provided with a first multi-level groove in the terminal area, and a first-level field plate and a second-level field plate are formed based on the first multi-level groove. The two-level field plates can better introduce the surface electric field of the device into the interior of the device in the terminal area based on the first multi-level groove, avoid the electric field from concentrating in the edge area of ​​the device plane, and better improve the voltage resistance and reliability of the semiconductor device.

[0069] Furthermore, a cellular structure can be formed based on a second multi-level groove located on the surface of the active area, which can provide better dielectric coverage and deeper electric field shielding in the active area, reduce the leakage current of the device in the active area, reduce the JFET effect in the active area, and reduce the on-resistance.

[0070] It should be noted that in the present embodiment, Ga 2 O 3 The basic power device is used as an example for explanation. Obviously, other types of semiconductor devices can also adopt the terminal area structure in the technical solution of the present application, forming a first-level field plate and a second-level field plate based on the first multi-level groove to improve the voltage resistance of the device. In the implementation of the present application, the semiconductor device can be any one of a power diode, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), a thyristor (such as SCR, GTO, etc.) and a silicon carbide device. The embodiment of the present application does not limit the type of semiconductor device.

[0071] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0072] refer to Figure 2 , Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application, wherein the semiconductor device includes:

[0073] The epitaxial wafer includes a substrate 11 and an epitaxial layer 12 located on the surface of the substrate 11; in a first direction X, the epitaxial layer includes an active region 10 and a terminal region 20 arranged in sequence; the first direction X is parallel to the plane where the substrate 11 is located;

[0074] A cellular structure 21, wherein the cellular structure 21 is located in the active area 10;

[0075] A first multi-level groove 22, the first multi-level groove 22 having a first step sidewall 221 and a second step sidewall 222 opposite to each other; the first step sidewall 221 is adjacent to the cellular structure 21; the bottom 223 of the first multi-level groove 22 includes a first bottom region 223a adjacent to the first step sidewall 221 and a second bottom region 223b adjacent to the second step sidewall 222;

[0076] The first-level field plate includes: a first dielectric layer 171, the first dielectric layer 171 covers the surface of the first multi-level groove 22, that is, covers the first step sidewall 221, the second step sidewall 222 and the bottom 223 of the first multi-level groove 22; a first field plate metal layer 141, the first field plate metal layer 141 covers the first dielectric layer 171 located on the first step sidewall 221 and the surface of the first bottom area 223a;

[0077] The second-level field plate includes: a second dielectric layer 18, the second dielectric layer 18 at least covers the first field plate metal layer 141 and the first dielectric layer 171 located in the first multi-level groove 22; a second field plate metal layer 142, the second field plate metal layer 142 covers at least a portion of the second dielectric layer 18 on the surface of the second bottom area 223b, and has an overlapping area with the first field plate metal layer 141.

[0078] like Figure 2 As shown, in the direction perpendicular to the plane where the substrate is located ( Figure 2 In the vertical direction), the second field plate metal layer 142 and the first field plate metal layer 141 have an overlapping area to form a two-level stacked trench field plate structure to better adjust the edge electric field of the semiconductor device in the terminal region 20.

[0079] In the semiconductor device provided in the embodiment of the present application, a first multi-level groove 22 is provided in the terminal region 20, and a first-level field plate and a second-level field plate are formed based on the first multi-level groove 22. The two-level field plates can better introduce the device surface electric field into the interior of the device in the terminal region 20 based on the first multi-level groove 22, avoid the electric field from concentrating in the edge area of ​​the device plane, and better improve the voltage resistance and reliability of the semiconductor device.

[0080] like Figure 2 As shown, the cellular structure 21 includes: a first metal layer M1, the first metal layer M1 is used to form a Schottky contact with the epitaxial layer 12 in the active area 10; the first metal layer M1 also extends into the first multi-level groove 22 to serve as a first field plate metal layer 141; a second metal layer M2, the second metal layer M2 is used to cover at least part of the first metal layer M1 in the active area 10 to form a first electrode 161; the second metal layer M2 also extends into the first multi-level groove 22 to serve as a second field plate metal layer 142. This method uses the first metal layer M1 in the cellular structure 21 to form the first field plate metal layer 141, and uses the second metal layer M2 in the cellular structure 21 to form the second field plate metal layer 142. The metal layer in the active area 10 can be directly used to prepare the field plate metal layer in the terminal area 20, thereby improving the device integration. In one implementation of the embodiment of the present application, the cellular structure 21 can be set as a trench cellular structure. At this time, the implementation method of the cellular structure 21 can be as follows Figure 2 As shown, the surface of the active area 10 has a second multi-level groove 23; the surface of the second multi-level groove 23 is covered with an isolation dielectric layer 172; the first metal layer M1 covers the isolation dielectric layer 172; and the second metal layer M2 fills the second multi-level groove 23. In this manner, the cell structure 21 is formed based on the second multi-level groove 23 located in the surface of the active area 10. Based on the second multi-level groove 23, better dielectric coverage and deeper electric field shielding can be provided in the active area 10, which can make the leakage current of the device in the active area 10 smaller, reduce the JFET effect in the active area, and reduce the on-resistance.

[0081] like Figure 2 As shown, the semiconductor device further includes a passivation protection layer 19, which fills the first multi-level grooves 22 formed with the second-level field plate and exposes the cell structure 21. The passivation protection layer 19 can protect the field plate structure in the terminal region 20 and fill the first multi-level grooves 22, so as to form a relatively flat surface in the terminal region 20. In addition, the surface of the substrate 11 on one side away from the epitaxial layer 12 is also covered with a second electrode 162.

[0082] refer to Figure 3 , Figure 3 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application, based on the above implementation, Figure 3In the semiconductor device shown, the surface of the first metal layer M1 located at the groove corner position of the second multi-level groove 23 is covered with a dielectric block 24. The dielectric block 24 can be used to adjust and optimize the electric field distribution of the device in the active area 10, which can further improve the device performance.

[0083] Optionally, the dielectric block 24 and the second dielectric layer 18 may be formed by etching from the same dielectric material.

[0084] In the embodiment of the present application, the isolation dielectric layer 172 and the first dielectric layer 171 can be the same insulating material film; the insulating material film covers the surface of the first multi-level groove 22 and the surface of the second multi-level groove 23, and exposes the surface of other regions of the epitaxial layer 12 outside the first multi-level groove 22 and the second multi-level groove 23, so that the first metal layer M1 is in Schottky contact with the epitaxial layer 12 on the surface of the epitaxial layer 12 outside the second multi-level groove 23. This method can simultaneously form the isolation dielectric layer 172 and the first dielectric layer 171 based on the same insulating material film, which can simplify the preparation process of the device.

[0085] If the isolation dielectric layer 172 and the first dielectric layer 171 can be the same insulating material film, the isolation dielectric layer 172 covers the surface of the second multi-level trench 23 and exposes the surface of the epitaxial layer 12 outside the second multi-level trench 23; the first dielectric layer 171 covers the surface of the first multi-level trench 22 and exposes the surface of the epitaxial layer 12 outside the first multi-level trench 22.

[0086] refer to Figure 4 , Figure 4 A schematic diagram of the structure of a semiconductor device is provided for the embodiment of the present application. Based on any one of the embodiments of the present application, the isolation dielectric layer 172 is a semiconductor film made of metal oxide, and the semiconductor film extends from the second multi-level groove 23 to the first multi-level groove 22 to serve as the first dielectric layer 171. In this way, the isolation dielectric layer 172 and the first dielectric layer 171 connected in one piece can be formed by the same layer of semiconductor film. Since the semiconductor film and the epitaxial layer 12 are both made of semiconductor materials, the Schottky contact effect of the first metal layer M1 on the surface of the epitaxial layer 12 between the cellular structure 21 and the first multi-level groove 22 is not affected. Therefore, the semiconductor film can be an integrated structure and can extend from the second multi-level groove 23 to the first multi-level groove to serve as the first dielectric layer 171.

[0087] Among them, the semiconductor film can be NiO film, Cu 2 Any of a SnO thin film and a SnO thin film.

[0088] exist Figure 4In the illustrated embodiment, the semiconductor film made of metal oxide can form a heterojunction with the epitaxial layer 12 . Based on the heterojunction, the electric field of the device on the surface of the epitaxial layer and inside the trench can be further optimized to improve the performance of the device.

[0089] In the embodiment of the present application, Figure 4 Based on the manner shown, the surface of the first metal layer M1 located at the groove corner position of the second multi-level groove 23 can also be covered with a dielectric block 24. This embodiment of the present application will not be separately illustrated.

[0090] If the isolation dielectric layer 172 is a semiconductor film made of metal oxide, the semiconductor film directly covers the surface of the first multi-level trench 22 and the surface of the second multi-level trench 23 , and also covers the surface of other regions of the epitaxial layer 12 outside the two multi-level trenches.

[0091] It should be noted that in the embodiment of the present application, a cellular structure 21 of a multi-level groove structure can be formed in the active area 10 based on the second multi-level groove 23. In other methods, the cellular structure 21 can also be set as a conventional planar device cellular structure, which will not be separately described in the embodiment of the present application.

[0092] On the basis of any implementation of the embodiment of the present application, a second field plate metal layer 142 may be provided to cover part of the second dielectric layer 18 on the surface of the second bottom region 223b, and have a spacing H between the second dielectric layer 18 on the second step sidewall 222. At this time, the first-level field plate covers the first region (including the first step sidewall 221 and the first bottom region 223a) of the first multi-level trench 22; the second-level field plate extends from the surface of the first-level trench to the second region (the second bottom region 223b is located outside the spacing H) of the first multi-level trench 22, and has a spacing H between the second dielectric layer 18 on the second step sidewall 222. In this way, the first-level field plate and the second-level field plate can form a step field plate structure at the bottom of the first multi-level trench 22, and can form a more effective electric field adjustment effect at the bottom of the first multi-level trench 22, thereby improving the adjustment effect of the first-level field plate and the second-level field plate on the device edge electric field, thereby better improving the pressure resistance and reliability of the semiconductor device.

[0093] refer to Figure 5 , Figure 5 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application, based on any of the above implementations, Figure 5In the semiconductor device shown, the second field plate metal layer 142 extends from the bottom 223 of the first multi-level trench 22 to the second step sidewall 222 to cover at least a portion of the second dielectric layer 18 on the surface of the second step sidewall 222. In this manner, since the second field plate metal layer 142 also covers at least a portion of the second dielectric layer 18 on the surface of the second step sidewall 222, the electric field adjustment effect of the second-level field plate can be further increased, and the voltage resistance and reliability of the semiconductor device can be improved.

[0094] exist Figure 5 In the illustrated embodiment, the second field plate metal layer 142 covers the second dielectric layer 18 on the surface of the second step sidewall 222 , extends from the second step sidewall 222 to the outside of the first multi-level trench 22 , and also covers the surface of the epitaxial layer 12 outside the first multi-level trench 22 adjacent to the second step sidewall 222 .

[0095] It should be noted that if the second field plate metal layer 142 covers at least a portion of the second dielectric layer 18 on the surface of the second step sidewall 222, the semiconductor device structure is not limited to Figure 5 In the manner shown, Figure 2-Figure 4 In either manner, the second field plate metal layer 142 is disposed to cover at least a portion of the second dielectric layer 18 on the surface of the second step sidewall 222 .

[0096] If the second field plate metal layer 142 also covers at least a portion of the second dielectric layer 18 on the surface of the second step sidewall 222, the second field plate metal layer 142 can cover the second dielectric layer 18 on the entire surface of the second step sidewall 222 and cover the surface of the epitaxial layer 12 adjacent to the second step sidewall 222 outside the first multi-level trench 22; or it can only cover a portion of the second dielectric layer 18 on the surface of the second step sidewall 222 near the bottom 223 and expose a portion of the second dielectric layer 18 on the surface of the second step sidewall 222 near the opening area of ​​the first multi-level trench 22.

[0097] Based on any implementation of the embodiments of the present application, the semiconductor device also includes: an ion implantation region 15, the ion implantation region 15 is located on the bottom 223 surface of the first multi-level groove 22, the resistivity of the ion implantation region 15 is greater than the resistivity of the epitaxial layer, or the ion implantation region 15 can gather electrons to form a negative charge center.

[0098] Since the resistivity of the ion implantation region 15 is greater than that of the epitaxial layer, or the ion implantation region 15 can gather electrons to form a negative charge center, the ion implantation region can be equivalent to a quasi-p-type doped region located on the bottom surface of the first multi-level groove 22. The quasi-p-type doped region can form a PN junction with the n-type doped epitaxial layer 12 at the bottom 223 of the first multi-level groove 22. When the semiconductor device is in a reverse bias, the electric field in the dielectric layer on the surface of the bottom 223 of the first multi-level groove 22 can be reduced, and the dielectric layer on the surface of the bottom 223 of the first multi-level groove 22 can be protected to prevent the dielectric layer from breaking down in the bottom region of the first multi-level groove 22.

[0099] In one implementation of the present application, the bottom 223 of the first multi-level trench 22 may be provided with an ion implantation region 15. Figure 2-Figure 5 As shown in any of the above methods, the bottom 223 of the first multi-level groove 22 is formed with an integrated ion implantation region 15, and the ion implantation region 15 covers the entire bottom 223 of the first multi-level groove 22. In this method, the first multi-level groove 22 can be directly used as an ion implantation window, and a self-aligned ion implantation region can be directly performed based on the first multi-level groove 22, so that an integrated ion implantation region 15 can be formed in the surface of the bottom 223 of the first multi-level groove 22, without the need for a separate ion implantation region mask process, thereby reducing the complexity of the device manufacturing process.

[0100] refer to Figure 6 , Figure 6 A structural schematic diagram of another semiconductor device provided in an embodiment of the present application, based on any of the above-mentioned implementation modes, if an ion implantation region 15 is formed in the surface of the bottom 223 of the first multi-level trench 22, a plurality of separate ion implantation regions 15 may be provided at the bottom 223 of the first multi-level trench 22.

[0101] Compared with forming a large-sized ion implantation area 15 covering the entire bottom 223 on the surface of the bottom 223 of the first multi-level groove 22, a plurality of separated ion implantation areas 15 are formed on the surface of the bottom 223 of the first multi-level groove 22. By setting the size and distribution interval of each ion implantation area 15, the bottom electric field distribution of the first multi-level groove 22 can be more flexibly adjusted through the ion implantation area 15 to further optimize the device performance.

[0102] If the bottom 223 of the first multi-level trench 22 has a plurality of separate ion implantation regions 15, in one embodiment, the ion implantation regions 15 may be formed as follows: Figure 6 As shown, a plurality of ion implantation regions 15 are uniformly distributed on the surface of the bottom 223 of the first multi-level trench 22 .

[0103] If the bottom 223 of the first multi-level groove 22 has a plurality of separated ion implantation regions 15, in another embodiment, a plurality of ion implantation regions 15 may be arranged to be unevenly distributed on the surface of the bottom 223 of the first multi-level groove 22. This method may more flexibly control the size and distribution interval of each ion implantation region 15, and may more flexibly adjust the bottom electric field distribution of the first multi-level groove 22 through the ion implantation region 15 to further optimize the device performance.

[0104] When the plurality of ion implantation regions 15 are non-uniformly distributed on the surface of the bottom 223 of the first multi-level groove 22, the ion implantation region 15 located below the continuous stacking region of the first dielectric layer 171 and the first field plate metal layer 141 (the first field plate control region formed by the first field plate at the bottom of the groove) at the bottom 223 of the first multi-level groove 22 has a first area ratio, and the ion implantation region 15 located below the continuous stacking region of the first dielectric layer 171, the second dielectric layer 18 and the second field plate metal layer 142 (the first field plate control region formed by the second field plate at the bottom of the groove) has a second area ratio, and the first area ratio is greater than the second area ratio. Among them, in the first multi-level groove 22, the second field plate metal layer 142 is located on the surface of the first field plate metal layer 141, which will be shielded by the first field plate metal layer 141, so the effective electric field control region of the second field plate is the region where the first dielectric layer 171, the second dielectric layer 18 and the second field plate metal layer 142 are continuously stacked.

[0105] In the embodiment of the present application, the first area ratio is set to be greater than the second area ratio, so that below the first-level field plate control region, an ion implantation region 15 with a larger area ratio can be formed to better protect the first dielectric layer 171 with a relatively thin thickness between the first field plate metal layer 141 and the epitaxial layer 12. In the second-level field plate control region, since the second field plate metal layer 142 has two stacked dielectric layers (the first dielectric layer 171 and the second dielectric layer 18) between the epitaxial layer 12, and the dielectric layer thickness is relatively large, an ion implantation region 15 with a relatively small area ratio can be used.

[0106] If the second field plate metal layer 142 covers part of the second dielectric layer 18 on the surface of the second bottom region 223b, and has a spacing H with the second dielectric layer 18 on the second step sidewall 222; the ion implantation region 15 below the spacing H is set to have a third area ratio, and the third area ratio is greater than the first area ratio. In this way, since there is no field plate structure in the region corresponding to the spacing H, the third area ratio is set to be greater than the first area ratio, and an ion implantation region 15 with a larger area ratio can be formed in the region, so that a PN junction with a larger area ratio can be formed in the region through the ion implantation region 15 and the epitaxial layer 12, and the electric field in the dielectric layer on the surface of the region can be more effectively reduced when the semiconductor device is in reverse bias. In this way, even if there is no field plate protection in the region, the dielectric layer above the cover region can be effectively protected to prevent the dielectric layer from being broken down in the region.

[0107] Based on any of the above implementations, in the embodiment of the present application, the substrate 11 is an n-type doped gallium oxide substrate, the epitaxial layer 12 is an n-type doped gallium oxide epitaxial layer, and the doping concentration of the substrate 11 is greater than the doping concentration of the epitaxial layer 12. In this way, when the semiconductor device is a power device, the technical solution of the embodiment of the present application can effectively improve the Ga 2 O 3 Furthermore, the ion implantation region 15 can be used to improve the withstand voltage performance of the Ga 2 O 3 A p-type doped region is formed in the epitaxial layer 12 of the material to solve the problem of Ga 2 O 3 The problem that it is difficult to achieve p-type doping of the material can be solved by further improving the voltage resistance of the device through the ion implantation area 15, which can compensate for the influence of the lack of p-type doping on the device in the current potassium oxide device to a certain extent.

[0108] In the embodiment of the present application, the layout of the cellular structure 21 can be arranged in the active area 10 according to the requirements. The layout of the cellular structure 21 includes but is not limited to Figure 7-10 The method shown.

[0109] refer to Figure 7-10 , Figure 7-10 The multi-level trench layout of the semiconductor device in the active area provided in the embodiment of the present application. In order to clearly illustrate the layout of the second multi-level trench 23 in the active area 10, Figure 7-10 Only a top view of the epitaxial layer 12 in the semiconductor device and the opening pattern of the second multi-level trench 23 on the surface of the epitaxial layer 12 is shown, and other structures in the semiconductor device are not shown.

[0110] exist Figure 7 In the illustrated embodiment, the active region 10 has a plurality of second multi-level trenches 23 arranged in an array, and each level of the second multi-level trenches 23 is a circular structure.

[0111] exist Figure 8 In the illustrated embodiment, the active region 10 has a plurality of second multi-level trenches 23 arranged in an array, and each level of the second multi-level trenches 23 has a rectangular structure or a rounded rectangular structure. Fig. 9 In the illustrated embodiment, the active region 10 has a plurality of second multi-level trenches 23 arranged in an array, and each level of the second multi-level trenches 23 is a pentagonal structure.

[0112] exist Fig.10 In the illustrated embodiment, the active region 10 has a plurality of second multi-level trenches 23 arranged in parallel rows. The plurality of second multi-level trenches 23 may be arranged at intervals along the first direction X. The second multi-level trenches 23 are rectangular structures.

[0113] It can be known from the above description that the semiconductor device provided in the embodiment of the present application can form a cellular structure 21 of a multi-level groove structure based on the second multi-level groove 23 in the active area 10, which can shield the electric field on the surface of the device and reduce the leakage current of the device, thereby solving the problem that the planar field plate device cannot solve the problem of electric field weakening in the active area. In addition, the first-level field plate and the second-level field plate can be formed in the terminal area 20 based on the first multi-level groove 22, which can more effectively improve the terminal withstand voltage of the device. Therefore, the technical solution of the embodiment of the present application can make the entire device have lower leakage current and higher withstand voltage.

[0114] In the semiconductor device provided by the embodiment of the present application, in the active area 10, a cellular structure 21 of a multi-level groove structure can be formed by the second multi-level groove 23, and the second multi-level groove 23 can make the isolation dielectric layer 172 cover the groove sidewall more uniformly. In addition, an electric field dispersion point can be formed at the bottom of each level of the second multi-level groove 23, so based on the second multi-level groove 23, multiple electric field dispersion points are formed in the active area 10. Compared with the single-level groove cellular structure, the cellular structure 21 of the multi-level groove can avoid electric field concentration through multiple electric field dispersion points, thereby preventing the isolation dielectric layer 172 from being broken down. In the direction from the substrate 11 to the epitaxial layer 12, since the width of each level of the groove in the multi-level groove increases successively, when the device is forward-conducted, the current conduction path in the active area 10 becomes larger as the width of each level of the groove increases step by step, so compared with the single-level groove of the same depth, the cellular structure 21 of the multi-level groove structure has a smaller on-resistance. Moreover, compared with the single-level trench structure, the cellular structure 21 of the multi-level trench structure can form a deeper reverse shielding effect and reduce reverse leakage.

[0115] In the terminal region 20, the semiconductor device forms a two-level field plate structure based on the first multi-level groove 22. The multi-level grooves can be formed simultaneously in the terminal region 20 and the active region 10, which can simplify the preparation process. The terminal region 20 can effectively improve the voltage resistance of the device through the two-level field plate of the multi-level groove structure. Compared with the flat field plate structure, the two-level field plate of the multi-level groove structure can reduce the lateral distance with the cellular structure 21 by covering the part of the first step side wall by the first-level field plate, so that the distance between the field plate structure and the cellular structure 21 is shorter, which is conducive to reducing the electric field strength at the edge of the active region 10 and improving the reliability of the device.

[0116] Based on any of the semiconductor devices provided in the above embodiments, another embodiment of the present application further provides a method for preparing a semiconductor device, which can be used to prepare the semiconductor device provided in the above embodiments. Figure 11-Figure 20 shown.

[0117] refer to Figure 11-Figure 20 , Figure 11-Figure 20 A product structure diagram of a semiconductor device manufacturing method at different process steps provided in an embodiment of the present application, the manufacturing method comprising:

[0118] Step S11: Fig.11 As shown, an epitaxial wafer is provided, which includes a substrate 11 and an epitaxial layer 12 located on the surface of the substrate 11; in a first direction X, the epitaxial layer 12 includes an active area 10 and a terminal area 20 arranged in sequence; the first direction X is parallel to the plane where the substrate 11 is located.

[0119] The substrate 11 may be an n-type doped gallium oxide substrate, and the epitaxial layer 12 may be an n-type doped gallium oxide epitaxial layer. The doping concentration of the substrate 11 is two orders of magnitude higher than that of the epitaxial layer 12. The doping concentration of the epitaxial layer 12 may be 1×10 15 cm -3 ~2×10 17 cm -3 , such as 2×10 16 cm -3 The thickness of the epitaxial layer 12 may be 3 μm to 15 μm, such as 10 μm. The epitaxial layer 12 may be formed on the surface of the substrate 11 by a HVPE (halide vapor phase epitaxy) process.

[0120] Step S12: Figure 12-Figure 20 As shown, a cell structure 21 is formed in the active region 10 , and a field plate structure is formed in the surface of the terminal region 20 .

[0121] A first multi-level groove 22 is formed in the surface of the terminal region 20; the first multi-level groove 22 has a first step sidewall 221 and a second step sidewall 222 opposite to each other; the first step sidewall 221 is adjacent to the cellular structure 21; the bottom 223 of the first multi-level groove 22 includes a first bottom region 223a adjacent to the first step sidewall 221 and a second bottom region 223b adjacent to the second step sidewall 222. The lengths of the first bottom region 223a and the second bottom region 223b in the first direction X may be the same or different. The field plate structure includes a first field plate and a second field plate.

[0122] The first-level field plate includes: a first dielectric layer 171, covering the surface of the first multi-level groove 22; a first field plate metal layer 141, covering the first dielectric layer located on the sidewall of the first step and the surface of the first bottom area. The second-level field plate includes: a second dielectric layer 18, covering at least the first field plate metal layer 141 and the first dielectric layer 171 located in the first multi-level groove 22; a second field plate metal layer 142, and the second field plate metal layer 142 covers at least a portion of the second dielectric layer 18 on the surface of the second bottom area 223b.

[0123] The method of forming the cell structure 21 in the active region 10 and forming the field plate structure in the surface of the terminal region 20 is as follows: Figure 12-Figure 20 As shown, including:

[0124] Step S21: Fig.12 As shown, a first multi-level trench 22 is simultaneously formed in the surface of the terminal region 20, and a second multi-level trench 23 is simultaneously formed in the surface of the active region 10. In the embodiment of the present application, the first multi-level trench 22 and the second multi-level trench 23 are both two-level trenches.

[0125] To facilitate the process preparation, the first multi-level groove 22 and the second multi-level groove 23 are both N-level groove structures, where N is any positive integer greater than 1, and is not limited to N being equal to 2. In this way, the first multi-level groove 22 and the second multi-level groove 23 can be prepared in the same process steps, which can simplify the preparation process.

[0126] A patterned silicon oxide or silicon nitride film is prepared on the upper surface of the epitaxial wafer to form a hard mask on the surface of the epitaxial layer 12. The epitaxial layer 12 is etched based on the hard mask to form a first multi-level groove 22 in the surface of the terminal area 20 and a second multi-level groove 23 in the surface of the active area 10.

[0127] Step S22: Figure 13-Figure 15 As shown, a first dielectric layer 171 covering the surface of the first multi-level trench 22 and an isolation dielectric layer 172 covering the second multi-level trench 23 are formed.

[0128] In this step, first, Fig.13As shown, ion implantation is performed at the bottom 223 of the first multi-level groove 22 to form an ion implantation region 15 within the surface of the bottom 223 of the first multi-level groove 22. As mentioned above, the resistivity of the ion implantation region 15 is greater than the resistivity of the epitaxial layer 12, or the ion implantation region 15 can gather electrons to form a negative charge center.

[0129] Optionally, at least one of the element ions of N, F, P, Mg and Be can be implanted into the surface of the bottom 223, and the doped ions can be activated to form a high resistance or negative charge center, thereby forming an ion implantation region 15. If the implanted element includes at least one of N, P, Be and Mg, a high resistance ion implantation region 15 can be formed, and if the implanted element includes F, an ion implantation region with a negative charge center can be formed.

[0130] Then, if Fig.14 As shown, an insulating material film can be formed on the surface of the epitaxial layer 12 by an ALD (atomic layer 2) epitaxial process. The insulating material film can be Al 2 O 3 Or Si 3 N 4 Thin film. The thickness of the insulating material thin film can be 100nm.

[0131] Finally, if Fig.15 As shown, a first photoresist layer 26 is applied to the epitaxial layer 12 and planarized, and then the first photoresist layer 26 and the insulating material film outside the multi-level grooves are removed to expose the epitaxial layer 12 outside the multi-level grooves. In this way, the portion of the insulating material film retained in the first multi-level grooves 22 is used as the first dielectric layer 171, and the portion retained in the second multi-level grooves 23 is used as the isolation dielectric layer 172.

[0132] The isolation dielectric layer 172 can prevent leakage caused by direct contact between the metal formed in the second multi-level trench 23 and the epitaxial layer 12 in the subsequent process. The first dielectric layer 171 can be used to form a field plate structure in the terminal region 20, which can protect the active region 10 when the device works in reverse.

[0133] exist Figure 13-Figure 15 In the illustrated method, an example of preparing the first dielectric layer 171 and the isolation dielectric layer 172 using an insulating material film is used for explanation. If a semiconductor film is used to prepare the first dielectric layer 171 and the isolation dielectric layer 172, the first dielectric layer 171 and the isolation dielectric layer 172 may be integrally connected, and in this case, the semiconductor films in the active region 10 and the terminal region 20 do not need to be etched and separated.

[0134] Step S23: Fig.16 and Fig.17As shown, a first metal layer M1 is formed, and the first metal layer M1 forms a Schottky contact with the epitaxial layer 12 in the active area 10 ; the first metal layer M1 covers the isolation dielectric layer 172 and also extends into the first multi-level trench 22 to serve as a first field plate metal layer 141 .

[0135] In this step, after removing the first photoresist layer 26 in the multi-level grooves, first, Fig.16 As shown, a patterned second photoresist layer 25 is formed, and the second photoresist layer 25 covers the second bottom region 223 b and the first dielectric layer 171 on the surface of the second step sidewall 222 , and exposes other regions of the epitaxial wafer.

[0136] Then, a first metal layer M1 is deposited on the epitaxial wafer based on the second photoresist layer 25, and the first metal layer M1 covers the surface of the second multi-level groove 23 and extends into the first multi-level groove 22, covering the first step sidewall 221 and the first bottom area 223a. Optionally, the first metal layer M1 can be a Ni layer with a thickness of 100 nm.

[0137] Finally, if Fig.17 As shown, the second photoresist layer 25 is removed. The first metal layer M1 can be prepared by evaporation process. After the first metal layer M1 is formed, the second photoresist layer 25 and the first metal layer M1 on the surface are removed by stripping process, and the first metal layer M1 in other areas is retained.

[0138] Step S24: Fig.18 As shown, a second dielectric layer 18 is formed, which covers the first metal layer M1 and the first dielectric layer 171 in the first multi-level trench 22 and also covers part of the first metal layer M1 outside the opening of the first multi-level trench 22 ; the second dielectric layer 18 is located outside the second multi-level trench 23 .

[0139] A second dielectric layer 18 covering the entire epitaxial wafer may be formed, and then an opening may be formed in the second dielectric layer 18 to expose the second multi-level trench 23 and the epitaxial layer 12 around the opening. The second dielectric layer 18 may be a silicon oxide layer with a thickness of 1 μm.

[0140] Step S25: Fig.19 As shown, a second metal layer M2 is formed, which fills the second multi-level trench 23 and electrically contacts the first metal layer M1 to form a first electrode 161 ; the second metal layer M2 also extends into the first multi-level trench 22 to serve as a second field plate metal layer 142 .

[0141] Optionally, the thickness of the second metal layer M2 is greater than that of the first metal layer M1. The second metal layer can increase the thickness of the front metal layer in the active area, thereby preventing the first electrode 161 from being burned by heat generated by a large current due to the thin metal layer.

[0142] The second metal layer M2 includes a Ni layer-Ti layer-Al layer formed in sequence, the thickness of the Ni layer may be 100 nm, the thickness of the Ti layer may be 300 nm, and the thickness of the Al layer may be 1000 nm. Similarly, the second metal layer M2 may be prepared based on a pre-prepared photoresist layer. After the second metal layer M2 is formed by evaporation, a stripping process is used to remove the photoresist layer and the second metal layer M2 on its surface, and the second metal layer M2 in other areas is retained.

[0143] Step S26: Fig. 20 As shown, a passivation protection layer 19 is formed, and the passivation protection layer 19 fills the first multi-level trench 22 formed with the second-level field plate and exposes the cell structure 21. The passivation protection layer 19 can be silicon oxide.

[0144] After forming the passivation protection layer 19, a second electrode 162 is formed on the lower surface of the substrate 11, and finally a Figure 3 The semiconductor device shown. The second electrode 162 may include a Ti layer-Au layer grown in sequence, the thickness of the Ti layer may be 20 nm, and the thickness of the Au layer may be 80 nm. After the second electrode 162 is formed, an annealing process may be performed so that the second electrode 162 and the substrate 11 form a good ohmic contact. The annealing temperature may be 470° C., and the annealing time may be 1 min.

[0145] The preparation methods of semiconductor devices with other structures in the embodiments of the present application can refer to Figure 3 The method for preparing the semiconductor device shown is not described in detail in the embodiments of the present application.

[0146] From the above description, it can be seen that the preparation method provided in the embodiment of the present application can be used to prepare the semiconductor device provided in any implementation mode of the above embodiments, and can form a device structure with multi-level grooves and double-level field plates, which can effectively improve the voltage resistance performance of the device.

[0147] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0148] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0149] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0150] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0151] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, characterized in that: include: An epitaxial wafer, the epitaxial wafer comprising a substrate and an epitaxial layer located on a surface of the substrate; in a first direction, the epitaxial layer comprises an active region and a terminal region arranged in sequence; The first direction is parallel to the plane where the substrate is located; A cellular structure, wherein the cellular structure is located in the active area; a first multi-level groove, the first multi-level groove having a first step sidewall and a second step sidewall opposite to each other; the first step sidewall is adjacent to the cellular structure; the bottom of the first multi-level groove includes a first bottom region adjacent to the first step sidewall and a second bottom region adjacent to the second step sidewall; A first-level field plate, the first-level field plate comprising: a first dielectric layer covering the surface of the first multi-level trench; a first field plate metal layer covering the first dielectric layer located on the sidewall of the first step and the surface of the first bottom area; a second-level field plate, the second-level field plate comprising: a second dielectric layer, at least covering the first field plate metal layer and the first dielectric layer in the first multi-level trench; a second field plate metal layer, the second field plate metal layer covering at least a portion of the second dielectric layer on the surface of the second bottom region, and having an overlapping region with the first field plate metal layer; An ion implantation region is located in the bottom surface of the first multi-level groove, the resistivity of the ion implantation region is greater than the resistivity of the epitaxial layer, or the ion implantation region can gather electrons to form a negative charge center; the bottom of the first multi-level groove has a plurality of separated ion implantation regions; at the bottom of the first multi-level groove, the ion implantation region located below the continuous stacking region of the first dielectric layer and the first field plate metal layer has a first area ratio, and the ion implantation region located below the continuous stacking region of the first dielectric layer, the second dielectric layer and the second field plate metal layer has a second area ratio, and the first area ratio is greater than the second area ratio.

2. The semiconductor device according to claim 1, wherein: The cellular structure comprises: A first metal layer, used to form a Schottky contact with the epitaxial layer in the active area; the first metal layer also extends into the first multi-level trench to serve as the first field plate metal layer; The second metal layer is used to cover at least a portion of the first metal layer in the active area to form a first electrode; the second metal layer also extends into the first multi-level trench to serve as the second field plate metal layer.

3. The semiconductor device according to claim 2, characterized in that The surface of the active area has a second multi-level groove; the surface of the second multi-level groove is covered with an isolation dielectric layer; The first metal layer covers the isolation dielectric layer; and the second metal layer fills the second multi-level trenches.

4. The semiconductor device according to claim 3, characterized in that The isolation dielectric layer and the first dielectric layer are made of the same insulating material film; The insulating material film covers the surface of the first multi-level trench and the surface of the second multi-level trench, and exposes the surface of other regions of the epitaxial layer outside the first multi-level trench and the second multi-level trench.

5. The semiconductor device according to claim 3, characterized in that The isolation dielectric layer is a semiconductor film made of metal oxide. The semiconductor film extends from the second multi-level trench to the first multi-level trench to serve as the first dielectric layer.

6. The semiconductor device according to claim 1, wherein: The second field plate metal layer covers a portion of the second dielectric layer on the surface of the second bottom region, and has a distance from the second dielectric layer on the sidewall of the second step.

7. The semiconductor device according to claim 1, wherein: The second field plate metal layer extends from the bottom of the first multi-level trench to the sidewall of the second step to cover at least a portion of the second dielectric layer on the surface of the sidewall of the second step.

8. The semiconductor device according to claim 1, wherein: The ion implantation region is formed in the bottom surface of each of the first multi-level trenches.

9. The semiconductor device according to claim 1, wherein: The second field plate metal layer covers a portion of the second dielectric layer on the surface of the second bottom region, and has a distance from the second dielectric layer on the sidewall of the second step; The ion implantation region below the gap has a third area ratio, and the third area ratio is greater than the first area ratio.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The substrate is an n-type doped gallium oxide substrate, the epitaxial layer is an n-type doped gallium oxide epitaxial layer, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer.

11. A method for preparing a semiconductor device according to any one of claims 1 to 10, characterized in that: include: Providing an epitaxial wafer, the epitaxial wafer comprising a substrate and an epitaxial layer located on a surface of the substrate; in a first direction, the epitaxial layer comprises an active region and a terminal region arranged in sequence; The first direction is parallel to the plane where the substrate is located; forming a cell structure in the active region and forming a field plate structure in the surface of the terminal region; Wherein, a first multi-level trench is formed in the surface of the terminal region; the first multi-level trench has a first step sidewall and a second step sidewall opposite to each other; the first step sidewall is adjacent to the cellular structure; the bottom of the first multi-level trench includes a first bottom region adjacent to the first step sidewall and a second bottom region adjacent to the second step sidewall; the field plate structure includes a first field plate and a second field plate; The first-level field plate includes: a first dielectric layer covering the surface of the first multi-level trench; a first field plate metal layer covering the first dielectric layer located on the sidewall of the first step and the surface of the first bottom area; A second-level field plate, the second-level field plate comprising: a second dielectric layer, at least covering the first field plate metal layer and the first dielectric layer located in the first multi-level trench; a second field plate metal layer, the second field plate metal layer covering at least a portion of the second dielectric layer on the surface of the second bottom region; Among them, before forming the first dielectric layer, it also includes: performing ion implantation at the bottom of the first multi-level groove to form an ion implantation area in the bottom surface of the first multi-level groove, the resistivity of the ion implantation area is greater than the resistivity of the epitaxial layer, or the ion implantation area can gather electrons to form a negative charge center; the bottom of the first multi-level groove has a plurality of separated ion implantation areas; at the bottom of the first multi-level groove, the ion implantation area located below the continuous stacking area of ​​the first dielectric layer and the first field plate metal layer has a first area ratio, and the ion implantation area located below the continuous stacking area of ​​the first dielectric layer, the second dielectric layer and the second field plate metal layer has a second area ratio, and the first area ratio is greater than the second area ratio.

12. The preparation method according to claim 11, characterized in that: A cell structure is formed in the active region, and a field plate structure is formed on the surface of the terminal region, including: Simultaneously forming the first multi-level trenches in the surface of the termination region and forming the second multi-level trenches in the surface of the active region; forming a first dielectric layer covering the surface of the first multi-level trench and an isolation dielectric layer covering the second multi-level trench; forming a first metal layer, wherein the first metal layer forms a Schottky contact with the epitaxial layer in the active area; the first metal layer covers the isolation dielectric layer and extends into the first multi-level trench to serve as the first field plate metal layer; forming a second dielectric layer, wherein the second dielectric layer covers the first metal layer and the first dielectric layer in the first multi-level trench, and also covers a portion of the first metal layer outside the opening of the first multi-level trench; forming a second metal layer, wherein the second metal layer fills the second multi-level grooves and is in electrical contact with the first metal layer to form a first electrode; the second metal layer also extends into the first multi-level grooves to serve as the second field plate metal layer; A passivation protection layer is formed, wherein the passivation protection layer fills the first multi-level trenches formed with the second-level field plates and exposes the cellular structure.

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