Manufacturing method of metal gate transistor

Abstract

The invention discloses a manufacturing method of a metal gate transistor, which comprises the following steps of: completing a metal gate process flow to form a metal gate which contains Cl; and forming an interlayer film. And forming the contact hole, which comprises the following sub-steps of: carrying out graphical etching to form an opening of the contact hole. And performing heat treatment to reduce the Cl content in the metal gate. And depositing an adhesion barrier layer, wherein the adhesion barrier layer comprises a first Ti layer and a second TiN layer which are stacked in sequence. And performing metal silicification reaction to enable the first Ti layer in contact with silicon to form TiSi, and reducing the content of Cl in the metal gate to ensure that the first Ti layer at the top of the metal gate does not form a cavity under the action of Cl in the metal silicification reaction. And filling metal in the contact hole opening to form a contact hole. The stability of the metal gate can be improved.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a metal gate (MG) transistor. Background Art

[0002] Since atomic layer deposition (ALD) TiN is deposited by the reaction of titanium tetrachloride (TiCl4) and NH3, the formed metal film will contain Cl elements. The presence of Cl elements will have a significant negative effect on the device stability of the MG process (loop).

[0003] For example, in the MG barrier metal layer, after the high-temperature process of the subsequent TiSi formation, the Cl in the barrier metal TiN will volatilize to the bottom of the contact hole (CT) and be adsorbed by the Ti in the contact glue layer to form a void. This defect will seriously affect the conductive resistance of the CT hole and the stability of the MG.

[0004] like Figure 1A to Figure 1B FIG. 1 is a schematic diagram of a device structure in each step of a conventional method for manufacturing a metal gate transistor; the conventional method for manufacturing a metal gate transistor comprises the following steps:

[0005] like Figure 1A As shown, the metal gate 102 process flow is completed to form the metal gate 102, and the metal gate 102 is formed in the gate trench between the zero-th interlayer film. Figure 1A In the embodiment, the zeroth interlayer film includes a portion of the thickness of the oxide layer 104, and a silicon nitride layer 103 is formed at the bottom of the oxide layer 104. The metal gate 102 includes a TiN layer formed by an ALD process, and the reactants include TiCl4 and NH3, so that the ALD TiN layer contains Cl.

[0006] An interlayer film is formed, and the interlayer film covers the metal gate 102 and the top surface of the zeroth interlayer film. Figure 1A In FIG. 1 , the interlayer film includes a top portion of an oxide layer 104 , a silicon nitride layer 105 , and an oxide layer 106 .

[0007] The contact hole 109 is formed, including the following steps:

[0008] like Figure 1A As shown, pattern etching is performed to form a contact hole opening 107, and the contact hole opening 107 passes through the corresponding interlayer film or the bottom zeroth interlayer film. For the corresponding semiconductor device, an active region and a drain region are formed in the semiconductor substrate 101 on both sides of the metal gate 102, and corresponding contact hole openings 107 are formed on the top of the metal gate 102, the source region, and the drain region. Figure 1A Only the contact hole opening 107 at the top of the metal gate 102 is shown. In the prior art, the contact hole opening 107 at the top of the source region and the drain region will expose the surface of the bottom semiconductor substrate 101. The semiconductor substrate 101 includes a silicon substrate.

[0009] like Figure 1B As shown, an adhesion barrier layer 108 is deposited, and the adhesion barrier layer 108 includes a Ti layer and a TiN layer stacked in sequence.

[0010] The metal silicide reaction is performed to form TiSi in the Ti layer in contact with silicon, wherein the Ti layer in the contact hole opening 107 at the top of the source region and the drain region reacts with the metal silicon in the semiconductor substrate 101 at the bottom to form TiSi.

[0011] In the metal silicidation reaction, Cl in the metal gate diffuses upward, and the Ti layer and Cl react to form Ti Cl compounds such as TiCl 4 after contacting each other. After TiCl 4 volatilizes, a cavity 110 is formed.

[0012] A metal is filled in the contact hole opening 107 to form a contact hole 109 .

[0013] like Figure 2 , is a photograph of a contact hole on top of a metal gate formed by a conventional method for manufacturing a metal gate transistor; it can be seen that there is a void in a region 110a between the contact hole and the metal gate.

[0014] In addition, the Cl element will block the diffusion of Al. For NMOS, the diffusion of Al is an important factor in adjusting Vt. Too high Cl content will seriously affect the device performance of NMOS.

[0015] Therefore, regardless of defects or electrical properties, reducing the content of Cl elements has always been the direction of research and development. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide a method for manufacturing a metal gate transistor, which can increase the stability of the metal gate.

[0017] In order to solve the above technical problems, the present invention provides a method for manufacturing a metal gate transistor, comprising the following steps:

[0018] A metal gate process flow is completed to form a metal gate, wherein the metal gate contains Cl.

[0019] An interlayer film is formed, the interlayer film covering the metal gate and top surfaces of the zeroth interlayer film.

[0020] The contact hole is formed, comprising the following steps:

[0021] Patterned etching is performed to form a contact hole opening, wherein the contact hole opening passes through the corresponding interlayer film or the zeroth interlayer film at the bottom.

[0022] A heat treatment is performed to reduce the Cl content in the metal gate.

[0023] An adhesion barrier layer is deposited, the adhesion barrier layer including a first Ti layer and a second TiN layer stacked in sequence.

[0024] A metal silicidation reaction is performed to form TiSi in the first Ti layer in contact with silicon, and the Cl content in the metal gate is reduced to ensure that in the metal silicidation reaction, the first Ti layer on the top of the metal gate will not form a cavity under the action of Cl.

[0025] The contact hole is formed by filling metal in the contact hole opening.

[0026] A further improvement is that the metal gate is formed in a gate trench located between the zeroth interlayer film, and a gate dielectric layer is separated between the metal gate and the surface of the semiconductor substrate; the metal gate includes a bottom barrier layer, a metal work function layer, a top barrier layer and a gate conductive material layer.

[0027] The bottom barrier layer includes a first TiN layer, which is formed by an ALD process. Reactants for forming the first TiN layer include TiCl 4 and NH 3 , and the first TiN layer contains Cl.

[0028] A further improvement is that the bottom barrier layer further includes a first TaN layer and the bottom barrier layer is formed by stacking the first TiN layer and the first TaN layer.

[0029] A further improvement is that the top barrier layer is composed of a third TiN layer or a stacked layer of a third TiN layer and a second Ti layer; the third TiN layer is also formed by an ALD process and contains Cl.

[0030] A further improvement is that the metal gate transistor includes NMOS and PMOS.

[0031] In the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer, the material of the P-type metal work function layer includes TiN, and the TiN of the P-type metal work function layer is also formed by ALD process and contains Cl.

[0032] A further improvement is that, in the NMOS formation region, the metal work function layer of the metal gate adopts an N-type metal work function layer.

[0033] A further improvement is that the material of the N-type metal work function layer includes TiAl.

[0034] A further improvement is that the metal filled in the contact hole opening includes Co.

[0035] A further improvement is that the step of filling the contact hole opening with metal to form the contact hole comprises:

[0036] A Co seed layer is formed.

[0037] An electroplating process is performed to form a Co main layer, wherein the Co main layer completely fills the interior of the contact hole opening and extends to the outer surface of the contact hole opening.

[0038] A chemical mechanical polishing process is performed to remove the Co bulk layer on the outer surface of the contact hole opening and to make the Co bulk layer only located in the contact hole opening.

[0039] A further improvement is that the heat treatment includes: dynamic surface annealing, spike annealing, and rapid thermal treatment.

[0040] The present invention adds a step of heat treatment to reduce the Cl content in the metal gate after the contact hole opening is formed and before the adhesion barrier layer is deposited. The heat treatment at this time can timely remove the Cl in the metal gate before the first Ti layer of the adhesion barrier layer is deposited, thereby preventing the Cl in the metal gate from diffusing to the bottom area of ​​the contact hole at the top of the metal gate and reacting with Ti to form Ti Cl compounds such as TiCl4 in the subsequent metal silicidation reaction. After TiCl4 volatilizes at high temperature, the area where Ti is lost will become a cavity. Therefore, the present invention can prevent the formation of voids, which can increase the stability of the metal gate and prevent the on-resistance at the bottom of the contact hole from increasing.

[0041] For NMOS, the present invention can facilitate the normal diffusion of Al in the metal gate of NMOS by reducing the Cl content in the metal gate, and can prevent the threshold voltage of NMOS and corresponding device performance from being affected when the Cl content is too high. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0043] Figure 1A-1B It is a schematic diagram of the device structure in each step of the manufacturing method of the existing metal gate transistor;

[0044] Figure 2 is a photograph of a contact hole on top of a metal gate formed by a conventional method for manufacturing a metal gate transistor;

[0045] Figure 3 is a flow chart of a method for manufacturing a metal gate transistor according to an embodiment of the present invention;

[0046] Figure 4A-4BIt is a schematic diagram of the device structure in each step of the method for manufacturing a metal gate transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] like Figure 3 FIG. 1 is a flow chart of a method for manufacturing a metal gate transistor according to an embodiment of the present invention; FIG. 4A to FIG. 4B FIG. 1 is a schematic diagram of a device structure in each step of a method for manufacturing a metal gate transistor according to an embodiment of the present invention; the method for manufacturing a metal gate transistor according to an embodiment of the present invention comprises the following steps:

[0048] Step S101: Figure 4A As shown, the metal gate 202 process flow is completed to form the metal gate 202, and the metal gate 202 is formed in the gate trench between the zero-th interlayer film. Figure 4A In the embodiment, the zeroth interlayer film includes a partial thickness of the oxide layer 204 , and a silicon nitride layer 203 is formed at the bottom of the oxide layer 204 .

[0049] The embodiment of the present invention does not involve any improvement in the formation process of the metal gate 202 itself. Figure 4A The structure inside the metal gate 202 is not described in detail. A gate dielectric layer (not shown) is provided between the metal gate 202 and the surface of the semiconductor substrate 201; the metal gate 202 includes a bottom barrier layer (not shown), a metal work function layer (not shown), a top barrier layer (not shown) and a gate conductive material layer (not shown); the bottom barrier layer includes a first TiN layer, which is formed by an ALD process, and the reactants for forming the first TiN layer include TiCl4 and NH3, and the first TiN layer contains Cl.

[0050] In the embodiment of the present invention, the bottom barrier layer further includes a first TaN layer, and the bottom barrier layer is formed by stacking the first TiN layer and the first TaN layer.

[0051] The top barrier layer consists of a third TiN layer or a stacked layer of a third TiN layer and a second Ti layer; the third TiN layer is also formed by the ALD process and contains Cl.

[0052] Metal gate transistors include NMOS and PMOS.

[0053] In the PMOS formation region, the metal work function layer of the metal gate 202 uses a P-type metal work function layer. The material of the P-type metal work function layer includes TiN. The TiN of the P-type metal work function layer is also formed by the ALD process and contains Cl.

[0054] In the NMOS formation region, the metal work function layer of the metal gate 202 uses an N-type metal work function layer.

[0055] The material of the N-type metal work function layer includes TiAl.

[0056] Step S102 , forming an interlayer film, the interlayer film covers the metal gate 202 and the top surface of the zeroth interlayer film. Figure 4A In FIG. 2 , the interlayer film includes a top portion of an oxide layer 204 , a silicon nitride layer 205 , and an oxide layer 206 .

[0057] Step S103, forming the contact hole 209, includes the following steps:

[0058] Step S1031: Figure 4A As shown, pattern etching is performed to form a contact hole opening 207, and the contact hole opening 207 passes through the corresponding interlayer film or the bottom zeroth interlayer film. For the corresponding semiconductor device, an active region and a drain region are formed in the semiconductor substrate 201 on both sides of the metal gate 202, and corresponding contact hole openings 207 are formed on the top of the metal gate 202, the source region, and the drain region. Figure 4A Only the contact hole opening 207 at the top of the metal gate 202 is shown. In the embodiment of the present invention, the contact hole opening 207 at the top of the source region and the drain region will expose the surface of the bottom semiconductor substrate 201. The semiconductor substrate 201 includes a silicon substrate, and an embedded epitaxial layer can be further formed in the source region and the drain region, such as an embedded SiP epitaxial layer for NMOS and an embedded SiGe epitaxial layer for PMOS.

[0059] Step S1032: Figure 4A As shown, a heat treatment is performed to reduce the Cl content in the metal gate 202 .

[0060] In the embodiment of the present invention, the heat treatment includes: conventional thermal annealing and dynamic surface annealing, spike annealing or rapid thermal treatment.

[0061] Step S1033: Figure 4B As shown, an adhesion barrier layer 208 is deposited, and the adhesion barrier layer 208 includes a first Ti layer and a second TiN layer stacked in sequence.

[0062] Step S1034, perform a metal silicidation reaction to form TiSi in the first Ti layer in contact with silicon, and reduce the Cl content in the metal gate 202 to ensure that during the metal silicidation reaction, the first Ti layer on the top of the metal gate 202 will not form a void under the action of Cl. In the embodiment of the present invention, the first Ti layer in the contact hole opening 207 at the top of the source region and the drain region will react with the metal silicon in the bottom semiconductor substrate 201 to form TiSi.

[0063] Step S1035 , filling the contact hole opening 207 with metal to form a contact hole 209 .

[0064] In the embodiment of the present invention, the metal filled in the contact hole opening 207 includes Co.

[0065] The sub-step of filling metal in the contact hole opening 207 to form the contact hole 209 includes:

[0066] A Co seed layer is formed.

[0067] An electroplating process is performed to form a Co body layer, which completely fills the inside of the contact hole opening 207 and extends to the outer surface of the contact hole opening 207 .

[0068] A chemical mechanical polishing process is performed to remove the Co bulk layer on the outer surface of the contact hole opening 207 and to leave the Co bulk layer only in the contact hole opening 207 .

[0069] In the embodiment of the present invention, after the contact hole opening 207 is formed and before the adhesion barrier layer 208 is deposited, a heat treatment step is added to reduce the Cl content in the metal gate 202. The heat treatment at this time can timely remove the Cl in the metal gate 202 before the first Ti layer of the adhesion barrier layer 208 is deposited, thereby preventing the Cl in the metal gate 202 from diffusing to the bottom area of ​​the contact hole 209 at the top of the metal gate 202 and reacting with Ti to form Ti Cl compounds such as TiCl4 in the subsequent metal silicidation reaction. After TiCl4 volatilizes at high temperature, the area where Ti is lost will become a cavity. Therefore, the embodiment of the present invention can prevent the formation of voids, which can increase the stability of the metal gate 202 and prevent the on-resistance at the bottom of the contact hole 209 from increasing.

[0070] For NMOS, the embodiment of the present invention can facilitate the normal diffusion of Al in the metal gate 202 of NMOS by reducing the Cl content in the metal gate 202, and can prevent the excessive Cl content from affecting the threshold voltage of NMOS and the corresponding device performance.

[0071] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a metal gate transistor, characterized in that: The steps include: completing a metal gate process flow to form a metal gate, wherein the metal gate contains Cl; forming an interlayer film, wherein the interlayer film covers the top surface of the metal gate and the zeroth interlayer film; The contact hole is formed, comprising the following steps: Performing patterned etching to form a contact hole opening, wherein the contact hole opening passes through the corresponding interlayer film or the zeroth interlayer film at the bottom; Performing heat treatment to reduce the Cl content in the metal gate; depositing an adhesion barrier layer, the adhesion barrier layer comprising a first Ti layer and a second TiN layer stacked in sequence; Performing a metal silicidation reaction to form TiSi in the first Ti layer in contact with silicon, and reducing the Cl content in the metal gate to ensure that the first Ti layer on the top of the metal gate does not form a cavity under the action of Cl in the metal silicidation reaction; The contact hole is formed by filling metal in the contact hole opening.

2. The method for manufacturing a metal gate transistor according to claim 1, wherein: The metal gate is formed in a gate trench between the zeroth interlayer film, and a gate dielectric layer is separated between the metal gate and the surface of the semiconductor substrate; the metal gate includes a bottom barrier layer, a metal work function layer, a top barrier layer and a gate conductive material layer; The bottom barrier layer includes a first TiN layer, which is formed by an ALD process. Reactants for forming the first TiN layer include TiCl 4 and NH 3 , and the first TiN layer contains Cl.

3. The method for manufacturing a metal gate transistor according to claim 2, wherein: The bottom barrier layer further includes a first TaN layer and is formed by stacking the first TiN layer and the first TaN layer.

4. The method for manufacturing a metal gate transistor according to claim 2, wherein: The top barrier layer is composed of a third TiN layer or a stacked layer of a third TiN layer and a second Ti layer; the third TiN layer is also formed by an ALD process and contains Cl.

5. The method for manufacturing a metal gate transistor according to claim 2, wherein: Metal gate transistors include NMOS and PMOS; In the PMOS formation region, the metal work function layer of the metal gate adopts a P-type metal work function layer, the material of the P-type metal work function layer includes TiN, and the TiN of the P-type metal work function layer is also formed by ALD process and contains Cl.

6. The method for manufacturing a metal gate transistor according to claim 5, wherein: In the NMOS formation region, the metal work function layer of the metal gate adopts an N-type metal work function layer.

7. The method for manufacturing a metal gate transistor according to claim 6, wherein: The material of the N-type metal work function layer includes TiAl.

8. The method for manufacturing a metal gate transistor according to claim 1, wherein: The metal filled in the contact hole opening includes Co.

9. The method for manufacturing a metal gate transistor according to claim 8, wherein: The step of filling metal in the contact hole opening to form the contact hole comprises: forming a Co seed layer; Performing an electroplating process to form a Co main layer, wherein the Co main layer completely fills the interior of the contact hole opening and extends to the outer surface of the contact hole opening; A chemical mechanical polishing process is performed to remove the Co bulk layer on the outer surface of the contact hole opening and to make the Co bulk layer only located in the contact hole opening.

10. The method for manufacturing a metal gate transistor according to claim 1, wherein: The heat treatment includes: dynamic surface annealing, spike annealing, and rapid thermal treatment.

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