Array substrates and their fabrication methods, display panels and electronic devices

Abstract

This application provides an array substrate and its fabrication method, a display panel, and an electronic device, relating to the field of display technology, and improves the display effect of the display panel at low grayscale levels. The array substrate includes a substrate and multiple conductive layers disposed on one side of the substrate and insulated from each other. The multiple conductive layers include: a first conductive layer, stacked on one side of the substrate, including a first conductive segment; a first metal layer, including a scan signal line and a gate; a second metal layer; a third metal layer; a second conductive layer, including a second conductive segment; the array substrate further includes an insulating layer, stacked between the first metal layer and the second conductive layer, including a first via and a second via; the second conductive segment fills the first and second vias, one end of the second conductive segment is connected to the first conductive segment through the first via, and the other end is connected to the gate through the second via, thereby reducing the parasitic capacitance generated between the second conductive segment and the scan signal line, thus improving the display effect of the display panel at low grayscale levels.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and its fabrication method, a display panel, and an electronic device. Background Technology

[0002] In recent years, organic light-emitting diode (OLED) display panels have gradually become the mainstream product in the display field. Transistors are an indispensable component in display panels. Research has found that in under-display camera products, there is an overlap between the metal layer bridging the gate and conductive section of the driving transistor and another metal layer. These two metal layers generate a large parasitic capacitance, leading to abnormal display in the sub-display area at low grayscale levels.

[0003] Therefore, improving the display effect of the secondary display area at low grayscale levels has become an urgent problem to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide an array substrate and its fabrication method, a display panel, and an electronic device.

[0005] In a first aspect, one embodiment of this application provides an array substrate, which includes a substrate and a plurality of conductive layers disposed on one side of the substrate and insulated from each other. The plurality of conductive layers include: a first conductive layer, stacked on one side of the substrate, the first conductive layer including a first conductive segment; a first metal layer, stacked on the side of the first conductive layer facing away from the substrate, the first metal layer including a scan signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate being located on opposite sides of the orthographic projection of the scan signal line on the substrate; a second metal layer, stacked on the side of the first metal layer facing away from the substrate; a third metal layer, stacked on the side of the second metal layer facing away from the substrate; and a second conductive layer. The array substrate further includes an insulating layer stacked between the first metal layer and the second conductive layer. The insulating layer includes a first via and a second via. The orthographic projection of the first via on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The orthographic projection of the second via on the substrate and the orthographic projection of the gate on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The second conductive segment fills the first via and the second via. One end of the second conductive segment is connected to the first conductive segment through the first via, and the other end is connected to the gate through the second via.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the insulating layer further includes a third via and a fourth via, wherein the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth via on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate; the third metal layer includes a third conductive segment and a fourth conductive segment, which are spaced apart, wherein the orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scan signal line on the substrate, and the orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scan signal line on the substrate; the third conductive segment fills the third via, and the third conductive segment is connected to one end of the second conductive segment through the first via; the fourth conductive segment fills the fourth via, and the fourth conductive segment is connected to the other end of the second conductive segment through the second via.

[0007] Preferably, the insulating layer includes a capacitor insulating layer, an interlayer insulating layer and a first planarization layer stacked sequentially along the direction away from the substrate, a first via and a second via respectively penetrating the first planarization layer, a third via penetrating the capacitor insulating layer and the interlayer insulating layer, and a fourth via penetrating the capacitor insulating layer and the interlayer insulating layer.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the third metal layer includes a first power line, the orthographic projection of the first power line on the substrate and the orthographic projection of the scan signal line on the substrate form a first overlapping region, and the orthographic projection of the second conductive segment on the substrate overlaps with the first overlapping region.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the array substrate further includes: a second planarization layer stacked on the side of the second conductive layer away from the substrate, the second planarization layer including a fifth via and a sixth via, the orthogonal projection of the fifth via on the substrate and the orthogonal projection of the first conductive segment on the substrate being located on the same side of the orthogonal projection of the scan signal line on the substrate, the orthogonal projection of the sixth via on the substrate and the orthogonal projection of the gate on the substrate being located on the same side of the orthogonal projection of the scan signal line on the substrate; the plurality of conductive layers further include a third conductive layer stacked on the side of the second planarization layer away from the substrate, the third conductive layer including a fifth conductive segment, the fifth conductive segment filling the fifth via and the sixth via, one end of the fifth conductive segment being connected to one end of the second conductive segment through the fifth via, and the other end of the fifth conductive segment being connected to the other end of the second conductive segment through the sixth via.

[0010] Secondly, one embodiment of this application provides an array substrate, which includes a substrate and a plurality of conductive layers disposed on one side of the substrate and insulated from each other. The plurality of conductive layers include: a first conductive layer, stacked on one side of the substrate, the first conductive layer including a first conductive segment; a first metal layer, stacked on the side of the first conductive layer away from the substrate, the first metal layer including a scan signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate being located on opposite sides of the orthographic projection of the scan signal line on the substrate; a second metal layer, stacked on the side of the first metal layer away from the substrate, the second metal layer including a second power line; and a third metal layer, stacked on the side of the second metal layer away from the substrate, the third metal layer including a sixth conductive segment, one end of the sixth conductive segment being connected to the first conductive segment and the other end being connected to the gate, the orthographic projection of the sixth conductive segment on the substrate and the orthographic projection of the scan signal line on the substrate forming a second overlapping region, and the orthographic projection of the second power line on the substrate overlapping with the second overlapping region.

[0011] Thirdly, one embodiment of this application provides a method for fabricating an array substrate, the method comprising: providing a substrate; fabricating a first conductive layer on one side of the substrate, the first conductive layer including a first conductive segment; fabricating a first metal layer on the side of the first conductive layer opposite to the substrate, the first metal layer and the first conductive layer being insulated from each other, the first metal layer including a scan signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate being located on opposite sides of the orthographic projection of the scan signal line on the substrate; fabricating a second metal layer on the side of the first metal layer opposite to the substrate; fabricating a third metal layer on the side of the second metal layer opposite to the substrate; and fabricating a third metal layer on the third metal layer. A second conductive layer is fabricated on the side facing away from the substrate. The second conductive layer includes a second conductive segment. The array substrate includes an insulating layer stacked between the first metal layer and the second conductive layer. The insulating layer includes a first via and a second via. The orthographic projection of the first via on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The orthographic projection of the second via on the substrate and the orthographic projection of the gate on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The second conductive segment fills the first via and the second via. One end of the second conductive segment is connected to the first conductive segment through the first via, and the other end is connected to the gate through the second via.

[0012] In conjunction with the third aspect, in certain implementations of the third aspect, after the first metal layer is fabricated on the side of the first conductive layer away from the substrate and before the second metal layer is fabricated on the side of the first metal layer away from the substrate, the fabrication method further includes: fabricating a stacked capacitor insulating layer on the side of the first metal layer away from the substrate; after the second metal layer is fabricated on the side of the first metal layer away from the substrate and before the third metal layer is fabricated on the side of the second metal layer away from the substrate, the method further includes: fabricating an interlayer insulating layer on the side of the second metal layer away from the substrate, the insulating layer further including a third via and a fourth via, the third via penetrating the capacitor insulating layer and the interlayer insulating layer, the fourth via penetrating the capacitor insulating layer and the interlayer insulating layer; the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth via on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate. The process includes partial overlap; before fabricating the second conductive layer on the side of the third metal layer away from the substrate, the process further includes: fabricating a first planarization layer on the side of the third metal layer away from the substrate, with a first via and a second via penetrating the first planarization layer; wherein the third metal layer includes a third conductive segment and a fourth conductive segment, the third conductive segment and the fourth conductive segment being spaced apart, the orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate being located on the same side of the orthographic projection of the scan signal line on the substrate, the orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate being located on the same side of the orthographic projection of the scan signal line on the substrate; the third conductive segment filling the third via, the third conductive segment connecting one end of the second conductive segment through the first via, the fourth conductive segment filling the fourth via, and the fourth conductive segment connecting the other end of the second conductive segment through the second via.

[0013] Fourthly, one embodiment of this application provides a method for fabricating an array substrate. The method includes: providing a substrate; fabricating a first conductive layer on one side of the substrate, the first conductive layer including a first conductive segment; fabricating a first metal layer on the side of the first conductive layer away from the substrate, the first metal layer and the first conductive layer being insulated from each other, the first metal layer including a scan signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate being located on opposite sides of the orthographic projection of the scan signal line on the substrate; fabricating a second metal layer on the side of the first metal layer away from the substrate, the second metal layer and the first metal layer being insulated from each other, the second metal layer including a second power line; fabricating a third metal layer on the side of the second metal layer away from the substrate, the second metal layer and the third metal layer being insulated from each other, the third metal layer including a sixth conductive segment, one end of the sixth conductive segment being connected to the first conductive segment and the other end being connected to the gate, the orthographic projection of the sixth conductive segment on the substrate and the orthographic projection of the scan signal line on the substrate forming a second overlapping region, the orthographic projection of the second power line on the substrate overlapping with the second overlapping region.

[0014] Fifthly, one embodiment of this application provides a display panel that includes an array substrate as mentioned in any of the above embodiments.

[0015] In a sixth aspect, one embodiment of this application provides an electronic device that includes a display panel as mentioned in the above embodiments.

[0016] The array substrate provided in this application embodiment includes a substrate and a plurality of conductive layers disposed on one side of the substrate and insulated from each other. The plurality of conductive layers include: a first conductive layer, stacked on one side of the substrate, the first conductive layer including a first conductive segment; a first metal layer, stacked on the side of the first conductive layer away from the substrate, the first metal layer including a scan signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate being located on opposite sides of the orthographic projection of the scan signal line on the substrate; a second metal layer, stacked on the side of the first metal layer away from the substrate; a third metal layer, stacked on the side of the second metal layer away from the substrate; and a second conductive layer, stacked on the side of the third metal layer away from the substrate, the second conductive layer including a second conductive segment. The array substrate further includes an insulating layer, stacked between the first metal layer and the second conductive layer, the insulating layer including a first via and a second via, the first via being on the side of the substrate... The projection of the first conductive segment onto the substrate and the orthogonal projection of the scan signal line onto the substrate are located on the same side as the orthogonal projection of the second via onto the substrate and the orthogonal projection of the gate onto the substrate are located on the same side as the orthogonal projection of the scan signal line onto the substrate. The second conductive segment fills the first and second vias. One end of the second conductive segment is connected to the first conductive segment through the first via, and the other end is connected to the gate through the second via. By using the second conductive segment in the second conductive layer on the side of the third metal layer away from the substrate as a bridging trace to connect the first conductive segment and the gate, the distance between the bridging trace and the scan signal line is increased, and the relative permittivity of the bridging trace and the scan signal line is reduced. This reduces the parasitic capacitance generated by the bridging trace and the scan signal line. In other words, the parasitic capacitance generated by the second conductive segment and the scan signal line is smaller, thereby improving the display effect of the display panel at low gray levels. Attached Figure Description

[0017] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 The diagram shown is a schematic diagram of the array substrate provided by the related technology.

[0019] Figure 2 As shown Figure 1 The diagram shows a cross-sectional structure of the array substrate.

[0020] Figure 3 The diagram shown is a structural schematic of an array substrate provided in an embodiment of this application.

[0021] Figure 4 As shown Figure 3 The diagram shows a cross-sectional structure of the array substrate.

[0022] Figure 5 The diagram shown is a structural schematic of an array substrate provided in another embodiment of this application.

[0023] Figure 6 As shown Figure 5 The diagram shows a cross-sectional structure of the array substrate.

[0024] Figure 7 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application.

[0025] Figure 8 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application.

[0026] Figure 9 The diagram shown is a structural schematic of the fabrication process of an array substrate provided in an embodiment of this application.

[0027] Figure 10 The diagram shown is a structural schematic of the fabrication process of an array substrate provided in another embodiment of this application.

[0028] Figure 11 The diagram shown is a structural schematic of the fabrication process of an array substrate provided in another embodiment of this application.

[0029] Figure 12 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application.

[0030] Figure 13 The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application.

[0031] Reference numerals: Array substrate 100; Substrate A; First conductive layer B1; First metal layer M1; Capacitor insulating layer CI; Interlayer insulating layer ILD; Second metal layer M2; Third metal layer M3; First planarization layer PLA1; Second conductive layer B2; Second planarization layer PLA2; Third conductive layer B3; First conductive segment Q1; Second conductive segment Q2; Third conductive segment Q3; Fourth conductive segment Q4; Fifth conductive segment Q5; Sixth conductive segment Q6; Seventh conductive segment Q7; Gate G; Scan signal line S; First power line E1; Second power line E2; First through hole K1; Second through hole K2; Third through hole K3; Fourth through hole K4; Fifth through hole K5; Sixth through hole K6; Main display area U1; Sub-display area U2; Electronic device 10. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented even without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0034] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0035] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0036] Figure 1 The diagram shown is a schematic diagram of the array substrate provided by the related technology. Figure 2 As shown Figure 1 A schematic diagram of the cross-sectional structure of the array substrate is shown. Figure 1 and 2As shown, the array substrate 100 provided by the related technology includes a substrate A and a plurality of conductive layers disposed on one side of the substrate A and insulated from each other. The plurality of conductive layers include: a first conductive layer B1, stacked on one side of the substrate A, the first conductive layer B1 including a first conductive segment Q1; a first metal layer M1, stacked on the side of the first conductive layer B1 away from the substrate A, the first metal layer M1 including a scan signal line S and a gate G, the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A being located on opposite sides of the orthographic projection of the scan signal line S on the substrate A; a second metal layer M2, stacked on the side of the first metal layer M1 away from the substrate A; a third metal layer M3, stacked on the side of the second metal layer M2 away from the substrate A; the third metal layer M3 includes a seventh conductive segment Q7, one end of the seventh conductive segment Q7 being connected to the first conductive segment Q1, and the other end being connected to the gate G.

[0037] Understandably, this is for the purpose of providing a comprehensive illustration. Figure 1 The cross-sectional structure of the array substrate 100 shown is as follows. Figure 2 Not Figure 1 The schematic diagram shows a cross-sectional structure at a certain location of the array substrate 100, but... Figure 1 The diagram shows a structural schematic formed by splicing cross-sections at multiple locations of the array substrate 100. Similarly, the cross-sectional structural schematics mentioned below are all structural schematics formed by splicing cross-sections at multiple locations of the corresponding array substrate 100.

[0038] As described in the background art, the array substrate 100 provided by the related art shows that the orthographic projection of the seventh conductive segment Q7 on the substrate A and the orthographic projection of the scan signal line S on the substrate A overlap, and the parasitic capacitance generated by the seventh conductive segment Q7 and the scan signal line S is large, resulting in poor display effect of the display panel at low gray levels, especially affecting the display effect of the sub-display area U2 of the display panel.

[0039] To address the aforementioned technical issues, this application proposes a method that connects the first conductive segment Q1 and the gate G by providing a bridging trace on the side of the third metal layer M3 away from the substrate. Compared to providing a bridging trace in the third metal layer M3, this increases the distance between the bridging trace and the scan signal line, thereby reducing parasitic capacitance and improving the display effect of the display panel at low grayscale levels.

[0040] Figure 3 The diagram shown is a structural schematic of an array substrate provided in an embodiment of this application. Figure 4 As shown Figure 3 A schematic diagram of the cross-sectional structure of the array substrate is shown. Figure 3 and 4As shown, the array substrate 100 provided in this embodiment includes a substrate A and a plurality of conductive layers disposed on one side of the substrate A and insulated from each other. The plurality of conductive layers include: a first conductive layer B1, stacked on one side of the substrate A, the first conductive layer B1 including a first conductive segment Q1; a first metal layer M1, stacked on the side of the first conductive layer B1 away from the substrate A, the first metal layer M1 including a scan signal line S and a gate G, the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A being located on opposite sides of the orthographic projection of the scan signal line S on the substrate A; a second metal layer M2, stacked on the side of the first metal layer M1 away from the substrate A; a third metal layer M3, stacked on the side of the second metal layer M2 away from the substrate A; and a second conductive layer B2, stacked on the third metal layer... On the side of M3 facing away from substrate A, the second conductive layer B2 includes a second conductive segment Q2; the array substrate 100 also includes an insulating layer stacked between the first metal layer M1 and the second conductive layer B2. The insulating layer includes a first via K1 and a second via K2. The orthographic projection of the first via K1 on substrate A and the orthographic projection of the first conductive segment Q1 on substrate A are located on the same side as the orthographic projection of the scan signal line S on substrate A. The orthographic projection of the second via K2 on substrate A and the orthographic projection of the gate G on substrate A are located on the same side as the orthographic projection of the scan signal line S on substrate A. The second conductive segment Q2 fills the first via K1 and the second via K2. One end of the second conductive segment Q2 is connected to the first conductive segment Q1 through the first via K1, and the other end is connected to the gate G through the second via K2.

[0041] It should be noted that in the entire display panel, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are stacked; or, in other words, during the fabrication of the display panel, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are fabricated sequentially. However, since the first metal layer M1, the second metal layer M2, and the third metal layer M3 are all patterned film layers, any one of the first metal layer M1, the second metal layer M2, and the third metal layer M3 may or may not be present on cross-sections at different locations on the array substrate 100.

[0042] For example, in Figure 4 In the cross-section shown, a third metal layer M3 exists between the second conductive segment Q2 and the scan signal line S, but a second metal layer M2 is not present. Alternatively, in another embodiment, a third metal layer M3 may exist between the second conductive segment Q2 and the scan signal line S, but a second metal layer M2 may also be present. Yet another embodiment may provide a cross-section where the third metal layer M3 may not be present between the second conductive segment Q2 and the scan signal line S, but a second metal layer M2 may be present.

[0043] In some embodiments, the first conductive layer B1 may be made of a semiconductor, such as polysilicon. The second conductive layer B2 may be made of indium tin oxide.

[0044] As can be seen from the array substrate 100 provided in the embodiments of this application, the trace bridging the first conductive segment Q1 and the gate G is the second conductive segment Q2, rather than the seventh conductive segment Q7 mentioned in the related art.

[0045] In the array substrate 100 provided in this application embodiment, a trace bridging the first conductive section Q1 and the gate G is used in the second conductive layer B2. Since the second conductive layer B2 is located on the side of the third metal layer M3 away from the substrate, compared with the trace bridging the first conductive section Q1 and the gate G using the seventh conductive section Q7 in the third metal layer M3, the distance between the bridging trace and the scan signal line S is increased (i.e., the distance between the second conductive section Q2 and the scan signal line S is larger), thereby reducing the parasitic capacitance generated by the bridging trace and the scan signal line S. That is, the parasitic capacitance generated by the second conductive section Q2 and the scan signal line S is smaller, thereby improving the display effect of the display panel at low gray levels.

[0046] refer to Figure 3 and 4 The insulating layer also includes a third via K3 and a fourth via K4. The orthographic projection of the third via K3 on the substrate A at least partially overlaps with the orthographic projection of the first conductive segment Q1 on the substrate A, and the orthographic projection of the fourth via K4 on the substrate A at least partially overlaps with the orthographic projection of the gate G on the substrate A. The third metal layer M3 includes a third conductive segment Q3 and a fourth conductive segment Q4, which are spaced apart. The orthographic projection of the third conductive segment Q3 on the substrate A overlaps with the orthographic projection of the first conductive segment Q1 on the substrate A. The orthographic projection on substrate A is located on the same side as the orthographic projection of the scan signal line S on substrate A. The orthographic projection of the fourth conductive segment Q4 on substrate A and the orthographic projection of the gate G on substrate A are located on the same side as the orthographic projection of the scan signal line S on substrate A. The third conductive segment Q3 fills the third through-hole K3 and is connected to one end of the second conductive segment Q2 through the first through-hole K1. The fourth conductive segment Q4 fills the fourth through-hole K4 and is connected to the other end of the second conductive segment Q2 through the second through-hole K2.

[0047] This application provides an embodiment in which one end of a second conductive segment Q2 is connected to a first conductive segment Q1, and the other end is connected to a gate G. Specifically, one end of the second conductive segment Q2 is directly connected to a third conductive segment Q3 through a first through-hole K1, and then the third conductive segment Q3 is directly connected to the first conductive segment Q1 through a third through-hole K3, thereby achieving the purpose of connecting one end of the second conductive segment Q2 to the first conductive segment Q1. The other end of the second conductive segment Q2 is directly connected to a fourth conductive segment Q4 through a second through-hole K2, and then the fourth conductive segment Q4 is directly connected to the gate G through a fourth through-hole K4, thereby achieving the purpose of connecting the other end of the second conductive segment Q2 to the gate G.

[0048] In one embodiment, the insulating layer comprises a capacitive insulating layer CI, an interlayer insulating layer ILD, and a first planarization layer PLA1 stacked sequentially along a direction away from substrate A. A first via K1 and a second via K2 penetrate the first planarization layer PLA1, respectively. A third via K3 penetrates the capacitive insulating layer CI and the interlayer insulating layer ILD, and a fourth via K4 penetrates the capacitive insulating layer CI and the interlayer insulating layer ILD. In this case, the first planarization layer PLA1 connects the bridging trace (i.e., the seventh conductive segment Q7) and the scan signal line S, reducing the relative permittivity between the bridging trace and the scan signal line S, thereby further reducing parasitic capacitance.

[0049] refer to Figure 3 and 4 In the array substrate 100 provided in this application embodiment, the third metal layer M3 includes a first power line E1. The orthographic projection of the first power line E1 on the substrate A and the orthographic projection of the scan signal line S on the substrate A form a first overlapping region. The orthographic projection of the first power line E1 on the substrate A is located on the same side as the orthographic projections of the first via K1 and the second via K2 on the substrate A. The orthographic projection of the second conductive segment Q2 on the substrate A overlaps with the first overlapping region.

[0050] In this embodiment, the first power line E1 shields the electrical interaction between the second conductive section Q2 and the scanning signal line S, making the parasitic capacitance generated by the two close to zero. This avoids the problem of abnormal display at low gray levels and greatly improves the display effect of the display panel at low gray levels.

[0051] refer to Figure 3 and 4The array substrate 100 provided in this embodiment further includes: a second planarization layer PLA2, stacked on the side of the second conductive layer B2 away from the substrate A. The second planarization layer PLA2 includes a fifth via K5 and a sixth via K6. The orthogonal projection of the fifth via K5 on the substrate A and the orthogonal projection of the first conductive segment Q1 on the substrate A are located on the same side as the orthogonal projection of the scan signal line S on the substrate A. The orthogonal projection of the sixth via K6 on the substrate A and the orthogonal projection of the gate G on the substrate A are located on the same side as the orthogonal projection of the scan signal line S on the substrate A. The plurality of conductive layers further include a third conductive layer B3, stacked on the side of the second planarization layer PLA2 away from the substrate A. The third conductive layer B3 includes a fifth conductive segment Q5. The fifth conductive segment Q5 fills the fifth via K5 and the sixth via K6. One end of the fifth conductive segment Q5 is connected to one end of the second conductive segment Q2 through the fifth via K5, and the other end of the fifth conductive segment Q5 is connected to the other end of the second conductive segment Q2 through the sixth via K6.

[0052] This embodiment of the application reduces the resistance of the second conductive section Q2 by setting a fifth conductive section Q5 and connecting the fifth conductive section Q5 and the second conductive section Q2 in parallel, thereby reducing power consumption and achieving the goal of energy saving and environmental protection.

[0053] It is understandable that the orthogonal projection of the fifth conductive segment Q5 on the substrate A also overlaps with the first overlapping area. The first power line E1 also shields the electrical interaction between the fifth conductive segment Q5 and the scan signal line S, making the parasitic capacitance generated by the two close to zero.

[0054] Figure 5 The diagram shown is a structural schematic of an array substrate provided in another embodiment of this application. Figure 6 As shown Figure 5 A schematic diagram of the cross-sectional structure of the array substrate is shown. Figure 5 and 6As shown, in another embodiment of the array substrate 100, the array substrate 100 includes a substrate A and a plurality of conductive layers disposed on one side of the substrate A and insulated from each other. The plurality of conductive layers include: a first conductive layer B1, stacked on one side of the substrate A, the first conductive layer B1 including a first conductive segment Q1; and a first metal layer M1, stacked on the side of the first conductive layer B1 facing away from the substrate A, the first metal layer M1 including a scan signal line S and a gate G. The orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are respectively located at the orthographic projection of the scan signal line S on the substrate A. The first metal layer M1 is stacked on the side opposite to the substrate A; the second metal layer M2 is stacked on the side opposite to the substrate A of the first metal layer M1, and the second metal layer M2 includes a second power line E2; the third metal layer M3 is stacked on the side opposite to the substrate A of the second metal layer M2, and the third metal layer M3 includes a sixth conductive segment Q6, one end of the sixth conductive segment Q6 is connected to the first conductive segment Q1, and the other end is connected to the gate G. The orthogonal projection of the sixth conductive segment Q6 on the substrate A and the orthogonal projection of the scan signal line S on the substrate A form a second overlapping region. The orthogonal projection of the second power line E2 on the substrate A overlaps with the second overlapping region.

[0055] In the array substrate 100 provided in this application embodiment, the trace bridging the first conductive segment Q1 and the gate G is the sixth conductive segment Q6. By setting the second power line E2, the electrical interaction between the sixth conductive segment Q6 and the scan signal line S is shielded, so that the parasitic capacitance generated by the two is close to zero, thereby avoiding the problem of abnormal display at low gray levels and greatly improving the display effect of the display panel at low gray levels.

[0056] The structure and working principle of the array substrate 100 have been described in detail above. Based on the same inventive concept, this application also provides a method for preparing the array substrate 100. The specific details of the preparation method are described below.

[0057] Figure 7 The diagram shown is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of this application. Figure 7 As shown in the embodiments of this application, a method for fabricating an array substrate 100 is also provided, the method comprising the following steps:

[0058] Step S901: Provide substrate A.

[0059] Step S902: Prepare a first conductive layer B1 on one side of substrate A.

[0060] The first conductive layer B1 includes a first conductive segment Q1.

[0061] Step S903: Prepare a first metal layer M1 on the side of the first conductive layer B1 that is away from the substrate A.

[0062] The first metal layer M1 and the first conductive layer B1 are insulated from each other. The first metal layer M1 includes a scan signal line S and a gate G. The orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are located on both sides of the orthographic projection of the scan signal line S on the substrate A, respectively.

[0063] Step S904: Prepare a second metal layer M2 on the side of the first metal layer M1 that is away from the substrate A.

[0064] Step S905: Prepare a third metal layer M3 on the side of the second metal layer M2 away from the substrate A.

[0065] Step S906: Prepare a second conductive layer B2 on the side of the third metal layer M3 facing away from the substrate A.

[0066] The array substrate includes an insulating layer comprising a first via K1 and a second via K2. The orthographic projection of the first via K1 onto substrate A and the orthographic projection of the first conductive segment Q1 onto substrate A are located on the same side as the orthographic projection of the scan signal line S onto substrate A. Similarly, the orthographic projection of the second via K2 onto substrate A and the orthographic projection of the gate G onto substrate A are located on the same side as the orthographic projection of the scan signal line S onto substrate A. The second conductive layer B2 includes a second conductive segment Q2, which fills both the first and second vias K1 and K2. One end of the second conductive segment Q2 is connected to the first conductive segment Q1 through the first via K1, and the other end is connected to the gate G through the second via K2.

[0067] The preparation method provided in this application reduces the parasitic capacitance generated by the second conductive segment Q2 and the scanning signal line S, thereby improving the display effect of the display panel at low gray levels.

[0068] Figure 8 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application. Figure 8 As shown, between step S903 and step S904, the preparation method further includes the following steps:

[0069] Step S1001: Prepare a capacitor insulating layer CI on the side of the first metal layer M1 away from the substrate A.

[0070] In this case, step S904 is executed as follows:

[0071] Step S1002: Prepare a second metal layer M2 on the side of the capacitor insulating layer CI that is away from the substrate A.

[0072] Between step S1002 and step S905, the preparation method further includes:

[0073] Step S1003: An interlayer insulating layer (ILD) is prepared on the side of the second metal layer M2 away from the substrate A.

[0074] In this case, step S905 is executed as follows:

[0075] Step S1004: Prepare a third metal layer M3 on the side of the interlayer insulating layer ILD away from the substrate A.

[0076] Between step S1004 and step S906, the preparation method further includes:

[0077] Step S1005: Prepare the first planarization layer PLA1 on the side of the third metal layer M3 away from the substrate A.

[0078] In this case, step S906 is executed as follows:

[0079] Step S1006: Prepare a second conductive layer B2 on the side of the first planarization layer PLA1 away from the substrate A.

[0080] The first through-hole K1 and the second through-hole K2 respectively penetrate the first planarization layer PLA1.

[0081] The insulating layer also includes a third via K3 and a fourth via K4. The third via penetrates the capacitor insulating layer and the interlayer insulating layer, and the fourth via penetrates the capacitor insulating layer and the interlayer insulating layer. The orthographic projection of the third via K3 on the substrate A at least partially overlaps with the orthographic projection of the first conductive segment Q1 on the substrate A, and the orthographic projection of the fourth via K4 on the substrate A at least partially overlaps with the orthographic projection of the gate G on the substrate A.

[0082] The third metal layer M3 includes a third conductive segment Q3 and a fourth conductive segment Q4, which are spaced apart. The orthographic projection of the third conductive segment Q3 on the substrate A is on the same side as the orthographic projection of the first conductive segment Q1 on the substrate A, and the orthographic projection of the fourth conductive segment Q4 on the substrate A is on the same side as the orthographic projection of the gate G on the substrate A, and the third conductive segment Q3 fills a third via K3 and is connected to one end of the second conductive segment Q2 through a first via K1. The fourth conductive segment Q4 fills a fourth via K4 and is connected to the other end of the second conductive segment Q2 through a second via K2.

[0083] The following is combined with Figures 9 to 11 Detailed description Figure 7 and 8 The preparation process corresponding to the preparation method shown. Figure 9 The diagram shown is a structural schematic of the fabrication process of an array substrate provided in an embodiment of this application. Figure 9In this process, substrate A, first conductive layer B1, first metal layer M1, capacitor insulating layer CI, interlayer insulating layer ILD, and second metal layer M2 were sequentially fabricated. The first conductive layer B1 can be made of polycrystalline silicon with a thickness of 450 angstroms; the first metal layer M1 can be made of molybdenum with a thickness of 2500 angstroms; the capacitor insulating layer CI can be made of silicon nitride with a thickness of 1000 angstroms; the interlayer insulating layer ILD can be made of a mixture of silicon oxide and silicon nitride, wherein the silicon oxide has a thickness of 2700 angstroms and the silicon nitride has a thickness of 2200 angstroms; the second metal layer M2 can be a titanium-aluminum-titanium stacked structure with thicknesses of 750 angstroms, 7000 angstroms, and 500 angstroms respectively.

[0084] Figure 10 The diagram shown is a structural schematic of the fabrication process of an array substrate according to another embodiment of this application. Figure 10 In this process, a first planarization layer PLA1 and a second conductive layer B2 were sequentially prepared. The thickness of the first planarization layer PLA1 is 1.2 micrometers, and the thickness of the second conductive layer B2 is 360 angstroms. The second conductive layer B2 was obtained by wet etching with an oxalic acid solution (3% to 4% by weight in the aqueous solution) followed by annealing at 250°C for 60 minutes.

[0085] Figure 11 The diagram shown is a structural schematic of the fabrication process of an array substrate according to another embodiment of this application. Figure 11 In this process, a second planarization layer PLA2 and a third conductive layer B3 were sequentially prepared. The thickness of the second planarization layer PLA2 is 1.65 micrometers, and the thickness of the third conductive layer B3 is 360 angstroms. The material of the third conductive layer B3 can be the same as that of the second conductive layer B2, and the preparation process for both can also be the same, which will not be described in detail here.

[0086] Understandable Figure 7 , Figure 8 The preparation method mentioned and Figures 9 to 11 For any details not shown in the structural diagram of the preparation process mentioned, please refer to [the provided text]. Figure 3 and Figure 4 The details described in the illustrated embodiments will not be repeated here.

[0087] Figure 12 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application. Figure 12 As shown in the embodiments of this application, a method for fabricating an array substrate 100 is also provided, the method comprising the following steps:

[0088] Step S1401: Provide substrate A.

[0089] Step S1402: Prepare a first conductive layer B1 on one side of substrate A.

[0090] The first conductive layer B1 includes a first conductive segment Q1.

[0091] Step S1403: Prepare a first metal layer M1 on the side of the first conductive layer B1 that is away from the substrate A.

[0092] The first metal layer M1 and the first conductive layer B1 are insulated from each other. The first metal layer M1 includes a scan signal line S and a gate G. The orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are located on both sides of the orthographic projection of the scan signal line S on the substrate A, respectively.

[0093] Step S1404: Prepare a second metal layer M2 on the side of the first metal layer M1 that is away from the substrate A.

[0094] The second metal layer M2 is insulated from the first metal layer M1, and the second metal layer M2 includes a second power line E2.

[0095] Step S1405: Prepare a third metal layer M3 on the side of the second metal layer M2 away from the substrate A.

[0096] The second metal layer M2 and the third metal layer M3 are insulated from each other. The third metal layer M3 includes a sixth conductive segment Q6. One end of the sixth conductive segment Q6 is connected to the first conductive segment Q1, and the other end is connected to the gate G. The orthographic projection of the sixth conductive segment Q6 on the substrate A and the orthographic projection of the scan signal line S on the substrate A form a second overlapping region. The orthographic projection of the second power line E2 on the substrate A overlaps with the second overlapping region.

[0097] The preparation method provided in this application makes the parasitic capacitance generated by the sixth conductive segment Q6 and the scanning signal line S close to zero, thereby avoiding the problem of abnormal display at low gray levels and greatly improving the display effect of the display panel at low gray levels.

[0098] Understandable Figure 12 For details not described in the mentioned preparation methods, please refer to [the relevant documentation / reference]. Figures 4 to 6 The details described in the illustrated embodiments will not be repeated here.

[0099] In another embodiment, this application also provides a display panel including an array substrate 100 as mentioned in any of the above embodiments.

[0100] Figure 13 The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application. Figure 13As shown, this application also provides an electronic device 10, which includes a display panel as mentioned in the above embodiments. Its technical principle and the effects produced are similar, and will not be described again here.

[0101] It is understood that the display panel can also be applied to other display devices, such as tablet computers, computer monitors, televisions, wearable devices, or information kiosks, or any other product or component with display functionality.

[0102] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0103] It should also be noted that in this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalent solutions to this application. Although several exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. An array substrate, characterized in that, Includes a substrate and a plurality of conductive layers disposed on one side of the substrate and insulated from each other, wherein the plurality of conductive layers include: A first conductive layer is stacked on one side of the substrate, and the first conductive layer includes a first conductive segment; A first metal layer is stacked on the side of the first conductive layer away from the substrate. The first metal layer includes a scan signal line and a gate. The orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on opposite sides of the orthographic projection of the scan signal line on the substrate, respectively. A second metal layer is stacked on the side of the first metal layer that faces away from the substrate; A third metal layer is stacked on the side of the second metal layer that faces away from the substrate; A second conductive layer is stacked on the side of the third metal layer away from the substrate, and the second conductive layer includes a second conductive segment; The array substrate further includes an insulating layer stacked between the first metal layer and the second conductive layer. The insulating layer includes a first through-hole and a second through-hole. The orthographic projection of the first through-hole on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scan signal line on the substrate. The orthographic projection of the second through-hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scan signal line on the substrate. The second conductive segment fills the first through hole and the second through hole, one end of the second conductive segment is connected to the first conductive segment through the first through hole, and the other end is connected to the gate through the second through hole; The second planarization layer is stacked on the side of the second conductive layer away from the substrate. The second planarization layer includes a fifth via and a sixth via. The orthographic projection of the fifth via on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The orthographic projection of the sixth via on the substrate and the orthographic projection of the gate on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The plurality of conductive layers further includes a third conductive layer, which is stacked on the side of the second planarization layer away from the substrate. The third conductive layer includes a fifth conductive segment, which fills the fifth via and the sixth via. One end of the fifth conductive segment is connected to one end of the second conductive segment through the fifth via, and the other end of the fifth conductive segment is connected to the other end of the second conductive segment through the sixth via. The second conductive segment and the fifth conductive segment are each integral structures.

2. The array substrate according to claim 1, characterized in that, The insulating layer further includes a third through-hole and a fourth through-hole, wherein the orthographic projection of the third through-hole on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth through-hole on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate; The third metal layer includes a third conductive segment and a fourth conductive segment, which are spaced apart. The orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scan signal line on the substrate. The orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scan signal line on the substrate. The third conductive segment fills the third via and is connected to one end of the second conductive segment through the first via. The fourth conductive segment fills the fourth via and is connected to the other end of the second conductive segment through the second via.

3. The array substrate according to claim 2, characterized in that, The insulating layer includes a capacitor insulating layer, an interlayer insulating layer and a first planarization layer stacked sequentially along the direction away from the substrate. The first via and the second via respectively penetrate the first planarization layer. The third via penetrates the capacitor insulating layer and the interlayer insulating layer. The fourth via penetrates the capacitor insulating layer and the interlayer insulating layer.

4. The array substrate according to claim 1, characterized in that, The third metal layer includes a first power line, the orthographic projection of the first power line on the substrate and the orthographic projection of the scan signal line on the substrate form a first overlapping region, and the orthographic projection of the second conductive segment on the substrate overlaps with the first overlapping region.

5. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A first conductive layer is formed on one side of the substrate, the first conductive layer including a first conductive segment; A first metal layer is formed on the side of the first conductive layer away from the substrate. The first metal layer and the first conductive layer are insulated from each other. The first metal layer includes a scan signal line and a gate. The orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scan signal line on the substrate. A second metal layer is prepared on the side of the first metal layer that is away from the substrate; A third metal layer is prepared on the side of the second metal layer that is away from the substrate; A second conductive layer is formed on the side of the third metal layer opposite to the substrate, the second conductive layer including a second conductive segment; The array substrate includes an insulating layer, which includes a first via and a second via. The orthographic projection of the first via on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The orthographic projection of the second via on the substrate and the orthographic projection of the gate on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The second conductive segment fills the first via and the second via. One end of the second conductive segment is connected to the first conductive segment through the first via, and the other end is connected to the gate through the second via. A second planarization layer is prepared on the side of the second conductive layer away from the substrate. The second planarization layer includes a fifth via and a sixth via. The orthographic projection of the fifth via on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. The orthographic projection of the sixth via on the substrate and the orthographic projection of the gate on the substrate are located on the same side as the orthographic projection of the scan signal line on the substrate. A third conductive layer is prepared on the side of the second planarization layer away from the substrate. The third conductive layer includes a fifth conductive segment, which fills the fifth via and the sixth via. One end of the fifth conductive segment is connected to one end of the second conductive segment through the fifth via, and the other end of the fifth conductive segment is connected to the other end of the second conductive segment through the sixth via. The second conductive segment and the fifth conductive segment are integral structures.

6. The preparation method according to claim 5, characterized in that, After fabricating a first metal layer on the side of the first conductive layer facing away from the substrate, and before fabricating a second metal layer on the side of the first metal layer facing away from the substrate, the method further includes: A capacitor insulating layer is prepared on the side of the first metal layer opposite to the substrate; After fabricating a second metal layer on the side of the first metal layer facing away from the substrate, and before fabricating a third metal layer on the side of the second metal layer facing away from the substrate, the method further includes: An interlayer insulating layer is formed on the side of the second metal layer opposite to the substrate. The insulating layer further includes a third via and a fourth via. The third via penetrates the capacitor insulating layer and the interlayer insulating layer, and the fourth via penetrates the capacitor insulating layer and the interlayer insulating layer. The orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth via on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate. After the third metal layer is formed on the side of the second metal layer facing away from the substrate, and before the second conductive layer is formed on the side of the third metal layer facing away from the substrate, the method further includes: A first planarization layer is prepared on the side of the third metal layer opposite to the substrate, and the first via and the second via respectively penetrate the first planarization layer; The third metal layer includes a third conductive segment and a fourth conductive segment, which are spaced apart. The orthographic projection of the third conductive segment on the substrate is located on the same side as the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth conductive segment on the substrate is located on the same side as the orthographic projection of the gate on the substrate, and the third conductive segment fills the third via. The third conductive segment is connected to one end of the second conductive segment through the first via, and the fourth conductive segment fills the fourth via. The fourth conductive segment is connected to the other end of the second conductive segment through the second via.

7. A display panel, characterized in that, Includes an array substrate as described in any one of claims 1 to 4 above.

8. An electronic device, characterized in that, Includes the display panel as described in claim 7 above.

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