Chip packaging structure and packaging method thereof

Abstract

The invention discloses a chip packaging structure and a packaging method thereof, and the packaging structure comprises a light-transmitting substrate which comprises an upper surface and a lower surface opposite to the upper surface; the fan-out substrate is arranged on the lower surface of the light-transmitting substrate, an opening penetrating through the upper surface and the lower surface of the fan-out substrate is formed in the fan-out substrate, a groove is formed in the upper surface of the fan-out substrate, the groove is communicated with the opening and the side wall of the fan-out substrate, and a sealing piece is arranged at the position, on the side wall of the fan-out substrate, in the groove; the upper surface of the chip faces the light-transmitting substrate and is arranged on the lower surface of the fan-out substrate, the chip is electrically connected with the fan-out substrate, a light sensing area is arranged on the upper surface of the chip, and the light sensing area is exposed in the opening. According to the invention, the groove for communicating the opening with the side wall of the fan-out substrate is prepared on the fan-out substrate, and the sealing element is prepared in the groove at the side wall of the fan-out substrate, so that the photosensitive area of the chip is sealed in a vacuum environment.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a chip packaging structure and a packaging method thereof. Background Art

[0002] Image sensor chip is an electronic device that can sense external light and convert it into electrical signals. After the image sensor chip is prepared, it needs to be packaged through a series of processes to form a packaged structure for use in various electronic devices such as digital cameras and digital video cameras.

[0003] At present, the Fanout structure is mostly used to realize the packaging of image sensor chips. In the prior art, the rewiring layer is directly prepared on the light-transmitting substrate, and the chip is directly electrically connected to the rewiring layer on the light-transmitting substrate. The connection is glued with a breathable adhesive layer to ensure the stability of the subsequent reflow soldering process. However, in the prior art, due to the use of a breathable adhesive layer for glue dispensing, the final chip packaging structure is not sealed, and the photosensitive area is exposed to the air for a long time, which seriously affects the stability and service life of the image sensor chip.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a chip packaging structure and a packaging method thereof. Summary of the invention

[0005] The object of the present invention is to provide a chip packaging structure and a packaging method thereof, which can seal a photosensitive area in an opening in a vacuum environment, thereby improving the stability and service life of the device.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A chip packaging structure, the packaging structure comprising:

[0008] A light-transmitting substrate, the light-transmitting substrate comprising an upper surface and a lower surface opposite to the upper surface;

[0009] A fan-out substrate, wherein the fan-out substrate is arranged on the lower surface of the light-transmitting substrate, wherein an opening penetrating the upper surface and the lower surface of the fan-out substrate is arranged in the fan-out substrate, wherein a groove is arranged on the upper surface of the fan-out substrate, wherein the groove is connected with the opening and the side wall of the fan-out substrate, and wherein a sealing member is arranged in the groove at the side wall of the fan-out substrate;

[0010] A chip, wherein the upper surface of the chip is arranged on the lower surface of the fan-out substrate toward the light-transmitting substrate and is electrically connected to the fan-out substrate; a photosensitive area is arranged on the upper surface of the chip and is exposed in the opening.

[0011] In one embodiment, the groove includes a first groove, a second groove and a third groove, the groove includes a first groove, the first groove is arranged outside the opening, the first groove is connected to the opening through the second groove, and the first groove is connected to the side wall of the fan-out substrate through the third groove; or,

[0012] The groove includes a first groove, a second groove, a third groove and a fourth groove, and the groove includes a plurality of first grooves, the first groove is arranged in a ring outside the opening, the innermost first groove is connected to the opening through the second groove, the outermost first groove is connected to the side wall of the fan-out substrate through the third groove, and two adjacent first grooves are connected through the fourth groove.

[0013] In one embodiment, the fan-out substrate has a thickness of 100 μm to 300 μm; and / or,

[0014] The depth of the groove is 5 μm to 15 μm.

[0015] In one embodiment, a rewiring layer is provided on the lower surface of the fan-out substrate, and the rewiring layer includes a first rewiring layer and a second rewiring layer arranged at intervals. A first solder ball is provided on the outer side of the photosensitive area, and the chip is electrically connected to the first rewiring layer on the lower surface of the fan-out substrate through the first solder ball.

[0016] In one embodiment, a sealant layer is provided at the electrical connection between the chip and the fan-out substrate, and the sealant layer at least encapsulates the first solder ball and the first redistribution layer.

[0017] In one embodiment, a first insulating layer is provided between the lower surface of the fan-out substrate and the rewiring layer, a second insulating layer is provided on the first insulating layer and the second rewiring layer, an opening is provided on the second insulating layer, the opening exposes a portion of the second rewiring layer, a second solder ball is provided in the opening and extends downward to protrude from the second insulating layer.

[0018] Another embodiment of the present invention provides a technical solution as follows:

[0019] A chip packaging method, the packaging method comprising the following steps:

[0020] Providing a fan-out substrate and etching a groove communicating with a side wall of the fan-out substrate on an upper surface of the fan-out substrate;

[0021] Providing a light-transmitting substrate and bonding the lower surface of the light-transmitting substrate to the upper surface of the fan-out substrate;

[0022] Etching the fan-out substrate to form an opening penetrating the upper surface and the lower surface of the fan-out substrate, wherein the opening is connected to the groove;

[0023] Providing a chip and electrically connecting the upper surface of the chip toward the light-transmitting substrate and the lower surface of the fan-out substrate, wherein a photosensitive area is provided on the upper surface of the chip and the photosensitive area is exposed in the opening;

[0024] A seal is fabricated in the groove at the sidewall of the fan-out substrate.

[0025] In one embodiment, providing a fan-out substrate and etching a groove on the upper surface of the fan-out substrate that is connected to the side wall of the fan-out substrate further comprises:

[0026] A groove is etched on the upper surface of the fan-out substrate, wherein the groove is located inside the groove and communicated with the groove.

[0027] In one embodiment, before etching the lower surface of the fan-out substrate, the method further includes:

[0028] preparing a first insulating layer on the lower surface of the fan-out substrate;

[0029] Preparing a first redistribution layer and a second redistribution layer spaced apart from each other on the first insulating layer;

[0030] A second insulating layer is prepared on the first insulating layer and the second rewiring layer, and a hole is opened in the second insulating layer to expose a portion of the second rewiring layer.

[0031] In one embodiment, after preparing the second insulating layer on the first insulating layer and the second redistribution layer, the method further comprises:

[0032] A second solder ball is prepared in the opening, wherein the second solder ball extends downward to protrude beyond the second insulating layer.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention adds a fan-out substrate between the chip and the light-transmitting substrate, and prepares an opening on the fan-out substrate to expose the photosensitive area of ​​the chip and a groove connected to the opening and the side wall of the fan-out substrate. At the same time, a seal is prepared in the groove on the side wall of the fan-out substrate, so that the photosensitive area is ensured to be in a vacuum environment after the chip is packaged, thereby increasing the stability and service life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 This is a schematic diagram of the chip packaging structure in Comparative Example 1 of the present invention;

[0037] Figure 2 is a schematic diagram of a chip packaging structure in Embodiment 1 of the present invention;

[0038] Figure 3 Schematic diagram of the planar structure of the fan-out substrate in Embodiment 1 of the present invention;

[0039] Figures 4a to 4j is a process flow chart of the chip packaging method in Example 1 of the present invention;

[0040] Figure 5 is a schematic diagram of a chip packaging structure in Embodiment 2 of the present invention;

[0041] Figure 6 It is a schematic diagram of the planar structure of the fan-out substrate in Example 2 of the present invention.

[0042] Description of main reference numerals:

[0043] 1-light-transmitting substrate, 2-fan-out substrate, 21-opening, 22-groove, 211-groove, 221-first groove, 222-second groove, 223-third groove, 224-fourth groove, 3-seal, 4-chip, 41-photosensitive area, 51-first redistribution layer, 52-second redistribution layer, 6-sealing glue layer, 71-first insulating layer, 72-second insulating layer, 81-first solder ball, 82-second solder ball, 9-bonding glue layer, 10-breathable glue layer. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0045] The present invention discloses a chip packaging structure, comprising:

[0046] A light-transmitting substrate, comprising an upper surface and a lower surface opposite to the upper surface;

[0047] A fan-out substrate is arranged on the lower surface of the light-transmitting substrate, an opening penetrating the upper surface and the lower surface of the fan-out substrate is arranged in the fan-out substrate, a groove is arranged on the upper surface of the fan-out substrate, the groove is connected with the opening and the side wall of the fan-out substrate, and a sealing member is arranged at the side wall of the fan-out substrate in the groove;

[0048] The chip is disposed on the lower surface of the fan-out substrate with the upper surface of the chip facing the light-transmitting substrate and is electrically connected to the fan-out substrate. A photosensitive area is disposed on the upper surface of the chip, and the photosensitive area is exposed in the opening.

[0049] The present invention also discloses a chip packaging method, comprising the following steps:

[0050] Providing a fan-out substrate and etching a groove communicating with a side wall of the fan-out substrate on an upper surface of the fan-out substrate;

[0051] Providing a light-transmitting substrate and bonding the lower surface of the light-transmitting substrate to the upper surface of the fan-out substrate;

[0052] Etching the fan-out substrate to form an opening penetrating the upper surface and the lower surface of the fan-out substrate, wherein the opening is connected to the groove;

[0053] A chip is provided and the upper surface of the chip is electrically connected to the lower surface of the fan-out substrate with the upper surface facing the light-transmitting substrate, wherein a photosensitive area is provided on the upper surface of the chip and the photosensitive area is exposed in the opening;

[0054] A seal is fabricated in the groove at the sidewall of the fan-out substrate.

[0055] The present invention is further described below with reference to specific examples.

[0056] Comparative Example 1:

[0057] Ginseng Figure 1 As shown, the chip packaging structure in this comparative example includes:

[0058] A light-transmitting substrate 1, the light-transmitting substrate 1 comprises an upper surface and a lower surface opposite to the upper surface, a rewiring layer is provided on the lower surface of the light-transmitting substrate 1, and the rewiring layer comprises a first rewiring layer 51 and a second rewiring layer 52 arranged at intervals;

[0059] The chip 4 has a photosensitive area 41 on its upper surface, a first solder ball 81 outside the photosensitive area 41 , and the upper surface of the chip 4 is electrically connected to the first redistribution layer 51 on the lower surface of the transparent substrate 1 through the first solder ball 81 .

[0060] In this comparative example, a first insulating layer 71 is provided between the lower surface of the transparent substrate 1 and the rewiring layer, a second insulating layer 72 is provided on the first insulating layer 71 and the second rewiring layer 52, an opening is provided on the second insulating layer 72, the opening exposes part of the second rewiring layer 52, a second solder ball 82 is provided in the opening, and the second solder ball 82 extends downward to protrude from the second insulating layer 72.

[0061] In this comparative example, a breathable adhesive layer 10 is provided at the electrical connection between the chip 4 and the light-transmitting substrate 1 , and the breathable adhesive layer 10 at least encapsulates the first solder ball 81 and the first redistribution layer 52 .

[0062] In this comparative example, a breathable adhesive layer 10 is used to dispense glue at the electrical connection between the chip 4 and the light-transmitting substrate 1. The chip packaging structure is not sealed after preparation, and the photosensitive area 41 is exposed to the air for a long time, which affects the stability and service life of the chip.

[0063] Embodiment 1:

[0064] Ginseng Figure 2 As shown, the chip packaging structure in this embodiment includes:

[0065] A light-transmitting substrate 1, comprising an upper surface and a lower surface opposite to the upper surface;

[0066] A fan-out substrate 2 is arranged on the lower surface of the light-transmitting substrate 1, and an opening 21 is arranged in the fan-out substrate 2, which passes through the upper surface and the lower surface of the fan-out substrate 2. A groove 22 is arranged on the upper surface of the fan-out substrate 2, and the groove 22 is connected with the opening 21 and the side wall of the fan-out substrate 2. A sealing member 3 is arranged on the side wall of the fan-out substrate 2 in the groove 22;

[0067] The chip 4 is disposed on the lower surface of the fan-out substrate 2 with its upper surface facing the transparent substrate 1 and electrically connected to the fan-out substrate 2 . A photosensitive area 41 is disposed on the upper surface of the chip 4 and is exposed in the opening 21 .

[0068] In this embodiment, the light-transmitting substrate 1 is a light-transmitting glass substrate, and the fan-out substrate 2 is a silicon substrate.

[0069] For example, in combination Figure 3 As shown, the groove 22 in this embodiment includes a first groove 221, a second groove 222, a third groove 223 and a fourth groove 224. The groove 22 in this embodiment includes a plurality of first grooves 221, the first groove 221 is arranged in a ring around the outer side of the opening 21, the innermost first groove 221 is connected to the opening 21 through the second groove 222, the outermost first groove 221 is connected to the side wall of the fan-out substrate 2 through the third groove 223, and two adjacent first grooves 221 are connected through the fourth groove 224.

[0070] Specifically, in this embodiment, the thickness of the fan-out substrate 2 is 100-300 μm, and the depth of the groove 22 is 5-15 μm, preferably 10 μm.

[0071] For example, in this embodiment, the transparent substrate 1 and the fan-out substrate 2 are bonded through the bonding adhesive layer 9 therebetween, and the groove 22 divides the upper surface of the fan-out substrate 2 into a plurality of sub-areas, which can effectively solve the problem of bubbles being easily generated in the bonding adhesive layer 9 during the bonding process. By properly controlling the amount of adhesive in the bonding adhesive layer 9, it is possible to prevent the bonding adhesive layer 9 from flowing into the groove 22 and blocking the exhaust channel.

[0072] Furthermore, a rewiring layer is provided on the lower surface of the fan-out substrate 2 , and the rewiring layer includes a first rewiring layer 51 and a second rewiring layer 52 which are arranged at intervals.

[0073] Exemplarily, a pad is provided outside the photosensitive area 41 of the chip 4, and a first solder ball 81 is provided on the pad. The first solder ball 81 is preferably a gold ball. The chip 4 is electrically connected to the first redistribution layer 51 on the lower surface of the fan-out substrate 2 through the first solder ball 81.

[0074] Furthermore, a sealant layer 6 is provided at the connection between the chip 4 and the fan-out substrate 2 , and the sealant layer 6 at least encapsulates the first solder ball 81 and the first redistribution layer 51 .

[0075] In this embodiment, a first insulating layer 71 is provided between the lower surface of the fan-out substrate 2 and the rewiring layer, a second insulating layer 72 is provided on the first insulating layer 71 and the second rewiring layer 52, an opening is provided on the second insulating layer 72, the opening exposes a portion of the second rewiring layer 52, a second solder ball 82 is provided in the opening, and the second solder ball 82 extends downward to protrude from the second insulating layer 72.

[0076] The chip packaging method in this embodiment includes the following steps:

[0077] S1. Figure 4a As shown, a fan-out substrate 2 is provided and a groove 22 communicating with the side wall of the fan-out substrate 2 is etched on the upper surface of the fan-out substrate 2 .

[0078] Exemplarily, this step further includes etching a groove 211 on the upper surface of the fan-out substrate 2 , wherein the groove 211 is located inside the groove 22 and communicates with the groove 22 .

[0079] Specifically, the groove 22 in this embodiment includes a first groove 221, a second groove 222, a third groove 223 and a fourth groove 224. The groove 22 in this embodiment includes a plurality of first grooves 221, the first groove 221 is arranged around the outside of the groove 211, the innermost first groove 221 is connected to the groove 211 through the second groove 222, the outermost first groove 221 is connected to the side wall of the fan-out substrate 2 through the third groove 223, and the two adjacent first grooves 221 are connected through the fourth groove 224. The depth of the groove 211 and the groove 22 is equal to 5 to 15 μm, preferably 10 μm. The position of the opening 21 is determined in advance by the groove 211, so as to facilitate the subsequent further etching to form the opening 21.

[0080] S2, ginseng Figure 4b As shown, a transparent substrate 1 is provided and the lower surface of the transparent substrate 1 is bonded to the upper surface of the fan-out substrate 2 .

[0081] Specifically, the transparent substrate 1 and the fan-out substrate 2 are bonded together by the bonding adhesive layer 9 , and after bonding, the upper part of the groove 22 is sealed to form an exhaust channel for vacuuming.

[0082] Combination Figure 4c As shown, after the transparent substrate 1 and the fan-out substrate 2 are bonded, the fan-out substrate 2 needs to be thinned to a desired thickness. After thinning, the thickness of the fan-out substrate 2 is 100 to 300 μm.

[0083] S3, ginseng Figure 4g As shown, the fan-out substrate 2 is etched to form an opening 21 that passes through the upper surface and the lower surface of the fan-out substrate 2 , and the opening 21 is connected to the groove 22 .

[0084] Specifically, first, a patterned photoresist layer is formed on the lower surface of the fan-out substrate 2 through an overlay process to expose the fan-out substrate 2 around the area corresponding to the groove 211; then, the exposed fan-out substrate 2 is etched using the photoresist layer as a mask until it is etched through, and the disconnected area is removed to form an opening 21 that passes through the upper and lower surfaces of the fan-out substrate 2.

[0085] More specifically, before etching the fan-out substrate 2 to form the opening 21 penetrating the upper surface and the lower surface of the fan-out substrate 2, the following steps are also included:

[0086] 1. Ginseng Figure 4d As shown, a first insulating layer 71 is prepared on the lower surface of the fan-out backplane 2 , and the first insulating layer 71 is located outside the area corresponding to the groove 211 .

[0087] 2. Ginseng Figure 4e As shown, a first re-wiring layer 51 and a second re-wiring layer 52 are prepared on the first insulating layer 71 and are spaced apart from each other.

[0088] 3. Ginseng Figure 4f As shown, a second insulating layer 72 is prepared on the first insulating layer 71 and the second rewiring layer 52 , and holes are opened in the second insulating layer 72 to expose a portion of the second rewiring layer 52 .

[0089] S4. Figure 4h As shown, a chip 4 is provided and the upper surface of the chip 4 is electrically connected to the lower surface of the fan-out substrate 2 facing the transparent substrate 1 , and a photosensitive area 41 is provided on the upper surface of the chip 4 , and the photosensitive area 41 is exposed in the opening 21 .

[0090] Exemplarily, the chip 4 is an image sensor chip. A pad is provided outside the photosensitive area 41 of the chip 4, and a first solder ball 81 is provided on the pad. The first solder ball 81 is preferably a gold ball. The chip 4 is electrically connected to the first redistribution layer 51 on the fan-out substrate 2 through the first solder ball 81.

[0091] Furthermore, after the upper surface of the chip 4 is electrically connected to the lower surface of the fan-out substrate 2, the following steps are also included:

[0092] 1. Combination Figure 4h As shown, a sealant layer 6 is prepared at the connection between the chip 4 and the fan-out substrate 2 .

[0093] 2. Ginseng Figure 4i As shown, the sealing member 3 is prepared in the third groove 223 under a vacuum environment.

[0094] Specifically, the packaging structure is first evacuated in a vacuum environment to ensure that the photosensitive area 41 of the chip 4 is in a vacuum environment; then the third groove 223 is sealed by glue in a vacuum environment; finally, the packaging structure is placed on a hot plate for drying to form a seal 3 in the third groove 223.

[0095] 3. Ginseng Figure 4j As shown, a second solder ball 82 is prepared in the opening, and the second solder ball 82 extends downward to protrude beyond the second insulating layer 72 .

[0096] It should be understood that multiple chips can be packaged simultaneously during the actual preparation process, so the chip packaging method also includes determining cutting paths, and after completing the preparation of the second solder balls 82, it also includes cutting along the cutting paths to form multiple chip packaging structures.

[0097] Embodiment 2:

[0098] Ginseng Figure 5 , Figure 6 As shown, the chip packaging structure and packaging method thereof in this embodiment are substantially the same as those in Embodiment 1, except that the groove 22 includes a first groove 221, a second groove 222 and a third groove 223, the groove 22 includes a first groove 221, the first groove 221 is arranged around the outside of the opening 21, the first groove 221 is connected to the opening 21 through the second groove 222, and the first groove 221 is connected to the side wall of the fan-out substrate 2 through the third groove 223.

[0099] It should be understood that in other embodiments, the groove 22 may be of any other shape as long as it is connected to the opening 21 and the side wall of the fan-out substrate 2 .

[0100] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0101] The present invention adds a fan-out substrate between the chip and the light-transmitting substrate, and prepares an opening on the fan-out substrate to expose the photosensitive area of ​​the chip and a groove connected to the opening and the side wall of the fan-out substrate. At the same time, a seal is prepared in the groove on the side wall of the fan-out substrate, so that the photosensitive area is ensured to be in a vacuum environment after the chip is packaged, thereby increasing the stability and service life of the chip.

[0102] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0103] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A chip packaging structure, characterized in that: The packaging structure comprises: A light-transmitting substrate, the light-transmitting substrate comprising an upper surface and a lower surface opposite to the upper surface; A fan-out substrate, wherein the fan-out substrate is arranged on the lower surface of the light-transmitting substrate, wherein an opening penetrating the upper surface and the lower surface of the fan-out substrate is arranged in the fan-out substrate, wherein a groove is arranged on the upper surface of the fan-out substrate, wherein the groove is connected with the opening and the side wall of the fan-out substrate, and wherein a sealing member is arranged in the groove at the side wall of the fan-out substrate; A chip, wherein the upper surface of the chip is arranged on the lower surface of the fan-out substrate toward the light-transmitting substrate and is electrically connected to the fan-out substrate; a photosensitive area is arranged on the upper surface of the chip and is exposed in the opening.

2. The chip packaging structure according to claim 1, characterized in that: The groove includes a first groove, a second groove and a third groove, the groove includes a first groove, the first groove is arranged outside the opening, the first groove is connected to the opening through the second groove, and the first groove is connected to the side wall of the fan-out substrate through the third groove; or, The groove includes a first groove, a second groove, a third groove and a fourth groove, and the groove includes a plurality of first grooves, the first groove is arranged in a ring outside the opening, the innermost first groove is connected to the opening through the second groove, the outermost first groove is connected to the side wall of the fan-out substrate through the third groove, and two adjacent first grooves are connected through the fourth groove.

3. The chip packaging structure according to claim 1, characterized in that: The fan-out substrate has a thickness of 100 μm to 300 μm; and / or, The depth of the groove is 5 μm to 15 μm.

4. The chip packaging structure according to claim 1, characterized in that: A rewiring layer is provided on the lower surface of the fan-out substrate, and the rewiring layer includes a first rewiring layer and a second rewiring layer arranged at intervals. A first solder ball is provided outside the photosensitive area, and the chip is electrically connected to the first rewiring layer on the lower surface of the fan-out substrate through the first solder ball.

5. The chip packaging structure according to claim 4, characterized in that: A sealant layer is provided at the electrical connection between the chip and the fan-out substrate, and the sealant layer at least encapsulates the first solder ball and the first redistribution layer.

6. The chip packaging structure according to claim 4, characterized in that: A first insulating layer is provided between the lower surface of the fan-out substrate and the rewiring layer, a second insulating layer is provided on the first insulating layer and the second rewiring layer, an opening is provided on the second insulating layer, the opening exposes part of the second rewiring layer, a second solder ball is provided in the opening and extends downward to protrude from the second insulating layer.

7. A chip packaging method, characterized in that: The packaging method comprises the following steps: Providing a fan-out substrate and etching a groove communicating with a side wall of the fan-out substrate on an upper surface of the fan-out substrate; Providing a light-transmitting substrate and bonding the lower surface of the light-transmitting substrate to the upper surface of the fan-out substrate; Etching the fan-out substrate to form an opening penetrating the upper surface and the lower surface of the fan-out substrate, wherein the opening is connected to the groove; Providing a chip and electrically connecting the upper surface of the chip toward the light-transmitting substrate and the lower surface of the fan-out substrate, wherein a photosensitive area is provided on the upper surface of the chip and the photosensitive area is exposed in the opening; A seal is fabricated in the groove at the sidewall of the fan-out substrate.

8. The chip packaging method according to claim 7, characterized in that: Providing a fan-out substrate and etching a groove on the upper surface of the fan-out substrate that is connected to the side wall of the fan-out substrate also includes: A groove is etched on the upper surface of the fan-out substrate, wherein the groove is located inside the groove and communicated with the groove.

9. The chip packaging method according to claim 7, characterized in that: Before etching the lower surface of the fan-out substrate, the following steps are also included: preparing a first insulating layer on the lower surface of the fan-out substrate; Preparing a first redistribution layer and a second redistribution layer spaced apart from each other on the first insulating layer; A second insulating layer is prepared on the first insulating layer and the second rewiring layer, and a hole is opened in the second insulating layer to expose a portion of the second rewiring layer.

10. The chip packaging method according to claim 9, characterized in that: After preparing the second insulating layer on the first insulating layer and the second redistribution layer, the method further comprises: A second solder ball is prepared in the opening, wherein the second solder ball extends downward to protrude beyond the second insulating layer.

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