LED chip with vertical structure and manufacturing method thereof

Abstract

The invention discloses a vertical-structure LED chip and a manufacturing method thereof, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps of epitaxial growth, first-round photoetching processing, eutectic bonding, substrate stripping, second-round photoetching processing and chip segmentation. Wherein a pretreatment structure is obtained after the substrate is stripped, and the N-GaN layer is exposed on the surface of the pretreatment structure; the second round of photoetching processing comprises the following steps: etching the exposed N-GaN layer to form an N hole protection structure; and carrying out roughening treatment on the surface of the N-GaN layer on which the N hole protection structure is formed. According to the invention, the N hole protection structure is formed on the N-GaN layer, so that the hole channel formed by processing the P-GaN surface can be effectively protected, and the electric leakage risk of the LED chip with the vertical structure can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical structure LED chip and a manufacturing method thereof. Background Art

[0002] Compared with horizontal structure LED chips, vertical structure LED chips have better high current resistance, heat dissipation performance and anti-static ability, so they are widely used in high-end lighting and display fields.

[0003] At present, the manufacturing process of vertical structure LED chips is complex and difficult to prepare. The manufacturing process of vertical structure LED chips includes: first completing the processing of the P-GaN surface on the epitaxial layer of the growth substrate, then transferring the chip epitaxy from the growth substrate to the supporting substrate by eutectic bonding and substrate peeling, then processing the N-GaN surface of the transferred chip epitaxy, and finally completing the chip segmentation to obtain multiple vertical structure LED chip particles.

[0004] However, the processing of the N-GaN surface involves epitaxial thinning processes such as etching and roughening, which can easily lead to over-etching or over-corrosion, causing damage to the channels formed by the P-GaN surface processing, thereby increasing the leakage risk of the vertical structure LED chip. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a vertical structure LED chip and a manufacturing method thereof. By forming an N-hole protection structure in the N-GaN layer, the holes formed by P-GaN surface processing can be effectively protected, which is beneficial to reducing the leakage risk of the vertical structure LED chip.

[0006] The present invention provides a method for manufacturing a vertical structure LED chip, the manufacturing method comprising epitaxial growth, a first round of photolithography processing, eutectic bonding, substrate stripping, a second round of photolithography processing and chip segmentation; wherein, after the substrate is stripped, a pre-processed structure is obtained, and an N-GaN layer is exposed on the surface of the pre-processed structure;

[0007] The second round of photolithography processing includes: etching the exposed N-GaN layer to form an N-hole protection structure; and roughening the surface of the N-GaN layer forming the N-hole protection structure.

[0008] Specifically, the epitaxial growth includes:

[0009] S11, forming an epitaxial layer on a growth substrate, wherein the epitaxial layer includes, from bottom to top, an N-GaN layer, an MQW layer, and a P-GaN layer;

[0010] The first round of photolithography processing includes:

[0011] S21, forming a plurality of first channels distributed at intervals in the epitaxial layer, wherein the first channels penetrate the P-GaN layer and the MQW layer and expose the N-GaN layer;

[0012] S22, forming an ITO transparent conductive layer on a preset area of ​​the epitaxial layer, wherein the ITO transparent conductive layer avoids the first channel;

[0013] S23, forming an insulating passivation layer along the surface of the first channel, wherein the insulating passivation layer extends to wrap around the side wall of the ITO transparent conductive layer;

[0014] S24, forming a silver reflective layer on the ITO transparent conductive layer, wherein two sides of the silver reflective layer are in contact with the insulating passivation layer;

[0015] S25, forming a silver mirror protection layer on the silver reflection layer, wherein the silver mirror protection layer extends to cover the junction between the silver reflection layer and the insulating passivation layer;

[0016] The silver mirror protection layer extends in a preset area to form a P-type metal connection portion, and the projection of the P-type metal connection portion in the vertical direction avoids the silver reflective layer and the ITO transparent conductive layer;

[0017] S26, forming an insulating protective layer along the surfaces of the silver mirror protective layer and the insulating passivation layer;

[0018] S27, etching the insulating protection layer and the insulating passivation layer to form a plurality of second channels, wherein any second channel correspondingly exposes an N-GaN layer at the bottom of the first channel;

[0019] The eutectic bonding comprises:

[0020] S31, forming a first bonding layer on the insulating protection layer, wherein the first bonding layer fills the second channel and the first channel;

[0021] S32, forming a second bonding layer on the supporting substrate;

[0022] S33, performing a bonding process on the first bonding layer and the second bonding layer to obtain a bonded wafer;

[0023] The substrate stripping comprises:

[0024] S41, peeling off the growth substrate of the bonded wafer by laser to obtain the pre-processed structure;

[0025] The second round of photolithography processing includes:

[0026] S51, etching the exposed N-GaN layer to form a plurality of N-hole protection structures distributed at intervals, wherein the N-hole protection structures correspond to the first holes one by one;

[0027] The N-hole protection structure protrudes in a direction away from the support substrate, and a projection of the first hole on the N-GaN layer falls within a coverage range of the N-hole protection structure;

[0028] S52, roughening the surface of the N-GaN layer forming the N hole protection structure by using an alkaline solution;

[0029] S53, etching to form a groove in a preset chip structure edge region, wherein the groove extends from the roughened N-GaN layer surface to the surface of the insulating passivation layer;

[0030] The inner side of the groove is a chip main body structure, and the outer side of the groove is a retaining wall structure;

[0031] The groove includes a first groove and a second groove, the width of the second groove is greater than the width of the first groove, and the projection of the second groove in the vertical direction overlaps with the P-type metal connecting portion;

[0032] S54, etching the insulating passivation layer at the bottom of the second groove to form a third channel, wherein the third channel exposes the P-type metal connecting portion;

[0033] S55, forming a P-type pad metal layer in the second groove and the third channel, with a gap between the P-type pad metal layer and the inner wall of the second groove;

[0034] S56, grinding and thinning a side of the support substrate away from the P-type pad metal layer;

[0035] S57, forming an N-type pad metal layer on one side of the support substrate after grinding and thinning, to obtain a finished wafer;

[0036] The chip segmentation comprises:

[0037] S61, cutting the finished wafer by laser to obtain a plurality of vertical structure LED chip particles.

[0038] Specifically, the growth substrate is a sapphire substrate;

[0039] The depth of the first channel ranges from 0.7 to 1.3 μm;

[0040] The thickness of the ITO transparent conductive layer is

[0041] The insulating passivation layer is made of SiO 2 Single layer, SiNx Single layer or SiO 2 / SiN x The composite film layer is composed of the insulating passivation layer, and the thickness range is

[0042] The silver reflective layer is composed of a silver bottom layer and a reflective surface layer, and the thickness of the silver bottom layer is in the range of The thickness of the reflective surface layer is in the range of

[0043] The material of the silver mirror protective layer includes one or more of Cr, Au, Pt, Ni, and Ti. The thickness of the silver mirror protective layer is

[0044] The insulating protective layer is made of SiO 2 Single layer, SiN x Single layer or SiO 2 / SiN x The thickness of the insulating protective layer is in the range of

[0045] The first bonding layer is composed of a first Cr bottom layer and a first bonding surface layer, and the thickness of the first Cr bottom layer is in the range of The total thickness of the first bonding layer is in the range of

[0046] The support substrate is a silicon-based substrate, the resistivity of the silicon-based substrate is lower than 0.005Ω.cm, and the thickness of the silicon-based substrate is in the range of 500 to 1000μm;

[0047] The second bonding layer is composed of a second Cr bottom layer and a second bonding surface layer, and the thickness of the second Cr bottom layer is in the range of The total thickness of the second bonding layer is in the range of 35000 to

[0048]

[0049] The protrusion height of the N-hole protection structure ranges from 0.7 to 1.3 μm;

[0050] Grinding and thinning the support substrate to 150-200 μm;

[0051] The N-type pad metal layer includes a first pad bottom layer and a first pad surface layer, the material of the first pad bottom layer is Cr or Ti, and the thickness of the first pad bottom layer is in the range of The material of the surface layer of the first pad is Au, and the thickness range of the surface layer of the first pad is

[0052] Specifically, step S22 also includes:

[0053] The ITO transparent conductive layer is annealed in a vacuum rapid annealing furnace, the temperature range of the annealing is 540-560° C., and the duration range of the annealing is 8-12 minutes.

[0054] Specifically, step S23 includes:

[0055] First, an insulating passivation layer is deposited along the surface of the ITO transparent conductive layer and the first hole, and then a part of the insulating passivation layer on the ITO transparent conductive layer is removed by etching to form a reflective window.

[0056] Specifically, step S24 includes:

[0057] A silver reflective layer is deposited in the reflective window.

[0058] Specifically, the silicon-based substrate is cleaned in sequence with isopropyl alcohol, acetone, SPM solution and BOE solution for 5 to 10 minutes before use.

[0059] Specifically, in step S33, the bonding pressure of the bonding process is controlled at 6000-8000 kg / cm 2 The bonding temperature of the bonding process is controlled at 250-270° C., and the bonding time of the bonding process is controlled at 30-60 min.

[0060] Specifically, in step S52, the alkaline solution is a KOH solution, the duration of the roughening treatment is controlled to be 5 to 8 minutes, and the temperature of the roughening treatment is controlled to be 50 to 60°C.

[0061] The present invention also provides a vertical structure LED chip, and the vertical structure LED chip is manufactured by the manufacturing method of the vertical structure LED chip.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The present invention forms an N-hole protection structure on the exposed N-GaN layer. The N-hole protection structure can serve as a barrier and is not easily etched through or corroded through. It can not only reduce the risk of damaging the P-GaN surface channel when etching the N-GaN layer, but also reduce the risk of damaging the P-GaN surface channel during the roughening of the N-GaN layer surface. It can effectively protect the channels formed by P-GaN surface processing and avoid perforation of the channels formed by P-GaN surface processing, thereby helping to reduce the leakage risk of vertical structure LED chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0065] Figure 1 is a schematic flow chart of a method for manufacturing a vertical structure LED chip in an embodiment of the present invention;

[0066] Figure 2 is a schematic diagram of the process of epitaxial growth in an embodiment of the present invention;

[0067] Figure 3 is a schematic structural diagram of a growth substrate and an epitaxial layer in an embodiment of the present invention;

[0068] Figure 4 is a schematic diagram of the process of the first round of photolithography processing in an embodiment of the present invention;

[0069] Figure 5 is a schematic structural diagram of the first channel in an embodiment of the present invention;

[0070] Figure 6 is a schematic structural diagram of an ITO transparent conductive layer in an embodiment of the present invention;

[0071] Figure 7 is a schematic structural diagram of an insulating passivation layer in an embodiment of the present invention;

[0072] Figure 8 is a schematic structural diagram of a silver reflective layer in an embodiment of the present invention;

[0073] Fig. 9 Schematic diagram of the structure of the silver mirror protective layer in an embodiment of the present invention;

[0074] Fig.10 is a schematic structural diagram of an insulating protective layer in an embodiment of the present invention;

[0075] Fig.11 is a schematic structural diagram of the second channel in an embodiment of the present invention;

[0076] Fig.12 is a schematic diagram of the process of eutectic bonding in an embodiment of the present invention;

[0077] Fig.13 is a schematic structural diagram of the first bonding layer in an embodiment of the present invention;

[0078] Fig.14 is a schematic structural diagram of a supporting substrate and a second bonding layer in an embodiment of the present invention;

[0079] Fig.15 is a schematic structural diagram of a bonded wafer in an embodiment of the present invention;

[0080] Fig.16 is a schematic diagram of the process of substrate peeling in an embodiment of the present invention;

[0081] Fig.17 is a structural schematic diagram of a preprocessing structure in an embodiment of the present invention;

[0082] Fig.18 is a schematic diagram of the process of the second round of photolithography processing in an embodiment of the present invention;

[0083] Fig.19 is a schematic structural diagram of an N-hole protection structure in an embodiment of the present invention;

[0084] Fig. 20 is a schematic structural diagram of a rough surface of an N-GaN layer in an embodiment of the present invention;

[0085] Fig.21 is a schematic diagram of the structure of the groove in an embodiment of the present invention;

[0086] Fig. 22 is a schematic structural diagram of the third channel in an embodiment of the present invention;

[0087] Fig.23 is a schematic structural diagram of a P-type pad metal layer in an embodiment of the present invention;

[0088] Fig.24 is a schematic diagram of a structure in which a supporting substrate is thinned in an embodiment of the present invention;

[0089] Fig.25 is a schematic structural diagram of an N-type pad metal layer in an embodiment of the present invention;

[0090] Fig.26 It is a schematic diagram of the chip segmentation process in an embodiment of the present invention.

[0091] In the accompanying drawings, 110, growth substrate; 120, N-GaN layer; 121, N-hole protection structure; 130, MQW layer; 140, P-GaN layer; 210, first channel; 220, ITO transparent conductive layer; 230, insulating passivation layer; 231, reflective window; 240, silver reflective layer; 250, silver mirror protection layer; 251, P-type metal connection; 260, insulating protection layer; 270, second channel; 310, first bonding layer; 321, supporting substrate; 322, second bonding layer; 330, eutectic bonding metal layer; 400, groove; 410, first groove; 420, second groove; 430, third channel; 500, retaining wall structure; 610, P-type pad metal layer; 620, N-type pad metal layer. DETAILED DESCRIPTION

[0092] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0093] The present invention provides a method for manufacturing a vertical structure LED chip. Figure 1 A schematic flow chart of a method for manufacturing a vertical structure LED chip in an embodiment of the present invention is shown, wherein the manufacturing method comprises: S1, epitaxial growth; S2, a first round of photolithography processing; S3, eutectic bonding; S4, substrate peeling; S5, a second round of photolithography processing; S6, chip segmentation; wherein, after the substrate is peeled off, a pre-processed structure is obtained, and the N-GaN layer 120 is exposed on the surface of the pre-processed structure;

[0094] The second round of photolithography includes: etching the exposed N-GaN layer 120 to form an N-hole protection structure 121 ; and roughening the surface of the N-GaN layer 120 where the N-hole protection structure 121 is formed.

[0095] The present invention forms an N-hole protection structure 121 on the exposed N-GaN layer 120. The N-hole protection structure 121 can serve as a barrier and is not easily etched through or corroded through. It can not only reduce the risk of damaging the P-GaN surface channels when etching the N-GaN layer 120, but also reduce the risk of damaging the P-GaN surface channels during the surface roughening of the N-GaN layer 120. It can effectively protect the channels formed by P-GaN surface processing and avoid perforation of the channels formed by P-GaN surface processing, thereby helping to reduce the leakage risk of vertical structure LED chips.

[0096] In some specific embodiments, Figure 2 A schematic diagram of the process of epitaxial growth in an embodiment of the present invention is shown, wherein the epitaxial growth comprises:

[0097] S11, forming an epitaxial layer on a growth substrate, wherein the epitaxial layer includes, from bottom to top, an N-GaN layer, an MQW layer, and a P-GaN layer;

[0098] Figure 3 A schematic diagram of the structure of a growth substrate and an epitaxial layer in an embodiment of the present invention is shown.

[0099] The growth substrate 110 is a sapphire substrate, which is easy to grow the N-GaN layer 120, the MQW layer 130 and the P-GaN layer 140; and the sapphire substrate has high mechanical strength and is easy to handle and clean.

[0100] In some specific embodiments, Figure 4 The schematic diagram of the process of the first round of photolithography processing in an embodiment of the present invention is shown, and the first round of photolithography processing includes:

[0101] S21, forming a plurality of first channels distributed at intervals in the epitaxial layer, wherein the first channels penetrate the P-GaN layer and the MQW layer and expose the N-GaN layer;

[0102] Figure 5 A schematic structural diagram of the first channel in an embodiment of the present invention is shown.

[0103] The first channel 210 is a MESA hole with an inverted trapezoidal structure, which facilitates the subsequent formation of a film layer on the side wall of the first channel 210; the first channel 210 is formed by photolithography patterning and dry etching (such as ICP process), and the depth of the first channel 210 ranges from 0.7 to 1.3 μm. The first channel 210 penetrates a certain distance into the N-GaN layer 120.

[0104] Optionally, the depth of the first channel 210 may be 0.7 μm, 1.0 μm or 1.3 μm.

[0105] S22, forming an ITO transparent conductive layer on a preset area of ​​the epitaxial layer, wherein the ITO transparent conductive layer avoids the first channel;

[0106] Figure 6 The schematic diagram of the structure of the ITO transparent conductive layer in the embodiment of the present invention is shown.

[0107] Specifically, an ITO transparent conductive layer 220 is formed by photolithography and wet etching. The thickness of the ITO transparent conductive layer 220 is On the one hand, it can expand the current, and on the other hand, it can reduce the absorption of light. Preferably, the thickness of the ITO transparent conductive layer 220 is Excellent effect of spreading current.

[0108] Furthermore, there is a certain gap between the edge of the ITO transparent conductive layer 220 and the edge of the first channel 210, so as to avoid the edge of the ITO transparent conductive layer 220 and the edge of the first channel 210 from being connected, so as to facilitate the subsequent insulating passivation layer 230 to extend and wrap around the side wall of the ITO transparent conductive layer 220, and to prevent other element substances from migrating from the edge of the ITO transparent conductive layer 220 into the edge of the first channel 210 during the subsequent deposition of the film layer.

[0109] In some specific embodiments, step S22 further includes: annealing the ITO transparent conductive layer 220 in a vacuum rapid annealing furnace, wherein the temperature range of the annealing is 540-560° C., and the duration range of the annealing is 8-12 min, which is beneficial to reducing the resistance value of the ITO transparent conductive layer 220. Preferably, the temperature of the annealing is 550° C., and the duration range of the annealing is 10 min, which has an excellent effect of reducing the resistance value.

[0110] S23, forming an insulating passivation layer along the surface of the first channel, wherein the insulating passivation layer extends to wrap around the side wall of the ITO transparent conductive layer;

[0111] Figure 7 A schematic structural diagram of an insulating passivation layer in an embodiment of the present invention is shown.

[0112] Specifically, the insulating passivation layer 230 is first deposited along the surface of the ITO transparent conductive layer 220 and the first channel 210, and then a part of the insulating passivation layer 230 on the ITO transparent conductive layer 220 is etched and removed to form a reflective window 231, so that the insulating passivation layer 230 can extend to wrap around the side wall of the ITO transparent conductive layer 220, and play a good protective role on the side wall of the ITO transparent conductive layer 220; the reflective window 231 is a reserved position for depositing the silver reflective layer 240, which is beneficial for the insulating passivation layer 230 to protect the side wall of the silver reflective layer 240; at the same time, the reflective window 231 does not reveal the edge of the ITO transparent conductive layer 220, which can avoid the edge of the subsequently formed silver reflective layer 240 from connecting with the edge of the ITO transparent conductive layer 220.

[0113] Furthermore, the insulating passivation layer 230 is made of SiO 2 Single layer, SiN x Single layer or SiO 2 / SiN x The thickness of the insulating passivation layer 230 is in the range of Good insulation effect.

[0114] S24, forming a silver reflective layer on the ITO transparent conductive layer, wherein two sides of the silver reflective layer are in contact with the insulating passivation layer;

[0115] Figure 8 The schematic diagram of the structure of the silver reflective layer in the embodiment of the present invention is shown.

[0116] Specifically, the silver reflection layer 240 is deposited in the reflection window 231 by magnetron sputtering; moreover, the thickness of the silver reflection layer 240 is less than or equal to the thickness of the insulating passivation layer 230, which is beneficial to confine the silver reflection layer 240 in the reflection window 231 and reduce the migration of silver elements in the silver reflection layer 240.

[0117] Furthermore, the silver reflective layer 240 is composed of a silver bottom layer and a reflective surface layer. The silver reflective layer 240 is a laminated structure with good light reflection effect. The thickness of the silver bottom layer ranges from It can effectively reflect light; the thickness of the reflective surface layer is in the range of The material of the reflective surface layer includes one or more of Ti, W, Ni, and Pt, which is beneficial to protecting the silver bottom layer.

[0118] S25, forming a silver mirror protection layer on the silver reflection layer, wherein the silver mirror protection layer extends to cover the junction between the silver reflection layer and the insulating passivation layer;

[0119] Fig. 9 The schematic diagram of the structure of the silver mirror protective layer in the embodiment of the present invention is shown.

[0120] A silver mirror protective layer 250 is formed on the silver reflective layer 240 by means of photolithography patterning and electron beam evaporation (EBM). The silver mirror protective layer 250 can not only protect the silver reflective layer 240, but also increase the large current expansion capability of the vertical structure LED chip; moreover, since the silver mirror protective layer 250 extends to cover the junction of the silver reflective layer 240 and the insulating passivation layer 230, it can effectively prevent the migration of silver elements at high temperatures.

[0121] Specifically, the silver mirror protective layer 250 extends in a preset area to form a P-type metal connecting portion 251, and the projection of the P-type metal connecting portion 251 in the vertical direction avoids the silver reflective layer 240 and the ITO transparent conductive layer 220, so as to facilitate the connection between the subsequently formed P-type pad metal layer 610 and the silver mirror protective layer 250.

[0122] Furthermore, the material of the silver mirror protective layer 250 includes one or more of Cr, Au, Pt, Ni, and Ti, and the thickness of the silver mirror protective layer 250 is The silver reflective layer 240 can be effectively protected and the current can be expanded.

[0123] S26, forming an insulating protective layer along the surfaces of the silver mirror protective layer and the insulating passivation layer;

[0124] Fig.10 A schematic structural diagram of an insulating protective layer in an embodiment of the present invention is shown.

[0125] The insulating protection layer 260 is not only used to separate the silver mirror protection layer 250 from the subsequent first bonding layer 310, but also used to further enhance the electrical isolation effect on the side wall of the first channel 210, which is beneficial to improving the working reliability of the vertical structure LED chip under high current conditions.

[0126] Specifically, the insulating protection layer 260 is made of SiO 2 Single layer, SiN x Single layer or SiO 2 / SiN x The thickness of the insulating protective layer 260 is in the range of Can provide strong insulation protection effect.

[0127] S27, etching the insulating protection layer and the insulating passivation layer to form a plurality of second channels, wherein any second channel correspondingly exposes an N-GaN layer at the bottom of the first channel;

[0128] Fig.11 A schematic structural diagram of the second channel in an embodiment of the present invention is shown.

[0129] The second channel 270 is formed by an ICP etching process. The second channel 270 is used to expose the N-GaN layer 120 to facilitate the subsequent electrical connection between the first bonding layer 310 and the N-GaN layer 120 .

[0130] In some specific embodiments, Fig.12 A schematic diagram of the process of eutectic bonding in an embodiment of the present invention is shown, and the eutectic bonding includes:

[0131] S31, forming a first bonding layer on the insulating protection layer, wherein the first bonding layer fills the second channel and the first channel;

[0132] Fig.13 A schematic structural diagram of the first bonding layer in an embodiment of the present invention is shown.

[0133] The first bonding layer 310 is connected to the N-GaN layer 120 through the first hole 210 and the second hole 270 to form electrical connection; moreover, the first bonding layer 310 has a flat surface to facilitate subsequent bonding.

[0134] Specifically, the first bonding layer 310 is composed of a first Cr bottom layer and a first bonding surface layer, and the thickness of the first Cr bottom layer is in the range of The first Cr bottom layer can form good adhesion with the insulating protection layer 260, which is beneficial to improve the stability of the first bonding layer 310; the material of the first bonding surface layer includes metals such as Al, Ti, Ni, Sn and Au, and the total thickness of the first bonding layer 310 is in the range of It is conducive to forming a good bonding effect.

[0135] S32, forming a second bonding layer on the supporting substrate;

[0136] Fig.14A schematic structural diagram of a supporting substrate and a second bonding layer in an embodiment of the present invention is shown.

[0137] Specifically, the support substrate 321 is a silicon-based substrate, the resistivity of the silicon-based substrate is lower than 0.005Ω.cm, the thickness of the silicon-based substrate is in the range of 500 to 1000μm, and has good conductive properties.

[0138] The silicon-based substrate is cleaned with isopropyl alcohol, acetone, SPM solution and BOE solution for 5 to 10 minutes in sequence before use to ensure that impurities and dirt on the surface of the silicon-based substrate are completely removed to ensure the quality and reliability of subsequent processes.

[0139] Furthermore, the second bonding layer 322 is composed of a second Cr bottom layer and a second bonding surface layer, and the thickness of the second Cr bottom layer is in the range of The second Cr bottom layer can form good adhesion with the supporting substrate 321, which is beneficial to improve the stability of the second bonding layer 322; the material of the second bonding surface layer includes metals such as Al, Ti, Ni, Sn and Au, and the total thickness of the second bonding layer 322 is in the range of It is conducive to forming a good bonding effect.

[0140] S33, performing a bonding process on the first bonding layer and the second bonding layer to obtain a bonded wafer;

[0141] Fig.15 A schematic structural diagram of a bonded wafer in an embodiment of the present invention is shown.

[0142] Specifically, the bonding pressure of the bonding process is controlled at 6000-8000 kg / cm 2 The bonding temperature of the bonding process is controlled at 250-270° C., and the bonding time of the bonding process is controlled at 30-60 min to ensure that the first bonding layer 310 and the second bonding layer 322 are fully integrated to form a firm and reliable eutectic bonding metal layer 330 .

[0143] In some specific embodiments, Fig.16 A schematic diagram of the process of substrate peeling in an embodiment of the present invention is shown, wherein the substrate peeling includes:

[0144] S41, peeling off the growth substrate of the bonded wafer by laser to obtain the pre-processed structure;

[0145] Fig.17 A structural schematic diagram of a preprocessing structure in an embodiment of the present invention is shown.

[0146] The growth substrate 110 is a sapphire substrate, and the laser can completely separate the sapphire substrate from the epitaxial layer, thereby epitaxially transferring the chip to the support substrate 321 .

[0147] Specifically, before laser lift-off, the sapphire substrate is ground and polished for at least 30 minutes so that the laser can better penetrate the sapphire substrate, thereby achieving a better lift-off effect.

[0148] In some specific embodiments, Fig.18 The schematic diagram of the process of the second round of photolithography processing in an embodiment of the present invention is shown, and the second round of photolithography processing includes:

[0149] S51, etching the exposed N-GaN layer to form a plurality of N-hole protection structures distributed at intervals, wherein the N-hole protection structures correspond to the first holes one by one;

[0150] Fig.19 A schematic structural diagram of an N-hole protection structure in an embodiment of the present invention is shown, wherein the N-hole protection structure 121 protrudes in a direction away from the support substrate 321, and the projection of the first hole 210 on the N-GaN layer 120 falls within the coverage of the N-hole protection structure 121;

[0151] The N-hole protection structure 121 can serve as a barrier, which is not easily etched through or corroded through. It can not only reduce the risk of damaging the first channel 210 when etching the N-GaN layer 120, but also reduce the risk of damaging the first channel 210 during the subsequent roughening of the surface of the N-GaN layer 120. It can effectively protect the first channel 210 and avoid perforation problems at the position of the first channel 210, thereby helping to reduce the leakage risk of the vertical structure LED chip.

[0152] Specifically, the protrusion height of the N-hole protection structure 121 ranges from 0.7 to 1.3 μm. The protrusion height of the N-hole protection structure 121 is consistent with the etching depth of the first hole channel 210 , and can effectively protect the first hole channel 210 .

[0153] S52, roughening the surface of the N-GaN layer forming the N hole protection structure by using an alkaline solution;

[0154] Fig. 20 A schematic structural diagram of a rough surface of an N-GaN layer in an embodiment of the present invention is shown.

[0155] The roughening treatment can make the N-GaN layer 120 form a rough surface, which is conducive to the light emission of the vertical structure LED chip. During the roughening process, the corrosion rate of the alkaline solution is easily affected by environmental factors such as temperature and fluctuates, which can easily lead to over-corrosion; however, the existence of the N hole protection structure 121 can avoid the problem of perforation of the first channel 210 caused by over-corrosion.

[0156] Specifically, the alkaline solution is a KOH solution, the duration of the roughening treatment is controlled to be 5 to 8 minutes, and the temperature of the roughening treatment is controlled to be 50 to 60° C., which can effectively roughen the surface of the N-GaN layer 120 on the one hand, and reduce the occurrence of over-corrosion on the other hand.

[0157] S53, etching to form a groove in a preset chip structure edge region, wherein the groove extends from the roughened N-GaN layer surface to the surface of the insulating passivation layer;

[0158] Fig.21 The schematic diagram of the structure of the groove in the embodiment of the present invention is shown. The inner side of the groove 400 is the chip main structure (light-emitting area), and the outer side of the groove 400 is the retaining wall structure 500. The retaining wall structure 500 can prevent the slag from contacting the chip main structure (light-emitting area) during subsequent laser cutting, thereby avoiding leakage of the chip main structure (light-emitting area), which is beneficial to improving the manufacturing yield of vertical structure LED chips. Moreover, in the subsequent solid crystal packaging process of vertical structure LED chip particles, the retaining wall structure 500 can avoid leakage of chip edge slurry, which is beneficial to reduce the risk of leakage during packaging.

[0159] Specifically, the groove 400 includes a first groove 410 and a second groove 420, the width of the second groove 420 is larger than the width of the first groove 410, and the projection of the second groove 420 in the vertical direction overlaps with the P-type metal connection part 251, which facilitates the subsequent lead-out of the P-type pad metal layer 610.

[0160] S54, etching the insulating passivation layer at the bottom of the second groove to form a third channel, wherein the third channel exposes the P-type metal connecting portion;

[0161] Fig. 22 A schematic structural diagram of the third channel in an embodiment of the present invention is shown.

[0162] The insulating passivation layer 230 at the bottom of the second groove 420 is etched by photolithography and BOE wet etching to form a third channel 430 , which is convenient for the subsequent extraction of the P-type pad metal layer 610 .

[0163] S55, forming a P-type pad metal layer in the second groove and the third channel, with a gap between the P-type pad metal layer and the inner wall of the second groove;

[0164] Fig.23 A schematic diagram of the structure of a P-type pad metal layer in an embodiment of the present invention is shown.

[0165] A P-type pad metal layer 610 is formed on the P-type metal connection portion 251 by electron beam evaporation (EBM), and the P-type pad metal layer 610 extends at least to the notch of the second groove 420 to facilitate the lead welding of the vertical structure LED chip; there is a gap between the P-type pad metal layer 610 and the inner wall of the second groove 420 to prevent the P-type pad metal layer 610 from directly contacting the chip main structure and causing a short circuit.

[0166] S56, grinding and thinning a side of the support substrate away from the P-type pad metal layer;

[0167] Fig.24 A schematic diagram of the structure of thinning the supporting substrate in an embodiment of the present invention is shown.

[0168] Specifically, the support substrate 321 is ground and thinned to 150-200 μm to reduce the resistance value of the support substrate 321 and obtain better conductive performance.

[0169] S57, forming an N-type pad metal layer on one side of the support substrate after grinding and thinning, to obtain a finished wafer;

[0170] Fig.25 A schematic structural diagram of an N-type pad metal layer in an embodiment of the present invention is shown.

[0171] Specifically, the N-type pad metal layer 620 covers the entire surface of the supporting substrate 321 . The N-type pad metal layer 620 has a large area, which is convenient for mounting the vertical structure LED chip.

[0172] Furthermore, the N-type pad metal layer 620 includes a first pad bottom layer and a first pad surface layer, the material of the first pad bottom layer is Cr or Ti, and the thickness of the first pad bottom layer is in the range of The first pad bottom layer can form good adhesion with the supporting substrate 321, which is beneficial to improve the stability of the N-type pad metal layer 620; the material of the first pad surface layer is Au, and the thickness range of the first pad surface layer is This is beneficial for the N-type pad metal layer 620 to form good electrical contact with the connection object.

[0173] In some specific embodiments, Fig.26 A schematic diagram of a chip segmentation process in an embodiment of the present invention is shown, wherein the chip segmentation comprises:

[0174] S61, cutting the finished wafer by laser to obtain a plurality of vertical structure LED chip particles.

[0175] When laser cutting is performed, the retaining wall structure 500 can prevent the slag from contacting the chip main structure (light-emitting area), thereby preventing the chip main structure (light-emitting area) from leaking electricity.

[0176] In some specific embodiments, the vertical structure LED chip particles are die-bonded to obtain a finished vertical structure LED chip.

[0177] The manufacturing method of the vertical structure LED chip of the present invention can not only reduce the risk of damaging the first channel 210 when etching the N-GaN layer 120, but also reduce the risk of damaging the first channel 210 during the subsequent surface roughening of the N-GaN layer 120 by forming an N-hole protection structure 121. It can effectively protect the first channel 210 and avoid perforation problems at the position of the first channel 210, thereby helping to reduce the leakage risk of the vertical structure LED chip.

[0178] Moreover, by forming the retaining wall structure 500, the slag during laser cutting can be blocked from contacting the chip main structure (light-emitting area), thereby avoiding leakage of the chip main structure (light-emitting area), which is beneficial to improving the manufacturing yield of vertical structure LED chips; during the solid crystal packaging process, the retaining wall structure 500 can avoid leakage of slurry at the edge of the chip, which is beneficial to reducing the risk of leakage during packaging.

[0179] In addition, the edges between the first channel 210, the ITO transparent conductive layer 220, the insulating passivation layer 230, the silver reflective layer 240 and the silver mirror protective layer 250 are staggered and not connected to each other, which is beneficial to prevent other element substances from migrating along the edge connections and can improve the working stability of the vertical structure LED chip.

[0180] The present invention also provides a vertical structure LED chip, which is manufactured by the manufacturing method of the vertical structure LED chip, see Fig.25 The vertical structure LED chip includes, from bottom to top, an N-type pad metal layer 620, a supporting substrate 321, a eutectic bonding metal layer 330, an insulating protection layer 260, an insulating passivation layer 230, a P-GaN layer 140, an MQW layer 130 and an N-GaN layer 120;

[0181] The eutectic bonding metal layer 330 protrudes in a direction away from the support substrate 321 to form a plurality of first protrusions distributed at intervals, and the first protrusions can extend into the N-GaN layer 120; the insulating protection layer 260 and the insulating passivation layer 230 cover the surface of the first protrusions; the top of the first protrusion protrudes in a direction away from the support substrate 321 to form a second protrusion, and the second protrusion passes through the insulating protection layer 260 and the insulating passivation layer 230 to directly contact the N-GaN layer 120;

[0182] The N-GaN layer 120 protrudes in a direction away from the support substrate 321 to form a plurality of N-hole protection structures 121 distributed at intervals, the N-hole protection structures 121 correspond to the first protrusions one by one, and the projection of the N-hole protection structures 121 on the eutectic bonding metal layer 330 completely covers the first protrusions;

[0183] The side of the N-GaN layer 120 away from the supporting substrate 321 is a rough surface;

[0184] Outside the vertical projection range of the N-hole protection structure 121, an ITO transparent conductive layer 220, a silver reflective layer 240 and a silver mirror protective layer 250 are sequentially arranged below the P-GaN layer 140 from top to bottom, the ITO transparent conductive layer 220 is in direct contact with the P-GaN layer 140, the insulating passivation layer 230 wraps the ITO transparent conductive layer 220 and the silver reflective layer 240, the insulating protective layer 260 wraps the silver mirror protective layer 250, and the silver mirror protective layer 250 is in direct contact with the insulating passivation layer 230; the silver mirror protective layer 250 extends in the insulating protective layer 260 to form a P-type metal connecting portion 251, and the projection of the P-type metal connecting portion 251 in the vertical direction avoids the silver reflective layer 240 and the ITO transparent conductive layer 220;

[0185] A groove 400 is provided in the edge area of ​​the vertical structure LED chip, and the groove 400 extends from the surface of the N-GaN layer 120 to the surface of the insulating passivation layer 230; the inner side of the groove 400 is the chip main structure (light-emitting area), and the outer periphery of the groove 400 is a retaining wall structure 500; the groove 400 includes a first groove 410 and a second groove 420, and the width of the second groove 420 is larger than the width of the first groove 410; a P-type pad metal layer 610 is provided in the second groove 420, and the lower end of the P-type pad metal layer 610 passes through the insulating passivation layer 230 and is connected to the P-type metal connecting part 251, and the upper end of the P-type pad metal layer 610 extends at least to the notch of the second groove 420.

[0186] The vertical structure LED chip of the present invention has high current resistance, good heat dissipation performance, strong antistatic ability, high brightness, good working stability and high reliability.

[0187] The vertical structure LED chip and its manufacturing method provided by the embodiment of the present invention are introduced in detail above. The principle and implementation mode of the present invention are explained by using specific examples herein. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for the general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for manufacturing a vertical structure LED chip, characterized in that: The manufacturing method includes epitaxial growth, a first round of photolithography, eutectic bonding, substrate stripping, a second round of photolithography and chip segmentation; wherein, after the substrate is stripped, a pre-processed structure is obtained, and the N-GaN layer is exposed on the surface of the pre-processed structure; The second round of photolithography processing includes: etching the exposed N-GaN layer to form an N-hole protection structure; and roughening the surface of the N-GaN layer forming the N-hole protection structure.

2. The method for manufacturing a vertical structure LED chip according to claim 1, characterized in that: The epitaxial growth comprises: S11, forming an epitaxial layer on a growth substrate, wherein the epitaxial layer includes, from bottom to top, an N-GaN layer, an MQW layer, and a P-GaN layer; The first round of photolithography processing includes: S21, forming a plurality of first channels distributed at intervals in the epitaxial layer, wherein the first channels penetrate the P-GaN layer and the MQW layer and expose the N-GaN layer; S22, forming an ITO transparent conductive layer on a preset area of ​​the epitaxial layer, wherein the ITO transparent conductive layer avoids the first channel; S23, forming an insulating passivation layer along the surface of the first channel, wherein the insulating passivation layer extends to wrap around the side wall of the ITO transparent conductive layer; S24, forming a silver reflective layer on the ITO transparent conductive layer, wherein two sides of the silver reflective layer are in contact with the insulating passivation layer; S25, forming a silver mirror protection layer on the silver reflection layer, wherein the silver mirror protection layer extends to cover the junction between the silver reflection layer and the insulating passivation layer; The silver mirror protection layer extends in a preset area to form a P-type metal connection portion, and the projection of the P-type metal connection portion in the vertical direction avoids the silver reflective layer and the ITO transparent conductive layer; S26, forming an insulating protective layer along the surfaces of the silver mirror protective layer and the insulating passivation layer; S27, etching the insulating protection layer and the insulating passivation layer to form a plurality of second channels, wherein any second channel correspondingly exposes an N-GaN layer at the bottom of the first channel; The eutectic bonding comprises: S31, forming a first bonding layer on the insulating protection layer, wherein the first bonding layer fills the second channel and the first channel; S32, forming a second bonding layer on the supporting substrate; S33, performing a bonding process on the first bonding layer and the second bonding layer to obtain a bonded wafer; The substrate stripping comprises: S41, peeling off the growth substrate of the bonded wafer by laser to obtain the pre-processed structure; The second round of photolithography processing includes: S51, etching the exposed N-GaN layer to form a plurality of N-hole protection structures distributed at intervals, wherein the N-hole protection structures correspond to the first holes one by one; The N-hole protection structure protrudes in a direction away from the support substrate, and a projection of the first hole on the N-GaN layer falls within a coverage range of the N-hole protection structure; S52, roughening the surface of the N-GaN layer forming the N hole protection structure by using an alkaline solution; S53, etching to form a groove in a preset chip structure edge region, wherein the groove extends from the roughened N-GaN layer surface to the surface of the insulating passivation layer; The inner side of the groove is a chip main body structure, and the outer side of the groove is a retaining wall structure; The groove includes a first groove and a second groove, the width of the second groove is greater than the width of the first groove, and the projection of the second groove in the vertical direction overlaps with the P-type metal connecting portion; S54, etching the insulating passivation layer at the bottom of the second groove to form a third channel, wherein the third channel exposes the P-type metal connecting portion; S55, forming a P-type pad metal layer in the second groove and the third channel, with a gap between the P-type pad metal layer and the inner wall of the second groove; S56, grinding and thinning a side of the support substrate away from the P-type pad metal layer; S57, forming an N-type pad metal layer on one side of the support substrate after grinding and thinning, to obtain a finished wafer; The chip segmentation comprises: S61, cutting the finished wafer by laser to obtain a plurality of vertical structure LED chip particles.

3. The method for manufacturing a vertical structure LED chip according to claim 2, characterized in that: The growth substrate is a sapphire substrate; The depth of the first channel ranges from 0.7 to 1.3 μm; The thickness of the ITO transparent conductive layer is The insulating passivation layer is composed of a SiO2 single layer, a SiN x Single layer or SiO2 / SiN x The composite film layer is composed of the insulating passivation layer, and the thickness range is The silver reflective layer is composed of a silver bottom layer and a reflective surface layer, and the thickness of the silver bottom layer is in the range of The thickness of the reflective surface layer is in the range of The material of the silver mirror protective layer includes one or more of Cr, Au, Pt, Ni, and Ti. The thickness of the silver mirror protective layer is The insulating protective layer is composed of a single layer of SiO2, SiN x Single layer or SiO2 / SiN x The thickness of the insulating protective layer is in the range of The first bonding layer is composed of a first Cr bottom layer and a first bonding surface layer, and the thickness of the first Cr bottom layer is in the range of The total thickness of the first bonding layer is in the range of The support substrate is a silicon-based substrate, the resistivity of the silicon-based substrate is lower than 0.005Ω.cm, and the thickness of the silicon-based substrate is in the range of 500 to 1000μm; The second bonding layer is composed of a second Cr bottom layer and a second bonding surface layer, and the thickness of the second Cr bottom layer is in the range of The total thickness of the second bonding layer is in the range of The protrusion height of the N-hole protection structure ranges from 0.7 to 1.3 μm; Grinding and thinning the support substrate to 150-200 μm; The N-type pad metal layer includes a first pad bottom layer and a first pad surface layer, the material of the first pad bottom layer is Cr or Ti, and the thickness of the first pad bottom layer is in the range of The material of the first pad surface layer is Au, and the thickness range of the first pad surface layer is 4. The method for manufacturing a vertical structure LED chip according to claim 2, wherein: Step S22 also includes: The ITO transparent conductive layer is annealed in a vacuum rapid annealing furnace, the temperature range of the annealing is 540-560° C., and the duration range of the annealing is 8-12 minutes.

5. The method for manufacturing a vertical structure LED chip according to claim 2, wherein: Step S23 includes: First, an insulating passivation layer is deposited along the surface of the ITO transparent conductive layer and the first hole, and then a part of the insulating passivation layer on the ITO transparent conductive layer is removed by etching to form a reflective window.

6. The method for manufacturing a vertical structure LED chip according to claim 5, characterized in that: Step S24 includes: A silver reflective layer is deposited in the reflective window.

7. The method for manufacturing a vertical structure LED chip according to claim 3, characterized in that: The silicon-based substrate is cleaned in sequence with isopropyl alcohol, acetone, SPM solution and BOE solution for 5 to 10 minutes before use.

8. The method for manufacturing a vertical structure LED chip according to claim 2, wherein: In step S33, the bonding pressure of the bonding process is controlled at 6000-8000 kg / cm 2 The bonding temperature of the bonding process is controlled at 250-270° C., and the bonding time of the bonding process is controlled at 30-60 min.

9. The method for manufacturing a vertical structure LED chip according to claim 2, wherein: In step S52, the alkaline solution is a KOH solution, the duration of the roughening treatment is controlled to be 5 to 8 minutes, and the temperature of the roughening treatment is controlled to be 50 to 60°C.

10. A vertical structure LED chip, characterized in that: The vertical structure LED chip is manufactured by the manufacturing method of the vertical structure LED chip according to any one of claims 1 to 9.

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