Method for testing synchronization domain during fixed test

Abstract

The disclosure relates to a method for testing a synchronization domain during a fixed test. A test circuit includes a PLL frequency divider that outputs first and third clock signals as PLL clock signals during a capture phase of a functional mode and a transition and fixed mode, and outputs a second clock signal as an ATE clock signal based on an external clock signal during a shift phase of the transition and fixed mode. The OCC passes the clock signals through sub-paths within a first path within the first and second clock selection circuits in a functional mode, a transition capture mode, and a fixed capture mode so that the first and third clock signals are transmitted through less than the entire first path, the sub-paths being the first and second functional clock paths. In a shift phase of the transition and fixed mode, the OCC passes a second clock signal through a sub-path within a second path within the first and second clock selection circuits during the shift phase, so that the second clock signal is transmitted through less than the entire second path, and passing a second clock signal through the first and second functional clock paths during the shift phase.

Description

Technical Field

[0001] The present disclosure relates to the field of design for testability (DFT) IC chips, and in particular to a DFT IC chip incorporating techniques for providing equal clock paths during both high-speed acquisition and fixed acquisition. Background Art

[0002] Scan testing is a hardware-level technique used to evaluate the functionality of an integrated circuit (IC). Figure 1 The IC 10 illustrated in FIG. 1 includes z scan chains 22. These scan chains 22 are sequences of flip-flops with reconfigurable connections that play standard roles within the IC 10, such as maintaining state information. In a test mode, the IC 10 reconfigures these flip-flops to form the scan chains 22, thereby enabling direct manipulation and monitoring of the state of the flip-flops.

[0003] The process of scan shifting involves shifting decompressed data from scan decompressor 21 into scan chain 22. Scan compressor 23 compresses the output from the scan chain, allowing a snapshot of the internal state of IC 10 to be captured and examined. This process is particularly useful in identifying manufacturing defects or design errors.

[0004] The two test strategies applied in this case are fixed testing and transition testing. Fixed testing is designed to identify faults where a circuit node is permanently "stuck" at a logic 0 or 1 due to a manufacturing defect. This test phase is called fixed capture, which uses a specific clock signal generated from the clock bits CKBITS and a scan enable signal sequence to drive the IC 10 into a specific state for testing.

[0005] In contrast, transition testing is used to detect faults that occur when a circuit transitions from one state to another. This testing phase is called high-speed capture, which involves a designed sequence of clock signals and scan enable signals to force transitions between different states and verify their correct operation.

[0006] The test clock TSTCLK synchronizes the scan chain 22 with the core logic of the IC 10 during testing. The test clock TSTCLK is generated by an on-chip clock controller (OCC) 11 based on the automatic test equipment (ATE) clock ATECLK and the phase-locked loop clock PLLCLK. Based on the clock bits CKBITS received from the clock chain 13, the logic components of the OCC 11 are dynamically reconfigured to generate test clock TSTCLK patterns for both the fixed test phase and the transition test phase. In response to the m clock chain input bits OCC[1], ..., OCC[m] received from the m pins, the changes in these clock bits CKBITS facilitate the generation of the required test clock signal patterns. This dynamic reconfiguration allows the OCC 11 to generate the desired test clock signal TSTCLK pattern, thereby controlling the operation of the scan chain 22 and the core logic of the chip during various test phases.

[0007] Figure 2 The diagram shows details of an example of a test circuit 1 used in an IC designed for testing, comprising an OCC 11 for an asynchronous clock domain, ie PLLCLKA and PLLCLKB are asynchronous, as are the outputs TSTCLKA and TSTCLKB of the test circuit.

[0008] Figure 3 The details of an example of a test circuit 1' used in an IC designed for testing are illustrated, which includes an OCC 11'. In this example, the output clock CLK of the PLL 5 is passed to a divider block 82, which includes multiple divider circuits (e.g., divide by 2, divide by 4, divide by 8, divide by 16) that provide divided versions of the passed PLL clock. During high-speed capture (transition testing), the phase-locked loop (PLL) clock CLK generated by the PLL 5 and its divided output are routed to the OCC 11 through exactly the same path as PLLCLK[1] and PLLCLK[2], arriving at the clock trees 41, 42 at essentially the same time due to path balancing. This ensures that the IC operates at normal speed, thereby capturing any faults that occur during state transitions.

[0009] However, during fixed capture (fixed test), a slower ATE clock ATECLK is used. It is worth noting that the path of the ATE clock ATECLK to the clock selection circuit 34 is shorter than its path to the clock selection circuit 32. Therefore, each pulse of the ATE clock ATECLK may reach the clock tree 42 before reaching the clock tree 41, thereby causing timing imbalance, which may lead to inaccurate detection of fixed faults.

[0010] This imbalance requires further development of the OCC or associated logic to ensure accurate and reliable timing during both high speed and fixed capture, thereby optimizing the detection of potential faults during both transition test and fixed test phases. Summary of the invention

[0011] Disclosed herein is a test circuit in an integrated circuit (IC) designed for testing, the test circuit comprising a phase-locked loop circuit, the phase-locked loop circuit being configured to: output a first clock signal, wherein the phase-locked loop circuit generates the first clock signal as a first PLL clock signal during a functional mode and during a capture phase of a transition mode, and wherein the phase-locked loop circuit outputs the first clock signal as a first ATE clock signal (ATECLK_T_SC) based on an external clock signal during a capture phase of a fixed mode. The phase-locked loop circuit is also configured to: during a shift phase of a transition mode and a fixed mode, output a second clock signal as a second ATE clock signal (ATECLK) based on the external clock signal.

[0012] An on-chip clock controller (OCC) is configured to receive the first clock signal and the second clock signal and to pass the first clock signal and the second clock signal therethrough. A first clock tree is configured to receive the first clock signal and the second clock signal passed by the OCC.

[0013] The OCC is configured to pass a first clock signal therethrough by: in a functional mode, a transition capture mode, and a fixed capture mode, passing the first clock signal through a subpath within a first path within a first clock selection circuit in the OCC such that the first clock signal passes through less than the entire first path within the first clock selection circuit, the subpath within the first path within the first clock selection circuit being the first functional clock path. The OCC is configured to pass a second clock signal therethrough by: in a transition scan shift mode and a fixed scan shift mode, during a shift phase of the transition mode and the fixed mode, passing the second clock signal through a subpath within a second path within the first clock selection circuit in the OCC such that the second clock signal passes through less than the entire second path within the first clock selection circuit, and during a shift phase of the transition mode and the fixed mode, passing the second clock signal through a subpath within the first clock selection circuit, the subpath within the first clock selection circuit being the first shift clock path.

[0014] The OCC is also configured to pass the second clock signal therethrough in a transition mode by passing the second clock signal through an entire second path within a first clock selection circuit in the OCC during a shift phase of the transition mode, and passing the first clock signal through an entire first path within a first clock selection circuit in the OCC during a capture phase of the transition mode.

[0015] The phase-locked loop circuit can output the first clock signal to the divider to generate a third clock signal as a third PLL clock signal during the functional mode and during the capture phase of the transition mode, and wherein during the capture phase of the fixed mode, when the third clock signal is output as the first ATE clock signal based on the external clock signal, the divider is bypassed. The OCC can also be configured to receive the third clock signal and pass the third clock signal therethrough. The second clock tree can be configured to receive the third clock signal passed by the OCC.

[0016] The OCC can be configured to pass a third clock signal therethrough in the following manner: in a functional mode, a transition capture mode, and a fixed capture mode, the third clock signal is passed through a subpath within a first path within a second clock selection circuit in the OCC such that the third clock signal is passed through less than the entire first path within the second clock selection circuit, the subpath within the first path within the second clock selection circuit being a second functional clock path.

[0017] The OCC can be configured to pass the second clock signal therethrough in the following manner: in a transition scan shift mode and a fixed scan shift mode, during the shift phase of the transition and fixed modes, the second clock signal is passed through a sub-path within a second path within a second clock selection circuit in the OCC, so that the second clock signal is passed through less than the entire second path within the second clock selection circuit, and during the shift phase of the transition mode and the fixed mode, the second clock signal is passed through a sub-path within the second clock selection circuit, the sub-path within the second clock selection circuit being a second shift clock path.

[0018] The phase-locked loop circuit and the divider can also generate the first clock signal and the third clock signal as the first PLL clock signal and the second PLL clock signal during the capture phase of the transition mode, and output the first clock signal and the third clock signal as the first ATE clock signal based on the external clock signal during the capture phase of the fixed mode.

[0019] The OCC can also be configured to pass the first clock signal, the second clock signal, and the third clock signal through it in the transition mode in the following manner: during the shift phase of the transition mode, the second clock signal is passed through the entire second path within the first clock selection circuit in the OCC, and during the capture phase of the transition mode, the first clock signal is passed through the entire first path within the first clock selection circuit in the OCC; and during the shift phase of the transition mode, the second clock signal is passed through the entire second path within the second clock selection circuit in the OCC, and during the capture phase of the transition mode, the third clock signal is passed through the entire first path within the second clock selection circuit in the OCC.

[0020] The first clock selection circuit may include: a first AND gate having a non-inverting input receiving a scan enable signal and an inverting input receiving an intermediate signal; a first flip-flop having a data input receiving an output from the first AND gate and a clock input receiving a second ATE clock signal; a second AND gate having a first non-inverting input receiving a scan enable signal and a second non-inverting input receiving an output from the first flip-flop; a first OR gate having a first non-inverting input receiving an output from the second AND gate and a second non-inverting input receiving a bypass signal; a third AND gate having a first non-inverting input receiving an output from the first OR gate and a second non-inverting input receiving a MUX output signal; a first latch having a data input receiving an output from the third AND gate and a clock input receiving an external clock signal; a fourth AND gate having a first non-inverting input receiving an output from the first latch and a second non-inverting input receiving an external clock signal; a fifth AND gate having a first inverting input receiving an output from the first flip-flop, a second inverting input receiving the scan enable signal, and a non-inverting input receiving a pipeline OR tree signal; a second flip-flop having an output from the fifth AND gate and a second non-inverting input receiving an output from the first latch; a data input for receiving the first PLL clock signal and a clock input for receiving the first PLL clock signal; a sixth AND gate having a non-inverting input for receiving the output from the second flip-flop and an inverting input for receiving the bypass signal; a second OR gate having a non-inverting input for receiving the output from the sixth AND gate and an inverting input for receiving the first MUX output signal; a second latch having a data input for receiving the output from the second OR gate and a clock input for receiving the first PLL clock signal; a seventh AND gate having a first non-inverting input for receiving the output from the second latch and a second non-inverting input for receiving the first PLL clock signal; an ND gate having a first non-inverting input receiving the first MUX output signal and a second non-inverting input receiving the bypass signal; an eighth AND gate having a first non-inverting input receiving the output from the seventh AND gate and a second non-inverting input receiving the output from the NAND gate; and a third OR gate having a first non-inverting input receiving the output from the fourth AND gate and a second non-inverting input receiving the output from the eighth AND gate, wherein the output of the third OR gate is provided to the first clock tree as a first clock signal during capture and a second clock signal during scan shifting transmitted by the OCC. The multiplexer may have a first input receiving a scan enable signal, and a second input, and the multiplexer generates a first MUX output signal.

[0021] The multiplexer may pass the scan enable signal during fixed mode, but in addition pass the test controller bit during transition ATPG, and pass the LBIST mode control signal through during transition LBIST as a test mode signal at the output of the multiplexer.

[0022] The scan enable signal may be asserted during the shift phase of the transition mode and during the shift phase of the fixed mode, and de-asserted during the capture phase of the transition mode and the capture phase of the fixed mode.

[0023] The bypass signal may be asserted during fixed mode and de-asserted during transition mode and functional mode. The pipeline OR tree signal may be asserted at some times during the capture phase of transition mode and de-asserted during other modes. The test mode signal at the output of the multiplexer may be asserted during transition mode and during the shift phase of fixed mode, but de-asserted during the capture phase of fixed mode and functional mode.

[0024] The second clock selection circuit may include: a first AND gate having a non-inverting input receiving a scan enable signal and an inverting input receiving a second intermediate signal; a first flip-flop having a data input receiving an output from the first AND gate and a clock input receiving a second ATE clock signal; a second AND gate having a first non-inverting input receiving a scan enable signal and a second non-inverting input receiving an output from the first flip-flop; a first OR gate having a first non-inverting input receiving an output from the second AND gate and a second non-inverting input receiving a bypass signal; a third AND gate having a first non-inverting input receiving an output from the first OR gate and a second non-inverting input receiving a first MUX output signal; a first latch having a data input receiving an output from the third AND gate and a clock input receiving an external clock signal; a fourth AND gate having a first non-inverting input receiving an output from the first latch and a second non-inverting input receiving an external clock signal; a fifth AND gate having a first inverting input receiving an output from the first flip-flop, a second inverting input receiving a scan enable signal, and a non-inverting input receiving a pipeline OR tree signal; a second flip-flop having a first non-inverting input receiving an output from the fifth AND gate and a second non-inverting input receiving an output from the first flip-flop; a data input for receiving the output from the second flip-flop and a clock input for receiving the second PLL clock signal; a sixth AND gate having a non-inverting input for receiving the output from the second flip-flop and an inverting input for receiving the bypass signal; a second OR gate having a non-inverting input for receiving the output from the sixth AND gate and an inverting input for receiving the first MUX output signal; a second latch having a data input for receiving the output from the second OR gate and a clock input for receiving the second PLL clock signal; a seventh AND gate having a first non-inverting input for receiving the output from the second latch and a second non-inverting input for receiving the second PLL clock signal; N an AND gate having a first non-inverting input receiving the first MUX output signal and a second non-inverting input receiving the bypass signal; an eighth AND gate having a first non-inverting input receiving the output from the seventh AND gate and a second non-inverting input receiving the output from the NAND gate; and a third OR gate having a first non-inverting input receiving the output from the fourth AND gate and a second non-inverting input receiving the output from the eighth AND gate, wherein the output of the third OR gate is provided to the second clock tree as a third clock signal during capture and a second clock signal during scan shift passed by the OCC.

[0025] A method for maintaining a balanced clock signal path when a test selection mode signal is at a logic low across different operating modes in an integrated circuit is also disclosed herein. The method includes outputting a first clock signal and a third clock signal from a phase-locked loop (PLL) circuit and a frequency divider circuit, respectively. The method also includes routing the first clock signal and the third clock signal through an on-chip clock controller (OCC) in a functional mode, a transition capture mode, and a fixed capture mode by: passing the first clock signal through a subpath within a first path within a first clock selection circuit, so that the first clock signal is passed through less than the entire first path within the first clock selection circuit, and the subpath within the first path within the first clock selection circuit is a first functional clock path; and passing the third clock signal through a subpath within the first path within a second clock selection circuit, so that the third clock signal is passed through less than the entire first path within the second clock selection circuit, and the subpath within the first path within the second clock selection circuit is a second functional clock path. In a transition shift mode and a fixed shift mode, the method includes routing a second clock signal through the OCC in the following manner: during the shift phase of the transition and fixed modes, passing the second clock signal through a subpath within a second path within the first clock selection circuit so that the second clock signal passes through less than the entire second path within the first clock selection circuit, and during the shift phase of the transition and fixed modes, passing the second clock signal through the first functional clock path; and during the shift phase of the transition and fixed modes, passing the second clock signal through a subpath within the second path within the second clock selection circuit so that the second clock signal passes through less than the entire second path within the second clock selection circuit, and during the shift phase of the transition and fixed modes, passing the second clock signal through the second functional clock path. The method also includes assigning the first clock signal and the second clock signal to the first clock tree after the first clock signal and the second clock signal have been routed through the OCC; and assigning the third clock signal and the second clock signal to the second clock tree after the third clock signal and the second clock signal have been routed through the OCC.

[0026] The first clock signal may be a PLL clock signal generated by the PLL circuit, or an automatic test equipment (ATE) clock signal (ATE_T_SC) passed through the PLL circuit when the bypass signal is set to logic 1.

[0027] The method may also include: generating a first clock signal as a first PLL clock signal by the PLL circuit during the functional mode and during the capture phase of the transition and fixed modes; and generating a second clock signal as a second ATE clock signal (ATECLK) based on an external clock signal during the shift phase of the transition and fixed modes; and generating a third clock signal as a second PLL clock signal by the divider circuit during the functional mode and during the capture phase of the transition and fixed modes; and generating a second clock signal as a second ATE clock signal based on the external clock signal during the shift phase of the transition and fixed modes.

[0028] The method may also include passing the second clock signal through the OCC in the transition mode in the following manner: during the shift phase of the transition mode, the second clock signal is passed through the entire second path within the first clock selection circuit, and during the capture phase of the transition mode, the first clock signal is passed through the entire first path within the first clock selection circuit; and passing the second clock signal through the OCC in the transition mode in the following manner: during the shift phase of the transition mode, the second clock signal is passed through the entire second path within the second clock selection circuit, and during the capture phase of the transition mode, the third clock signal is passed through the entire first path within the second clock selection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram of a conventional integrated circuit (IC) designed for testing;

[0030] Figure 2 is a block diagram of a conventional test circuit used in an IC designed for testing, the test circuit including an on-chip clock controller (OCC) for an asynchronous clock domain;

[0031] Figure 3 is a block diagram of a conventional test circuit used in an IC designed for testing, the test circuit including an on-chip clock controller (OCC) for synchronizing clock domains;

[0032] Figure 4 A test circuit for use in an IC designed for testing, the test circuit comprising an on-chip clock controller (OCC) for synchronizing clock domains; and

[0033] Figure 5 is used for Figure 4 Block diagram of the clock selection block in the OCC. DETAILED DESCRIPTION

[0034] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the disclosure. It is not intended to limit the disclosure to the embodiments shown, but rather to give it the widest scope consistent with the principles and features disclosed or suggested herein.

[0035] Reference now Figure 4 A modified test circuit 1' is described, which includes a modified OCC 11'. Figure 3 , in this example, the output clock CLK of PLL 5 is passed to a divider block 82, which includes a plurality of divider circuits that provide divided versions of the passed PLL clock. During both the transition scan shift and the fixed scan shift, the clock selection blocks 32 and 34 will continue to be clocked from the ATE clock ATECLK, which arrives at these blocks directly from the automatic test equipment (ATE). When the scan flip-flop 84 is clocked by the clock TSTCLKB, a locking latch 85 exists between the Q output of the scan flip-flop 83 and the SI input of the scan flip-flop 84, which is connected after the scan flip-flop 83 clocked by TSTCLKA in the same scan chain. This is used to eliminate timing imbalance inaccuracies in the scan shift path. With Figure 3 In comparison, Figure 4 In this embodiment, during both transition capture and fixed capture, clock selection blocks 32 and 34 are always clocked by PLL 5, either by the PLL clock generated as CLK when the bypass signal BYPASS is at logic 0, or by the ATE clock ATECLK_T_SC passed to the clock input CLKIN of PLL 5 when the bypass signal BYPASS is at logic 1.

[0036] In fact, the purpose of the modified OCC 11 'is to keep the scan shift path from ATECLK to the clock trees 41 and 42 balanced, and to keep the scan capture path from the PLL clock itself or from ATE_CLK_T_SC (routed through PLL 5) balanced. In each capture mode, the clock signal flows through PLL 5. When the PLL bypass signal BYPASS signal is set to logic 1, it can be the PLL clock PLLCLK itself or the ATE clock ATECLK_T_SC routed through the PLL. Then, the clock signal is passed from PLL5 through OCC 11 '(specifically, through fast pulse controllers 31 and 33, and clock selection circuits 32 and 34) to clock trees 41, 42. By maintaining the same clock path that is balanced in each capture mode, the need for additional circuit devices for managing potential timing problems that may occur when the clock paths through controllers 31 and 33, and clock selection circuits 32 and 34 become unbalanced according to the operating mode is eliminated. This saves space without reducing reliability.

[0037] Reference now Figure 5 Description can be used Figure 4 The clock selection circuit 32 or 34 in the OCC 11' is used to provide a balanced clock path regardless of whether the operation is in high-speed capture or fixed capture. However, before doing so, note that Figure 4 The presence of multiplexer 73 in Figure 3 Multiplexer 73 has a first input connected to test select signal TEST_SE, a second input driven from a test controller bit in ATPG and a LBIST mode control signal (collectively referred to as TCBA_LM) from a LBIST controller in LBIST mode, and an output test mode signal TESTMODE into OCC 11' and clock selection circuits 32 and 34. Multiplexer 73 has a select input connected to receive a fixed mode signal STUCK_AT_MODE driven from another test controller bit in ATPG and another LBIST mode control signal from a LBIST controller in LBIST mode.

[0038] The clock selection circuit 32 or 34 includes a first AND gate 51 having an input receiving a test selection signal TEST_SE, an inverting input receiving the output of the flip-flop 62 (e.g., an inverter connected in series with the input), and an output. The flip-flop 52 has a data input connected to receive the output of the AND gate 51, a clock input connected to receive the ATE clock signal ATECLK, an inverting reset input configured to receive the inversion of the reset signal RESET (e.g., an inverter connected in series with the reset input), and an output. The AND gate 53 has a first input connected to receive the test selection signal TEST_SE, a second input connected to receive the output of the flip-flop 52, and an output. The OR gate 54 has a first input connected to receive the output of the AND gate 53, a second input connected to receive the bypass signal BYPASS, and an output. The AND gate 55 has a first input connected to receive the output of the OR gate 54, a second input connected to receive the output of the multiplexer 73, and an output. Latch 56 has a data input connected to receive the output of AND gate 55, an inverted clock input connected to receive the ATE clock ATECLK (e.g., an inverter in series with the clock input), and an output. AND gate 57 has a first input connected to receive the output of latch 56, a second input connected to receive the ATE clock ATECLK, and an output.

[0039] The clock selection circuit 32 or 34 also includes an AND gate 61 having a first inverting input connected to receive the output of the flip-flop 52, a second inverting input connected to receive the test selection signal TEST_SE, an input connected to receive a pipeline OR tree (pipeline_or_tree) signal PIPELINE_OR_TREE, and an output. Note that PIPELINE_OR_TREE is output by the fast pulse controller 31 or 33 based on the clock bit CKBITS, thereby ultimately providing a high-speed pulse of the required number of CLKs (output by the OR gate 58, as described below).

[0040] Flip-flop 62 has a data input connected to receive the output of AND gate 61, a clock input connected to receive the PLL clock signal PLLCLK (CLK output generated by PLL 5 or DIV2 output from divider block 82), an inverting reset input connected to receive the inverted version of reset signal RESET (e.g., an inverter connected in series with the reset input), and an output. AND gate 63 has an input connected to receive the output of flip-flop 62, an inverting input connected to receive bypass signal BYPASS (e.g., an inverter connected in series with the input), and an output. OR gate 64 has an input connected to receive the output of AND gate 63, an inverting input connected to receive the output of multiplexer 73 (e.g., an inverter connected in series with the input), and an output. Latch 65 has a data input connected to receive the output of OR gate 64, an inverting clock input connected to receive the PLL clock signal PLLCLK (e.g., an inverter connected in series with the clock input), and an output. AND gate 66 has a first input connected to receive the output of latch 65, a second input connected to receive the PLL clock signal PLLCLK, and an output. AND gate 67 has a first input connected to receive the output of AND gate 66, a second input connected to receive the output of NAND gate 72, and an output. OR gate 58 has a first input connected to receive the output of AND gate 57, a second input connected to receive the output of AND gate 67, and an output to generate a clock signal CLK, which is ultimately passed to clock trees 41 and 42 to generate test clocks TSTCLKA, TSTCLKB.

[0041] NAND gate 72 has a first input connected to receive the output of multiplexer 73, a second input connected to receive bypass signal BYPASS, and an output connected to the second output of AND gate 67. Reset signal RESET is inverted by inverter 71 and provided to the inverting reset inputs of flip-flops 62 and 52.

[0042] The output of multiplexer 73 is connected to a first input of NAND gate 72 , an inverting input of OR gate 64 , and a second input of AND gate 55 .

[0043] A. Functional Mode Operation

[0044] Consider first the operation of the circuit in functional mode rather than test mode. In this mode, the STUCK_AT_MODE signal is logic 0 (TCBA_LM_S = '0'), indicating that the multiplexer 73 delivers TCBA_LM to the test mode signal TEST_MODE as its output. When TEST_MODE is set to logic 0 in functional mode (such as TCBA_LM = '0'), the multiplexer 73 therefore passes logic 0. This triggers both NAND gate 72 and OR gate 64 to output logic 1. When PLLCLK is logic 0, the Q output of latch 65 will be logic 1, and will remain logic 1 thereafter. This enables the output of AND gate 66 to align with the PLL clock PLLCLK. It is worth noting that at this stage, when TEST_MODE is at logic 0, AND gate 55 delivers logic 0, thereby effectively preventing any logic 1 from passing through this part of the circuit. Therefore, in functional mode, the output CLK of OR gate 58 is exclusively aligned with the PLL clock PLLCLK.

[0045] B. Mode change operation, shift

[0046] Now, the transition mode will be discussed. Here, the test mode signal TEST_MODE transitions to logic 1 (eg, TCBA_LM='1') during the shift period, and BYPASS is at logic 0. Assuming that the STUCK_AT_MODE signal remains at logic 0 (eg, TCBA_LM_S='0') in this mode, multiplexer 73 continues to output TCBA_LM to the test mode signal TEST_MODE.

[0047] When the scan enable TEST_SE switches to logic 1 during the shift, since TEST_SE is connected to the inverting input of AND gate 61 (e.g., an inverter in series with the input), the output of AND gate 61 becomes logic 0. This then sets the output of flip-flop 62 to logic 0, thereby enabling AND gate 51 to receive two logic 1s at its input (TEST_SE at its input, and logic 0 from flip-flop 62 at its inverting input), and thus output logic 1 to flip-flop 52. When the next ATE clock signal ATECLK pulse arrives, flip-flop 52 outputs this logic 1, thereby causing the output of AND gate 53 to transition to logic 1. The output of OR gate 54 is therefore at logic 1. Therefore, in the case where multiplexer 73 outputs the test mode signal TEST_MODE, AND gate 55 simulates the output of OR gate 54. When ATECLK is logic 0, the output of latch 56 follows the output of AND gate 55, and will thereafter hold this value, thereby enabling the output of AND gate 57 to be aligned with the ATE clock ATECLK.

[0048] It is noted here that since TEST_SE is at logic 1, the output of flip-flop 62 remains at logic 0, causing the output of AND gate 63 to transition to logic 0. In addition, when TEST_MODE is at logic 1 at the inverting input of OR gate 64, the output of OR gate 64 remains at logic 0. This state causes the output of latch 65 to remain at logic 0, causing AND gates 66 and 67 to maintain their outputs at logic 0. Therefore, in transition mode, during the scan shift, the output CLK of OR gate 58 is exclusively aligned with the ATE clock signal ATECLK. When scan flip-flop 84 is clocked by TSTCLKB, the resulting test clocks TSTCLKA, TSTCLKB generated can be passed as clock inputs to scan flip-flops 83 and 84, wherein the latch latch 85 is connected between the Q output of scan flip-flop 83 and the SI input of scan flip-flop 84, which is connected after the scan flip-flop 83 clocked by TSTCLKA in the same scan chain.

[0049] C. Transition mode operation, capture

[0050] During capture, the test enable signal TEST_SE switches to logic 0. This deactivation of TEST_SE causes the AND gate 61 to output logic 1 when the pipeline_or_tree signal PIPELINE_OR_TREE is active.

[0051] The logic 1 output by AND gate 61 is then passed to flip-flop 62 , and the output of flip-flop 62 switches to logic 1 when the next PLL clock signal PLLCLK pulse arrives.

[0052] At the same time, TEST_SE is logic 0 so that the output of AND gate 51 becomes logic 0. Therefore, when the next ATE clock signal ATECLK pulse arrives, the output of flip-flop 52 remains at logic 0. This causes AND gate 53, and thus OR gate 54 and AND gate 55, to maintain their outputs at logic 0. Therefore, latch 56 and AND gate 57 also output logic 0.

[0053] On the other hand, since the output of flip-flop 62 is now a logic 1 and BYPASS is a logic 0, the output of AND gate 63 becomes a logic 1. Therefore, the output of OR gate 64 follows the output of AND gate 63. When PLLCLK is a logic 0, the Q output of the latch becomes a logic 1 and will remain at a logic 1 thereafter until PIPELINE_OR_TREE becomes a logic 0, where TEST_SE is a logic 0. This causes AND gate 66 to provide the required number of PLLCLK pulses. Assuming that NAND gate 72 outputs a logic 1, AND gate 67 also follows AND gate 66 (limiting the number of PLLCLK pulses based on the PIPELINE_OR_TREE value).

[0054] Therefore, during capture mode, the output CLK of OR gate 58 is exclusively aligned with the PLL clock signal PLLCLK within a limited time based on the value of PIPELINE_OR_TRE because it combines the output of AND gate 57 (now at logic 0) and the output of AND gate 67 (following the PLL clock signal, controlled by the PIPELINE_OR_TRE value).

[0055] D. Fixed mode operation, shift

[0056] The fixed test is now described. In this mode, the divider of the divider block 82 can be bypassed so that the clock delivered to the divider block 82 by the PLL 5 is output at each output of the divider block 82 without performing frequency division. During the fixed test, the STUCK_AT_MODE signal is asserted, causing the multiplexer 73 to pass the scan enable signal TEST_SE as its TESTMODE output.

[0057] During the shift phase of the fixed test, TEST_SE is at logic 1 and the bypass signal BYPASS is also at logic 1.

[0058] Since NAND gate 72 has one input at logic 1 from multiplexer 73 and the other input at logic 1 from bypass signal BYPASS, the output of NAND gate 72 becomes logic 0. This sets the input condition of AND gate 67 so that it blocks, thereby outputting logic 0.

[0059] At the same time, since BYPASS is connected to the second input of OR gate 54, BYPASS at logic 1 causes OR gate 54 to output logic 1. TEST_SE is also logic 1 during the shift phase, causing AND gate 55 to have two logic 1s at its inputs, thereby outputting logic 1. When the ATE clock signal ATECLK is logic 0, latch 56 outputs this logic 1 and will hold logic 1 thereafter, causing AND gate 57 to output logic 1 when ATECLK is also at logic 1 (aligned with ATE clock ATECLK).

[0060] Conversely, since BYPASS is a logic 1 and TEST_MODE output by multiplexer 73 is a logic 1, AND gate 67 remains at a logic 0, forcing the output of NAND gate 72 to a logic 0, which in turn forces the output of AND gate 67 to a logic 0.

[0061] Therefore, during the shift phase of the fixed test, since AND gate 57 outputs logic 1 and AND gate 67 outputs logic 0, the output CLK of OR gate 58 follows the ATE clock signal ATECLK. The resulting test clocks TSTCLKA, TSTCLKB generated can be passed as clock inputs to scan flip-flops 83 and 84, wherein when the scan flip-flop 84 is clocked by TSTCLKB, the locking latch 85 is connected between the Q output of the scan flip-flop 83 and the SI input of the scan flip-flop 84, and is connected after the scan flip-flop 83 clocked by TSTCLKA in the same scan chain.

[0062] E. Fixed mode operation, capture

[0063] During the capture phase of the fixed test, the test enable signal TEST_SE switches to logic 0. Therefore, NAND gate 72 outputs logic 1. However, in the case where TEST_SE is now at logic 0 and is passed to the inverting input of OR gate 64, the output of OR gate 64 switches to logic 1. This state causes the output of latch 65 to follow the PLL clock signal PLLCLK, and in turn, AND gate 66 also follows the PLL clock PLLCLK. Since AND gate 67 receives logic 1 at each input, it also outputs a signal aligned with the PLL clock PLLCLK. However, since TEST_SE is at logic 0 during capture, AND gate 55 blocks the signal, resulting in AND gate 57 outputting logic 0. Therefore, during the capture phase, the output CLK of OR gate 58 is exclusively aligned with the PLL clock signal PLLCLK. Since the divider block 82 is bypassed and the PLL 5 is bypassed, the ATE clock ATECLK_T_SC passed by the PLL 5 to the divider block 82 is output at each output of the divider block 82 without performing division and is available at PLLCLK and the OR gate 58 output CLK.

[0064] F. Benefits

[0065] By means of the above-described OCC 11' and associated circuit devices, the problems faced by the prior art are solved. The same clock path is utilized in all modes where TEST_SE is logic 0, whether the operation is in functional mode, transition capture test mode, or fixed capture test mode, thereby eliminating concerns about timing issues while saving area and complexity compared to prior art solutions that employ different solutions (such as modifying certain clock path lengths). In addition, since the pulses output by the clock selection circuits 32 and 34 are aligned, circuit devices such as a one-hot decoder are not required to correct for misaligned pulses, thereby saving area, complexity, and increasing pattern time.

[0066] Furthermore, since a functional path through PLL 5 is employed, wherein ATECLK_T_SC is passed through PLL 5 via being input to clock input CLKIN, controllability is maintained since the output is not limited to the frequency and duty cycle that can be generated by the PLL 5 circuitry. Furthermore, as previously described, the dividers of divider block 82 can be bypassed during fixed testing so that the flip-flops therein can be used as part of a scan chain.

[0067] Obviously, modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0068] Although the present disclosure has been described using a limited number of embodiments, those skilled in the art having benefit of the present disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein made in various ways.

Claims

1. A test circuit in an integrated circuit IC designed for testing, comprising: The phase-locked loop circuit is configured as: outputting a first clock signal, wherein the phase-locked loop circuit generates the first clock signal as a first PLL clock signal during a functional mode and during a capture phase of a transition mode, and wherein the phase-locked loop circuit outputs the first clock signal as a first ATE clock signal based on an external clock signal during a capture phase of a fixed mode; and outputting a second clock signal as a second ATE clock signal based on an external clock signal during the shift phases of the transition mode and the fixed mode; an on-chip clock controller OCC configured to receive the first clock signal and the second clock signal, and to transmit the first clock signal and the second clock signal through the OCC; as well as a first clock tree configured to receive the first clock signal and the second clock signal transmitted by the OCC; wherein the OCC is configured to pass the first clock signal through the OCC in the following manner: In the functional mode, transition capture mode, and fixed capture mode: passing the first clock signal through a subpath within a first path within a first clock selection circuit in the OCC such that the first clock signal passes through less than the entire first path within the first clock selection circuit, the subpath within the first path within the first clock selection circuit being a first functional clock path; and wherein the OCC is configured to pass the second clock signal through the OCC in the following manner: In transition scan shift mode and fixed scan shift mode: During the shift phase of the transition mode and the fixed mode, the second clock signal is passed through a sub-path within a second path within the first clock selection circuit in the OCC, so that the second clock signal is passed through less than the entire second path within the first clock selection circuit, and during the transition mode and the shift phase of the fixed mode, the second clock signal is passed through the sub-path within the first clock selection circuit, and the sub-path within the first clock selection circuit is a first shift clock path.

2. The test circuit of claim 1 , wherein the OCC is further configured to pass the second clock signal through the OCC in the transition mode by passing the second clock signal through an entire second path within the first clock selection circuit in the OCC during the shift phase of the transition mode, and passing the first clock signal through an entire first path within the first clock selection circuit in the OCC during the capture phase of the transition mode.

3. The test circuit according to claim 1, wherein the phase-locked loop circuit outputs the first clock signal to a frequency divider to generate a third clock signal as a third PLL clock signal during a functional mode and during a capture phase of a transition mode, and wherein during a capture phase of the fixed mode, when the third clock signal is output as a first ATE clock signal based on the external clock signal, the frequency divider is bypassed; wherein the OCC is further configured to receive the third clock signal and pass the third clock signal through the OCC; The test circuit further includes a second clock tree configured to receive the third clock signal delivered by the OCC; and wherein the OCC is configured to pass the third clock signal through the OCC in the following manner: in the functional mode, the transition capture mode, and the fixed capture mode, passing the third clock signal through a subpath within a first path within a second clock selection circuit in the OCC such that the third clock signal passes through less than the entire first path within the second clock selection circuit, the subpath within the first path within the second clock selection circuit being a second functional clock path; and wherein the OCC is configured to pass the second clock signal through the OCC in the following manner: In the transition scan shift mode and the fixed scan shift mode, during the shift phase of the transition and fixed modes, the second clock signal is passed through a sub-path within the second path within the second clock selection circuit in the OCC, so that the second clock signal is passed through less than the entire second path within the second clock selection circuit, and during the shift phase of the transition mode and the fixed mode, the second clock signal is passed through the sub-path within the second clock selection circuit, and the sub-path within the second clock selection circuit is a second shift clock path.

4. The test circuit of claim 3 , wherein the phase-locked loop circuit and the frequency divider further generate the first clock signal and the third clock signal as the first PLL clock signal and the second PLL clock signal during a capture phase of the transition mode, and output the first clock signal and the third clock signal as the first ATE clock signal based on the external clock signal during the capture phase of the fixed mode.

5. The test circuit of claim 4, wherein the OCC is further configured to pass the first clock signal, the second clock signal, and the third clock signal through the OCC in the following manner: In the transition mode: passing the second clock signal through an entire second path within the first clock selection circuit in the OCC during the shift phase of the transition mode, and passing the first clock signal through an entire first path within the first clock selection circuit in the OCC during the capture phase of the transition mode; and During the shift phase of the transition mode, the second clock signal is passed through an entire second path within the second clock selection circuit in the OCC, and during the capture phase of the transition mode, the third clock signal is passed through an entire first path within the second clock selection circuit in the OCC.

6. The test circuit according to claim 5, wherein the first clock selection circuit comprises: A first AND gate (51) having a non-inverting input receiving a scan enable signal and an inverting input receiving an intermediate signal (from 62); a first flip-flop (52) having a data input receiving the output from the first AND gate and a clock input receiving the second ATE clock signal; a second AND gate (53) having a first non-inverting input receiving the scan enable signal and a second non-inverting input receiving the output from the first flip-flop; a first OR gate (54) having a first non-inverting input receiving the output from the second AND gate and a second non-inverting input receiving a bypass signal; a third AND gate (55) having a first non-inverting input receiving the output from the first OR gate and a second non-inverting input receiving the MUX output signal (from 73); a first latch (56) having a data input receiving the output from the third AND gate and a clock input receiving the external clock signal; a fourth AND gate (57) having a first non-inverting input receiving the output from the first latch and a second non-inverting input receiving the external clock signal; a fifth AND gate (61) having a first inverting input receiving the output from the first flip-flop, a second inverting input receiving the scan enable signal, and a non-inverting input receiving a pipeline OR tree signal; a second flip-flop (62) having a data input receiving the output from the fifth AND gate and a clock input receiving the first PLL clock signal; a sixth AND gate (63) having a non-inverting input receiving the output from the second flip-flop and an inverting input receiving the bypass signal; a second OR gate (64) having a non-inverting input receiving the output from the sixth AND gate and an inverting input receiving the first MUX output signal; a second latch (65) having a data input receiving the output from the second OR gate and a clock input receiving the first PLL clock signal; a seventh AND gate (66) having a first non-inverting input receiving the output from the second latch and a second non-inverting input receiving the first PLL clock signal; A NAND gate (72) having a first non-inverting input receiving the first MUX output signal and a second non-inverting input receiving the bypass signal; an eighth AND gate (67) having a first non-inverting input receiving the output from the seventh AND gate and a second non-inverting input receiving the output from the NAND gate; a third OR gate (58) having a first non-inverting input receiving the output from the fourth AND gate and a second non-inverting input receiving the output from the eighth AND gate, wherein the output of the third OR gate is provided to the first clock tree as the first clock signal during capture and the second clock signal during scan shift delivered by the OCC; as well as A multiplexer has a first input receiving the scan enable signal and a second input, the multiplexer generating the first MUX output signal.

7. The test circuit according to claim 6, wherein the multiplexer passes the scan enable signal during the fixed mode, but in addition passes the test controller bit during transition ATPG and passes the LBIST mode control signal during transition LBIST as a test mode signal at the output of the multiplexer; wherein the scan enable signal is asserted during the shift phase of the transition mode and during the shift phase of the fixed mode, and is de-asserted during the capture phase of the transition mode and the capture phase of the fixed mode; wherein the bypass signal is asserted during the fixed mode and de-asserted during the transition mode and the functional mode; wherein said pipelined OR tree signal is asserted at some times during said capture phase of said transition mode and is de-asserted during other modes; and Wherein the test mode signal at the output of the multiplexer is asserted during the transition mode and during the shift phase of the fixed mode, but is de-asserted during the capture phase of the fixed mode and the functional mode.

8. The test circuit according to claim 7, wherein the second clock selection circuit comprises: a first AND gate having a non-inverting input for receiving the scan enable signal and an inverting input for receiving the second intermediate signal; a first flip-flop having a data input receiving the output from the first AND gate and a clock input receiving the second ATE clock signal; a second AND gate having a first non-inverting input receiving the scan enable signal and a second non-inverting input receiving an output from the first flip-flop; a first OR gate having a first non-inverting input receiving the output from the second AND gate and a second non-inverting input receiving the bypass signal; a third AND gate having a first non-inverting input receiving the output from the first OR gate and a second non-inverting input receiving the first MUX output signal; a first latch having a data input receiving the output from the third AND gate and a clock input receiving the external clock signal; a fourth AND gate having a first non-inverting input receiving the output from the first latch and a second non-inverting input receiving the external clock signal; a fifth AND gate having a first inverting input receiving the output from the first flip-flop, a second inverting input receiving the scan enable signal, and a non-inverting input receiving the pipeline OR tree signal; a second flip-flop having a data input receiving the output from the fifth AND gate and a clock input receiving the second PLL clock signal; a sixth AND gate having a non-inverting input receiving the output from the second flip-flop and an inverting input receiving the bypass signal; a second OR gate having a non-inverting input receiving the output from the sixth AND gate and an inverting input receiving the first MUX output signal; a second latch having a data input receiving the output from the second OR gate and a clock input receiving the second PLL clock signal; a seventh AND gate having a first non-inverting input receiving the output from the second latch and a second non-inverting input receiving the second PLL clock signal; a NAND gate having a first non-inverting input receiving the first MUX output signal and a second non-inverting input receiving the bypass signal; an eighth AND gate having a first non-inverting input receiving the output from the seventh AND gate and a second non-inverting input receiving the output from the NAND gate; as well as a third OR gate having a first non-inverting input receiving the output from the fourth AND gate and a second non-inverting input receiving the output from the eighth AND gate, wherein the output of the third OR gate is provided to the second clock tree as the third clock signal during capture and the second clock signal during scan shift signal delivered by the OCC.

9. A method for maintaining a balanced clock signal path when a test select mode signal is at a logic low across different operating modes in an integrated circuit, the method comprising: Outputting a first clock signal and a third clock signal from a phase-locked loop (PLL) circuit and a frequency divider circuit respectively; In the functional mode, the transition capture mode, and the fixed capture mode, the first clock signal and the third clock signal are routed through the on-chip clock controller OCC in the following manner: passing the first clock signal through a subpath within a first path within a first clock selection circuit such that the first clock signal passes through less than the entire first path within the first clock selection circuit, the subpath within the first path within the first clock selection circuit being a first functional clock path; as well as passing the third clock signal through a subpath within a first path within a second clock selection circuit such that the third clock signal passes through less than the entire first path within the second clock selection circuit, the subpath within the first path within the second clock selection circuit being a second functional clock path; and In the transition shift mode and the fixed shift mode, the second clock signal is routed through the OCC in the following manner: during a shift phase of a transition and fixed mode, passing the second clock signal through a subpath within the second path within the first clock selection circuit such that the second clock signal passes through less than the entire second path within the first clock selection circuit, and during a shift phase of the transition and fixed mode, passing the second clock signal through the first functional clock path; as well as during said shift phase of said transition and fixed mode, passing said second clock signal through a subpath within said second path within said second clock selection circuit such that said second clock signal passes through less than the entirety of said second path within said second clock selection circuit, and during said shift phase of said transition and fixed mode, passing said second clock signal through said second functional clock path; assigning the first clock signal and the second clock signal to a first clock tree after the first clock signal and the second clock signal have been routed through the OCC; as well as After the third clock signal and the second clock signal have been routed through the OCC, the third clock signal and the second clock signal are distributed to a second clock tree.

10. The method of claim 9, wherein the first clock signal is a PLL clock signal generated by the PLL circuit, or an automatic test equipment ATE clock signal (ATE_T_SC) passed through the PLL circuit when a bypass signal is set to logic 1.

11. The method according to claim 9, further comprising: generating the first clock signal as a first PLL clock signal by the PLL circuit during a functional mode and during a capture phase of a transition and a fixed mode; and generating the second clock signal as a second ATE clock signal (ATECLK) based on an external clock signal during a shift phase of the transition and fixed modes; as well as generating the third clock signal as a second PLL clock signal by the frequency divider circuit during the functional mode and during the capture phase of the transition and fixed modes; And during the shift phase of the transition and fixed mode, generating the second clock signal as a second ATE clock signal based on the external clock signal.

12. The method according to claim 11, further comprising: passing the second clock signal through the OCC in the transition mode by passing the second clock signal through an entire second path within the first clock selection circuit during the shift phase of the transition mode and passing the first clock signal through an entire first path within the first clock selection circuit during the capture phase of the transition mode; as well as The second clock signal is passed through the OCC in the transition mode by passing the second clock signal through an entire second path within the second clock selection circuit during the shift phase of the transition mode, and the third clock signal is passed through an entire first path within the second clock selection circuit during the capture phase of the transition mode.

13. A test circuit in an integrated circuit IC designed for testing, comprising: The phase-locked loop circuit is configured as: outputting the first clock signal as a first PLL clock signal during the functional mode and during a capture phase of the transition mode, and outputting the first clock signal as a first ATE clock signal during a capture phase of the fixed mode; and outputting a second clock signal as a second ATE clock signal based on an external clock signal during the shift phases of the transition mode and the fixed mode; An on-chip clock controller OCC, configured to receive the first clock signal and the second clock signal; wherein the OCC is configured to pass the first clock signal through the OCC in the following manner: In the functional mode, transition capture mode, and fixed capture mode: passing the first clock signal through a subpath within a first path within a first clock selection circuit in the OCC; and wherein the OCC is configured to pass the second clock signal through the OCC in the following manner: In transition scan shift mode and fixed scan shift mode: During the transition mode and the shift phase of the fixed mode, the second clock signal is passed through a sub-path within a second path within the first clock selection circuit in the OCC, and during the transition mode and the shift phase of the fixed mode, the second clock signal is passed through the sub-path within the first clock selection circuit.

14. The test circuit of claim 13 , wherein the OCC is further configured to pass the second clock signal through the OCC in the transition mode by passing the second clock signal through an entire second path within the first clock selection circuit in the OCC during the shift phase of the transition mode, and passing the first clock signal through an entire first path within the first clock selection circuit in the OCC during the capture phase of the transition mode.

15. The test circuit according to claim 13, wherein the phase-locked loop circuit outputs the first clock signal to a frequency divider to generate a third clock signal as a third PLL clock signal during a functional mode and during a capture phase of a transition mode, and wherein during a capture phase of the fixed mode, when the third clock signal is output as a first ATE clock signal based on the external clock signal, the frequency divider is bypassed; wherein the OCC is further configured to receive the third clock signal and pass the third clock signal through the OCC; wherein the OCC is configured to pass the third clock signal through the OCC in the following manner: In the functional mode, the transition capture mode, and the fixed capture mode, the third clock signal is passed through a subpath within a first path within a second clock selection circuit in the OCC; and wherein the OCC is configured to pass the second clock signal through the OCC in the following manner: In the transition scan shift mode and the fixed scan shift mode, during the shift phase of the transition and fixed modes, the second clock signal is passed through a sub-path within the second path within the second clock selection circuit in the OCC, and during the shift phase of the transition mode and the fixed mode, the second clock signal is passed through the sub-path within the second clock selection circuit.

16. The test circuit of claim 15 , wherein the phase-locked loop circuit and the frequency divider further generate the first clock signal and the third clock signal as the first PLL clock signal and the second PLL clock signal during a capture phase of the transition mode, and output the first clock signal and the third clock signal as the first ATE clock signal based on the external clock signal during the capture phase of the fixed mode.

17. The test circuit of claim 16, wherein the OCC is further configured to pass the first clock signal, the second clock signal, and the third clock signal through the OCC in the following manner: In the transition mode: passing the second clock signal through an entire second path within the first clock selection circuit in the OCC during the shift phase of the transition mode, and passing the first clock signal through an entire first path within the first clock selection circuit in the OCC during the capture phase of the transition mode; and During the shift phase of the transition mode, the second clock signal is passed through an entire second path within the second clock selection circuit in the OCC, and during the capture phase of the transition mode, the third clock signal is passed through an entire first path within the second clock selection circuit in the OCC.

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