Resolution-adjustable time-to-digital converter based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a resolution-adjustable time-to-digital converter based on an FPGA (Field Programmable Gate Array), and relates to the technical field of digital circuits, the time-to-digital converter adopts CARRY4 units in the FPGA of xilinx to construct a delay chain, the number of the CARRY4 units is 160, and the resolution-adjustable time-to-digital converter based on the FPGA has the advantages that the resolution-adjustable time-to-digital converter based on the FPGA can be adjusted by the aid of the CARRY4 units; a user can conveniently select the resolution of the TDC by himself / herself according to own requirements and resource limitation conditions, the time-to-digital converter solves the problem of single use scene in the traditional TDC, can be used for scenes with various resolutions, can be applied to time-of-flight (TOF) measurement of positron in medical image processing and time measurement in a laser radar, and can also be used for measuring the resolution of the TDC by himself / herself according to the requirements of the user and the limitation condition of resources. The method can be applied to high-resolution use scenes such as time measurement in high-speed particles in high-energy physics, and can also be applied to low-resolution use scenes such as climate change and water resource management.

Description

Technical Field

[0001] The invention relates to the technical field of digital circuits, in particular to a time-to-digital converter with adjustable resolution based on FPGA. Background Art

[0002] At present, the main methods of TDC digital design include counting type TDC, delay chain type TDC, multi-phase clock type TDC, vernier delay chain type TDC, and ring oscillation type TDC. Counting type and multi-phase clock type TDC have low complexity and consume less resources, but limited resolution; vernier type has higher resolution, but complex structure and consumes more resources; ring and delay chain type TDC have average performance in all aspects among these structures.

[0003] The counter of the pulse counter is composed of a group of triggers, which collect the number of clock pulses contained in the time interval between the start signal START and the end signal STOP under the drive of the clock pulse (rising edge or falling edge). The main advantages of the counting TDC structure are simple implementation and low requirements for FPGA hardware resources. However, the maximum resolution that can be achieved is limited by the system clock frequency.

[0004] Delay chain TDC interpolates the clock cycle using time intervals with delay times less than one clock cycle, thereby breaking the clock cycle into time stamps with smaller delays, thereby improving the resolution of the TDC. Its maximum resolution is limited by the delay time and number of the interpolated delay units.

[0005] Multi-phase clock type TDC. Usually, the PLL or clock management module in the FPGA is used to generate multiple clocks with fixed phase differences. The phase clock architecture constructed by this method is not only easy to implement but also has good linearity. The state of the D flip-flop samples the clock with a test hit signal Hit, and then sends the result to a decoding module to obtain fine measurement. The multi-phase clock method can minimize the use of hardware resources and simplify the architecture of the TDC, but the resolution is not high enough.

[0006] Vernier delay chain (VDL) TDC uses two delay units with different delay times to form two delay chains, which can break through the delay time limit of the delay unit caused by the process and achieve higher resolution. Compared with TDC with the same measurement range, the vernier structure requires more delay units, so the vernier TDC consumes more area and power, and the measurement conversion time required for the same measurement time interval is also longer, so the dead time is also longer, and its measurement dynamic range will also be limited.

[0007] Ring oscillator TDC (RO-TDC) can achieve a large dynamic measurement range. However, the resolution of RO-TDC is the delay time of the basic delay unit, so like the delay chain TDC, the resolution of RO-TDC is also limited by the process, resulting in its limit resolution can only reach the size of the gate-level logic unit delay. Since the signal in this ring structure will be continuously transmitted in the loop, it will introduce higher power consumption than TDL-TDC, and like VDL-TDC, PVT will also affect the delay performance of the delay unit of RO-TDC. Therefore, a time-to-digital converter with adjustable resolution based on FPGA is proposed. Summary of the invention

[0008] In view of the deficiencies of the prior art, the present invention provides a time-to-digital converter with adjustable resolution based on FPGA, which solves the problems raised in the above background technology.

[0009] To achieve the above objectives, the present invention is implemented through the following technical solutions: a time-to-digital converter with adjustable resolution based on FPGA, wherein the time-to-digital converter uses the CARRY4 unit in the FPGA of Xilinx to construct a delay chain, and the number of the CARRY4 units is 160.

[0010] Optionally, the process of verifying the time-to-digital converter comprises the following steps: S1: 320 tap values ​​are selected in the delay chain formed by CARRY4 to form a 320-bit binary data as the decoded data; S2: A clock with a time period of 1000ps is added to the initial stage of the delay chain. The 320-bit data will show the same 598 changes in each time period. S3: When the external signal comes, the 320-bit decoded data is recorded at this time. By comparison, the specific position of this signal in the 398 changes can be obtained, so as to know the specific position in 1000ps. The equivalent resolution reaches 1.67ps, which is much longer than the delay time of a single CARRY4 element of dozens to tens of ps.

[0011] Optionally, in the step S1: selecting 320 tap values ​​in the delay chain formed by CARRY4 to form a 320-bit binary data as the decoding data, the values ​​of the 320 taps may be 0 or 1.

[0012] Optionally, the time-to-digital converter implements a high-resolution equivalent delay chain by means of multi-clock multi-cycle coupling. During the decoding process, the resolution provided by the TDC can be selected according to the usage scenario and required resources, so that the TDC can adapt to various scenarios.

[0013] Optionally, S3: when an external signal arrives, the 320-bit decoded data at this time is recorded. By comparison, the specific position of this signal in 398 changes can be obtained, so as to know the specific position in 1000ps. The equivalent resolution reaches 1.67ps, which is far greater than the delay time of a single CARRY4 element of more than ten to several tens of ps. When decoding, it is necessary to compare the recorded 320-bit decoded data with the 598 320-bit data corresponding to the 598 changes.

[0014] Optionally, the 320-bit decoded data and 598 320-bit data corresponding to 598 changes are compared and searched using a binary decoding method. Different binary decoding times can be selected according to resolution requirements and resource constraints. Different binary decoding times correspond to different resolutions and also correspond to different resource usage conditions.

[0015] The present invention provides a time-to-digital converter with adjustable resolution based on FPGA, which has the following beneficial effects: This FPGA-based time-to-digital converter with adjustable resolution allows users to choose the resolution of TDC according to their needs and resource constraints. This time-to-digital converter solves the problem of single usage scenario in traditional TDC and can be used in multiple resolution scenarios. It can be applied to high-resolution usage scenarios such as positron time-of-flight (TOF) measurement in medical image processing, time measurement in lidar, and time measurement in high-speed particles in high-energy physics. It can also be applied to lower resolution usage scenarios such as climate change and water resource management. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 Construct a schematic diagram for the delay chain of the present invention; Figure 2 A schematic diagram of the binary decoding method of the present invention; Figure 3 A schematic diagram of the binary decoding method of the present invention; Figure 4 is a code width distribution diagram under different configurations of the present invention; Figure 5 One of the DNL distribution diagrams under different configurations of the present invention; Figure 6 This is the second DNL distribution diagram under different configurations of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] See also Figures 1 to 6 The present invention provides a technical solution: a time-to-digital converter with adjustable resolution based on FPGA. The time-to-digital converter uses the CARRY4 unit in the FPGA of Xilinx to construct a delay chain. The number of CARRY4 units is 160. The time-to-digital converter realizes a high-resolution equivalent delay chain through multi-clock multi-cycle coupling. During the decoding process, the resolution provided by the TDC can be selected according to the usage scenario and the required resources, so that the TDC can adapt to various scenarios.

[0020] The process of verifying the time-to-digital converter includes the following steps: S1: 320 tap values ​​are selected in the delay chain formed by CARRY4 to form a 320-bit binary data as the decoded data. The values ​​of the 320 taps can be 0 or 1. S2: A clock with a time period of 1000ps is added to the initial stage of the delay chain. The 320-bit data will show the same 598 changes in each time period. S3: When the external signal comes, the 320-bit decoded data is recorded. By comparison, the specific position of the signal in 398 changes can be obtained, so as to know the specific position in 1000ps. The equivalent resolution reaches 1.67ps, which is much longer than the delay time of a single CARRY4 element of dozens to tens of ps. When decoding, it is necessary to compare the recorded 320-bit decoded data with the 598 320-bit data corresponding to the 598 changes, and use the binary decoding method for comparison and search. Different binary decoding times can be selected according to the resolution requirements and resource constraints. Different binary decoding times correspond to different resolutions and also correspond to different resource usage.

[0021] Figure 1 The construction principle of the TDC delay chain shown in can be constructed in a way that exceeds the delay time limit of the delay unit, wherein, Figure 1The minimum delay time of the delay unit is 0.3TCLK, and the actual resolution can reach 0.1TCLK; Figure 2 and Figure 3 Indicates the decoding method. The TDC decoding method adopts a decoding method that approximates binary division. The user can select different decoding cycles according to the scenario in which the TDC is used. The corresponding binary division times of the delay chain decoding are different, and the resource consumption and conversion time are also different.

[0022] in, Figures 4 to 6 Only a portion of the resolution is represented.

[0023] In the description of the present invention, it is necessary to understand that the terms "coaxial", "bottom", "one end", "top", "middle", "the other end", "upper", "one side", "top", "inside", "front", "center", "both ends" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0024] In addition, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include at least one of such features.

[0025] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "screw-on" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0026] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A time-to-digital converter with adjustable resolution based on FPGA, characterized in that: The time-to-digital converter uses the CARRY4 unit in the Xilinx FPGA to construct a delay chain, and the number of the CARRY4 units is 160.

2. The FPGA-based time-to-digital converter with adjustable resolution according to claim 1, characterized in that: The process of verifying the time-to-digital converter comprises the following steps: S1: 320 tap values ​​are selected in the delay chain formed by CARRY4 to form a 320-bit binary data as the decoded data; S2: A clock with a time period of 1000ps is added to the initial stage of the delay chain. The 320-bit data will show the same 598 changes in each time period. S3: When the external signal comes, the 320-bit decoded data is recorded at this time. By comparison, the specific position of this signal in the 398 changes can be obtained, so as to know the specific position in 1000ps. The equivalent resolution reaches 1.67ps, which is much longer than the delay time of a single CARRY4 element of dozens to tens of ps.

3. The FPGA-based time-to-digital converter with adjustable resolution according to claim 1, characterized in that: In the step S1: selecting 320 tap values ​​in the delay chain formed by CARRY4 to form a 320-bit binary data as decoded data, the values ​​of the 320 taps can be 0 or 1.

4. The FPGA-based time-to-digital converter with adjustable resolution according to claim 1, characterized in that: The time-to-digital converter realizes a high-resolution equivalent delay chain by means of multi-clock multi-cycle coupling. During the decoding process, the resolution provided by the TDC can be selected according to the usage scenario and the required resources, so that the TDC can adapt to various scenarios.

5. The FPGA-based time-to-digital converter with adjustable resolution according to claim 1, characterized in that: The S3: when the external signal comes, the 320-bit decoded data at this time is recorded. By comparison, the specific position of this signal in the 398 changes can be obtained, so as to know the specific position in 1000ps. The equivalent resolution reaches 1.67ps, which is far greater than the delay time of a single CARRY4 element of dozens to tens of ps. When decoding, it is necessary to compare the recorded 320-bit decoded data with the 598 320-bit data corresponding to the 598 changes.

6. The FPGA-based time-to-digital converter with adjustable resolution according to claim 5, characterized in that: The 320-bit decoded data and the 598 320-bit data corresponding to the 598 changes are compared and searched using a binary decoding method. Different binary decoding times can be selected according to resolution requirements and resource constraints. Different binary decoding times correspond to different resolutions and also correspond to different resource usage conditions.

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