Direct decision feedback equalization single-ended receiver

Abstract

The invention relates to a direct decision feedback equalization single-ended receiver. A system includes a memory subsystem controller to transmit data signals via a communication channel. The system includes a receiver to receive the data signal from the memory subsystem controller via an interface, the receiver including a decision feedback equalizer (DFE) subsystem. The DFE subsystem includes a first data detector circuit including a first tap circuit, wherein the first data detector circuit generates a first subset of detected bit values corresponding to the data signal using a first reference voltage. The DFE subsystem includes a second data detector circuit including a second tap circuit, wherein the second data detector circuit generates a second subset of detected bit values corresponding to the data signal using a second reference voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to data communications, and more particularly, to high-speed interfaces and data communications paths with direct decision feedback equalization for data transfers associated with memory devices in a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, nonvolatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a system comprising: a memory subsystem controller for transmitting a data signal via a communication channel; a receiver for receiving the data signal from the memory subsystem controller via an interface, the receiver comprising a decision feedback equalizer (DFE) subsystem, the DFE subsystem comprising: a first data detector circuit comprising a first tap circuit, wherein the first data detector circuit generates a first detected bit value subset corresponding to the data signal using a first reference voltage; and a second data detector circuit comprising a second tap circuit, wherein the second data detector circuit generates a second detected bit value subset corresponding to the data signal using a second reference voltage.

[0004] On the other hand, the present disclosure provides a memory device comprising: a memory array comprising a group of memory cells; and a decision feedback equalizer (DFE) subsystem, the DFE subsystem comprising: a first data detector circuit comprising a first tap circuit, wherein the first data detector circuit uses a first reference voltage to generate a first detected bit value subset corresponding to a data signal; and a second data detector circuit comprising a second tap circuit, wherein the second data detector circuit uses a second reference voltage to generate a second detected bit value subset corresponding to the data signal.

[0005] On the other hand, the present disclosure provides a method comprising: receiving a data signal via an interface coupled to a memory subsystem controller; generating a first detected bit value subset corresponding to the data signal by a first data detector circuit including a first tap circuit using a first reference voltage; and generating a first detected bit value subset corresponding to the data signal by a second data detector circuit including a second tap circuit using a second reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1A An example computing system including a memory subsystem according to one or more embodiments of the present disclosure is described.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to one or more embodiments of the present disclosure.

[0009] Figures 2A to 2D According to one or more embodiments of the present disclosure, as can be seen in reference Figure 1B Schematic diagram of a portion of a memory cell array used in a memory of the type described.

[0010] Figure 3 According to one or more embodiments of the present disclosure, as can be seen in reference Figure 1B A block schematic diagram of a portion of a memory cell array used in a memory of the type described.

[0011] Figure 4 An example memory subsystem is described that includes a transmitter to transmit data via a communication channel to a receiver including a direct decision feedback equalizer to generate digital samples corresponding to the received data in accordance with one or more embodiments of the present disclosure.

[0012] Figure 5 An example direct decision feedback equalizer is described in accordance with one or more embodiments of the present disclosure.

[0013] Figure 6 An example single-tap data detector for a direct decision feedback equalizer is illustrated in accordance with one or more embodiments of the present disclosure.

[0014] Figure 7 An example multi-tap data detector for a direct decision feedback equalizer is described in accordance with one or more embodiments of the present disclosure.

[0015] Figure 8 is a flow chart of an example method of generating a set of detected bit values ​​corresponding to an incoming data signal received from a transmitter via a communication channel according to one or more embodiments of the present disclosure.

[0016] Fig. 9 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure are directed to enhancing the speed capability of data transfer in a data path using direct mode decision feedback equalization of data associated with a memory device in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1A to 1B Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0018] The memory subsystem may include a high-density non-volatile memory device where it is desirable to retain data when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1A Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may include two or more planes. For some types of nonvolatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. In some implementations, each block may include multiple sub-blocks. Each plane carries a matrix of memory cells formed on a silicon wafer and connected by conductors called word lines (WL) and bit lines (BL), such that word lines connect multiple memory cells forming rows of the memory cell matrix, and bit lines connect multiple memory cells forming columns of the memory cell matrix.

[0019] Each memory cell can store one or more binary bits of information, depending on the cell type, and have various logic states related to the number of bits stored. The logic states can be represented by binary values ​​(e.g., "0" and "1" or a combination of such values), also referred to herein as logic bit values. Memory cells can be programmed (written) by applying a certain voltage to the memory cells, which causes charge to be stored by the memory cells, thus allowing the voltage distribution generated by the memory cells to be modulated. A group of memory cells, called a memory page, can be programmed together in a single operation (e.g., by selecting consecutive bit lines).

[0020] A memory device may consist of bits arranged in a two-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device, which together with one or more bit lines are used to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. A block hereinafter refers to a unit of a memory device used to store data, and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of a memory device in order to allow concurrent operations to occur on each plane. A memory device may include a circuit system that performs concurrent memory page accesses of two or more memory planes. For example, a memory device may include a corresponding access line driver circuit and a power supply circuit for each plane of the memory device to facilitate concurrent access of pages of two or more memory planes (including different page types (e.g., LP, UP, XP, and TP)).

[0021] To perform a programming operation initiated by a host system, data to be programmed into a memory array of a memory device is transmitted via a communication channel or data path between a transmitter (e.g., a memory subsystem controller) and a receiver (e.g., a memory device) in a double data rate (DDR) memory subsystem. Several signal processing techniques may be applied to monitor and verify the accuracy of high-speed data transmitted to the memory device. For example, the transmitter and receiver may employ a serializer / deserializer (SerDes) technology configured to perform techniques (e.g., equalization techniques) to mitigate high inter-symbol interference (ISI) from highly dispersive and reflective channels. Example equalization techniques include linear algorithms, such as zero forcing and minimum mean square estimation (MMSE) equalizers. In a linear equalizer, each output sample is a simple linear combination of the input samples (i.e., as determined by the equalizer taps). However, linear equalizers suffer from significant performance issues, including the generation of signal noise and the generation of inaccurate sample estimates.

[0022] Therefore, to address the shortcomings associated with linear equalization in a single-ended receive path, some transmission systems employ decision feedback equalization (DFE). Decision feedback equalization employs nonlinear equalization to equalize a channel using a feedback loop based on previously decided symbols, which can be used to remove ISI and other noise. DFE provides nonlinear equalization that relies on decisions about the level (e.g., high / low) of previous symbols to correct current symbol estimates to allow the DFE to account for current symbol distortion caused by previous symbols. Some DFE configurations use a slicer to quantize a signal into a binary "1" or "0" based on a sampled value and a slicer threshold. These DFE architectures employ multiple data detectors or digital slicers to perform detection on the signal to recover the actual data being transmitted. Each slicer is configured to produce detected data bits or symbols acquired at time intervals (e.g., data samples associated with time n). In one example, the data detector performs a slice operation to convert a first analog value into a digital decision estimate or sample, thereby reflecting a filtered or equalized version of the equalized input signal. The data detector may include one or more latches that "slice" the voltage at a programmable threshold or an ADC that produces a multi-bit output from which data may be detected and used for purposes of programming the memory cells of the memory device.

[0023] According to certain methods, two data detectors or slicers are employed to generate digital estimates of different samples of an incoming or transmitted signal. Each slicer acquires samples of the incoming signal (i.e., the transmitted signal) at a time interval (e.g., the first slicer acquires a first sample at time T0, the second slicer acquires a second sample at time T1, the first slicer acquires a third sample at time T2, and so on), and compares it to a common static reference voltage level to generate a digital estimate of the data sample. For example, if the incoming signal value is greater than the reference voltage level, then the slicer may determine the digital estimate to be "1", or if the incoming signal value is less than the reference voltage level, then the slicer may determine the digital estimate to be "0". According to these implementations, the two slicers share the same or common static reference voltage. The DFE may include one or more taps applied to the normalized voltage based on a symbol slicer decision, where the tap value is used to correct a portion of the tap symbol that distorts the current symbol. Each tap is associated with a weight or "tap coefficient" to adjust the slicer response to compensate for unknown factors and elements of the communication medium between the transmitter and the receiver.

[0024] In some DFE architectures, two limiters are used in a half-rate scheme, where each limiter is associated with its own offset. The offset may be due to differences in transistors arranged in the incoming signal path and the reference voltage path (e.g., due to manufacturing differences). To compensate for any offset between the incoming signal path and the reference voltage path, a source degeneration resistor scheme may be employed, where an offset correction circuit (e.g., a set of transistors) is arranged in the incoming signal path and the reference voltage path. However, implementing dedicated offset correction circuitry in the respective paths results in a degradation of the signal speed. This speed loss is caused by the resistance associated with the offset correction circuit arranged in series with the incoming signal path.

[0025] Furthermore, these architectures use a single reference voltage (i.e., common Vref) that provides a static voltage level for each of the slicers to use when generating a digital estimate of the received data signal. Since the resistances of the two offset correction circuitry are in series and the corresponding resistances are fixed, the total switch resistance is non-linear if binary code resistances are used.

[0026] In some architectures, each limiter includes a capacitive circuit system for enabling tap functionality. For example, each limiter may include a first capacitive circuit arranged in an incoming signal path, wherein the first capacitive circuit stores a voltage (i.e., a capacitor voltage) for controlling the limiter tap. The incoming signal is received by one or more transistors of the limiter and passed through the capacitive circuit, wherein the capacitor voltage is increased to increase the signal voltage amplitude to improve the detectability of the signal at high frequency rates and control the feedback tap. Similarly, a second capacitive circuit is arranged in a reference voltage path to increase the reference voltage before comparing with the increased incoming signal voltage. However, as data rates increase, the introduction of capacitive storage in the data path can lead to a degradation of signal speed.

[0027] In addition, some DFE architectures include multi-tap limiters. In these approaches, each of the multiple taps of the limiter has a corresponding capacitive circuit disposed in the main signal path. Therefore, the multiple capacitive circuits in the main signal path used to control the operation of the corresponding taps of the multi-tap limiter disadvantageously reduce the data rate of the DFE.

[0028] Aspects of the present disclosure address the above and other deficiencies by implementing a direct decision feedback equalization mode method to enhance the speed capability of data transmitted via a data path between a transmitter (e.g., a memory subsystem controller) and a single-ended receiver (e.g., a memory device). In an embodiment, decision feedback equalization (also referred to as direct decision feedback equalization) is implemented using a direct decision feedback equalizer (i.e., a direct DFE that directly receives an incoming signal from a transmitter) that includes a plurality of data detectors (e.g., a first slicer and a second slicer) each associated with a respective reference voltage. According to an embodiment, the direct DFE interface processes a single-ended signal received from a memory subsystem controller.

[0029] According to an embodiment, the direct DFE includes a first limiter (Limiter 1) associated with a first reference voltage (Vref1) and a second limiter (Limiter 2) associated with a second reference voltage (Vref2). Advantageously, the use of multiple reference voltages enables the removal of dedicated offset compensation circuitry from the data path. According to an embodiment, the use of two different reference voltages for the two limiters enables high-speed transmission that is not degraded by having source degeneration resistance in the high-speed data path. Advantageously, two different reference voltages (i.e., Vref1 for the first limiter and Vref2 for the second limiter) are used to cancel limiter offsets without the need to use offset correction circuitry in the data path.

[0030] According to an embodiment, each limiter includes an independent voltage generator circuit to generate a voltage (referred to herein as a "tap voltage") for controlling a feedback tap of the limiter. Advantageously, the tap voltage is generated by the tap voltage generator to control the limiter tap in a branch parallel to the signal path, thereby enabling the removal of capacitive circuitry from the signal path. The use of the tap voltage generator in a parallel branch relative to the main or primary signal path provides control of the tap functionality without the need for separate capacitive circuitry in the signal path, which results in an increase in data rate processing for direct DFE.

[0031] According to an embodiment, a direct DFE may be used with a limiter having multiple taps (e.g., tap 1, tap 2, tap 3, etc.) Advantageously, the multi-tap direct DFE may include a tap voltage generator arranged in parallel with the signal path for controlling the multiple taps without using capacitive circuitry for each tap in the signal path.

[0032] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0033] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0034] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0035] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 via an interface 50 (e.g., a peripheral component interconnect (PCI) or a serial advanced technology attachment (SATA) interface) is illustrated. As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0036] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system 120 uses the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0037] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a fiber optic backbone, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0038] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0039] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0040] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single level memory cell (SLC), may store one bit per memory cell. Other types of memory cells, such as multi-level memory cells (MLC), three-level memory cells (TLC), four-level memory cells (QLC), and five-level memory cells (PLC), may store multiple bits per memory cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0041] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory or electrically erasable programmable read-only memory (EEPROM).

[0042] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0043] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0044] In some embodiments, local memory 119 may include a memory page buffer that stores memory pointers, fetched data, etc. Local memory 119 may also include a read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0045] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0046] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0047] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic on the die (e.g., the local media controller 132) and a controller for media management (e.g., the memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0048] Figure 1B is in accordance with an embodiment and presents a memory subsystem (eg, Figure 1A 1 is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 of a memory subsystem 110 of an electronic system. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory.

[0049] Memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells of a logical row are connected to the same access line (e.g., word line), while memory cells of a logical column are selectively connected to the same data line (e.g., bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1B ) can be programmed to one of at least two target data states.

[0050] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to memory device 130 and the output of data and status information from memory device 130. Address register 114 (address page buffer) communicates with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 111 to latch address signals prior to decoding. Command register (or command page buffer) 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0051] According to an embodiment, the I / O control circuitry 112 includes a direct DFE 134 to receive incoming data associated with the memory device 130 (e.g., data for a programming operation associated with the memory device 130). According to an embodiment of the present disclosure, the direct DFE 134 receives the incoming data (e.g., data transmitted by the memory subsystem controller 115) and generates a digital estimate associated with a sample of the transmitted data signal. As described in more detail below, the direct DFE 134 includes two data detector circuits (i.e., two slicers) that each employ a respective reference voltage to generate a corresponding digital sample. According to an embodiment, the direct DFE 134 controls the first slicer using a first reference voltage and controls the second slicer using a second reference voltage. Advantageously, the use of two different reference voltages to control the two slicers cancels or corrects the offset between the slicers without the need for additional offset correction circuitry in the signal path. Eliminating the need for additional offset correction circuitry in view of correcting the slicer offset due to the use of two different reference voltages increases the data rate and frequency capabilities of the I / O control circuitry 112.

[0052] According to an embodiment, each limiter of the direct DFE 134 includes a separate or independent voltage generator circuit to generate a voltage (referred to herein as a "tap voltage") used to control a feedback tap of the limiter. According to an embodiment, a tap voltage generator that generates a tap voltage to control the limiter tap is arranged in a branch of the limiter circuitry in parallel with the signal path. Therefore, the limiter tap can be controlled by the tap voltage without the need for capacitive circuitry arranged in the signal path (i.e., in series with the incoming signal). Therefore, using a voltage generator to provide the tap voltage in a parallel branch can result in an increase in the processing speed of the direct DFE because no capacitive elements are used within the signal path. Providing the tap voltage using a tap voltage generator in parallel with the signal path emulates the function performed by capacitive circuitry in previous DFE architectures.

[0053] A controller (e.g., a local media controller 135 inside the memory device 130) controls access to the memory cell array 104 in response to a command and generates status information for the external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform an access operation (e.g., a read operation, a program operation, and / or an erase operation) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 111 to control the row decoding circuitry 108 and the column decoding circuitry 111 in response to an address. In one embodiment, the local media controller 135 includes a direct DFE 134 that can implement a page mapping scheme including placing first data associated with a first subset of page types (e.g., LP and UP) into a first subset of memory cells of a first subset of bit lines (e.g., even-numbered bit lines) and placing second data associated with a second subset of page types (e.g., XP and TP) into a second subset of memory cells of a second subset of bit lines (e.g., odd-numbered bit lines) during a programming operation of a set of target memory cells of one or more memory devices 130.

[0054] The local media controller 135 also communicates with the cache register 118. The cache register 118 latches data (either incoming or outgoing) as directed by the local media controller 135 to temporarily store the data while the memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from the cache register 118 to the data register 121 for transfer to the memory cell array 104; the new data from the I / O control circuitry 112 may then be latched in the cache register 118. During a read operation, data may be transferred from the cache register 118 to the I / O control circuitry 112 for output to the memory subsystem controller 115; the new data may then be transferred from the data register 121 to the cache register 118. The cache register 118 and / or the data register 121 may form (e.g., may form part of) a page buffer of the memory device 130. The page buffer may further include a sensing device ( ) for sensing the data state of a memory cell of the memory cell array 104 (eg, by sensing the state of a data line connected to that memory cell). Figure 1B 1 . A status register (or status page buffer) 122 may communicate with the I / O control circuitry 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0055] The memory device 130 receives control signals from the local media controller 135 at the memory subsystem controller 115 through the control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be further received through the control link 132.

[0056] According to an embodiment, the memory device 130 receives a command signal (which indicates a command), an address signal (which indicates an address), and a data signal (which indicates data) from the memory subsystem controller 115 through a multiplexed input / output (I / O) interface 136, and outputs the data to the memory subsystem controller 115 through the I / O interface 136. In an embodiment, the memory subsystem controller 115 operates as a transmitter to transmit one or more data signals to the memory device 130 (i.e., a receiver) including a direct DFE via a communication channel (i.e., the I / O interface 136) to receive and process the one or more data signals.

[0057] For example, commands may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O interface 136 and may then be written into command page buffer 124. Addresses may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O interface 136 and may then be written into address page buffer 114. Data may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device and may then be written into cache register 118. The data may then be written into data register 121 for use in programming memory cell array 104.

[0058] In an embodiment, cache register 118 may be omitted and data may be written directly into data register 121. Data may also be output through input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference may be made to I / O pins, they may include any conductive node that provides an electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115), such as a commonly used conductive pad or conductive bump.

[0059] Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified. Figure 1A to 1B It should be appreciated that reference Figure 1A to 1BThe functionality of the various block components described need not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1A to 1B Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1A to 1B Additionally, while specific I / O pins are described according to general conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0060] Figures 2A to 2D is a diagram of a portion of an example memory cell array included in a memory device according to some embodiments of the present disclosure. For example, Figure 2A 2 is a schematic diagram of a portion of a memory cell array 200A (eg, as a portion of memory cell array 104) as may be used in a memory device. The memory array 200A includes access lines (eg, word lines 2020 to 2021). N ) and data lines (e.g., bit lines 204). Word lines 202 may be connected to Figure 2A For some embodiments, memory array 200A may be formed on a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity, such as to form a p-well, or a conductivity type such as n-type conductivity, such as to form an n-well.

[0061] The memory array 200A may be arranged into rows that each correspond to a respective word line 202 and columns that each correspond to a respective bit line 204. The rows of memory cells 208 may be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 may include every other memory cell 208 commonly connected to a given word line 202. For example, a physical page of memory cells 208 commonly connected to a word line 202 may be divided into one or more groups of physical pages of memory cells 208. N The memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be one physical page of memory cells 208 (eg, even memory cells), while the memory cells 208 commonly connected to the word line 202 may be one physical page of memory cells 208 (eg, even memory cells). N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041, 2043, 2045, etc.) may be another physical page of the memory cells 208 (eg, odd memory cells). Figure 2A 2043 to 2045 are not explicitly depicted in the figure, but it can be understood from the figure that the bit lines 204 of the memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204. M. Other groupings of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered a physical page of memory cells. The portion of a physical page of memory cells (which may still be an entire row in some embodiments) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 through 2021. N Unless expressly distinguished otherwise, references herein to a page of memory cells refer to memory cells of a logical page of memory cells.

[0062] Each column may include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as strings 2060 through 206 M Each string 206 can be connected (eg, selectively connected) to a source line (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 of each string 206 may be connected in series at a select gate 210 (eg, select gates 2100 to 210 M ) and the selection gate 212 (e.g., the selection gate 2120 to 212 M In some embodiments, gates 2100 to 210 M is a source side select gate (SG) and selects gates 2120 to 212 M It is the drain side selection gate. Select gate 2100 to 210 M can be connected to a select line 214 (eg, a source side select line) and select gates 2120 to 212 M 214. The drain of each select gate 212 may be connected to the bit line 204 of the corresponding string 206. The source of each select gate 210 may be connected to the SRC 216, and the drain of each select gate 210 may be connected to the memory cell 2080 of the corresponding string 206. Thus, each select gate 210 may be configured to selectively connect the corresponding string 206 to the SRC 216. The control gate of each select gate 210 may be connected to the select line 214. The drain of each select gate 212 may be connected to the bit line 204 of the corresponding string 206. The source of each select gate 212 may be connected to the memory cell 2080 of the corresponding string 206. NThus, each select gate 212 can be configured to selectively connect a corresponding string 206 to a bit line 204 . The control gate of each select gate 212 can be connected to a select line 215 .

[0063] In some embodiments, and as will be referred to below Figure 2B To describe in further detail, Figure 2A The memory array in is a three-dimensional memory array in which the strings 206 extend substantially perpendicular to a plane containing the SRCs 216 and a plane containing the plurality of bit lines 204 (which may be substantially parallel to the plane containing the SRCs 216).

[0064] Figure 2B 2 is another schematic diagram of a portion of a memory cell array 200B (e.g., a portion of memory cell array 104) arranged in a three-dimensional memory array structure. The three-dimensional memory array 200B may incorporate a vertical structure that may include a semiconductor pillar, wherein a portion of the pillar may serve as a channel region for a memory cell of a string 206. The strings 206 may each be selectively connected to bit lines 2040 to 2044 through a select gate 212. M The plurality of strings 206 can be selectively connected to the same bit line 204. By biasing the select lines 2150 to 215 L A subset of the strings 206 may be connected to their respective bit lines 204 by selectively activating a particular select gate 212 each between the string 206 and the bit line 204. The select gates 210 may be activated by biasing the select line 214. Each word line 202 may be connected to multiple rows of memory cells of the memory array 200B. The rows of memory cells that are generally connected to each other by a particular word line 202 may be collectively referred to as a level.

[0065] Figure 2C Depicting the grouping of NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500 to 250 L . A memory cell block 250 may be a grouping of memory cells 208 that may be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The source 216 of a memory cell block 2500 may be a grouping of memory cells 208 that may be erased together in a single erase operation, sometimes referred to as an erase block. L For example, each memory cell block 2500 to 250 L The access line 202 and the select lines 214 and 215 of one memory cell block 250 may not be connected to the memory cell blocks 250 to 250, respectively. LThe access line 202 and the select lines 214 and 215 of any other memory cell block in the memory cell block are directly connected.

[0066] Bit lines 2040 to 204 M The buffer portion 240 may be connected (eg, selectively connected) to the buffer portion 240, which may be part of the page buffer 152 of the memory device 130. The buffer portion 240 may correspond to a memory plane (eg, a group of memory cell blocks 2500 to 250 L Buffer portion 240 may include sensing circuitry (which may include a sense amplifier) ​​for sensing the data value indicated on corresponding bit line 204 .

[0067] Figure 2D 2 is a diagram of a portion of a memory cell array 200D (eg, a portion of the memory cell array 104). A channel region (eg, semiconductor pillar) 238 00 and 238 01 2040 selectively connected to the memory cell strings (eg, Figures 2A to 2C Similarly, the channel region 238 10 and 238 11 2041 selectively connected to the bit line 2041 of the memory cell string (eg, Figures 2A to 2C The channel region of the NAND string 206). The memory cell ( Figure 2D 2 (not depicted) may be formed at each intersection of the word line 202 and the channel region 238, and the memory cells corresponding to the single channel region 238 may collectively form a series-connected memory cell string (eg, Figures 2A to 2C In such structures, additional features such as dummy word lines, segmented channel regions with intermediate conductive regions, etc. may be common.

[0068] Figure 3 If you can refer to Figure 1B 1 is a block schematic diagram of an example portion of a memory cell array 300 for use in a memory of the type described. The memory cell array 300 is depicted as having four memory planes 350 (e.g., memory planes 3500-3503) that each communicate with a respective buffer portion 240, which may collectively form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 may collectively communicate with the page buffer 352. Each memory plane 350 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500-2503). L ).

[0069] Figure 4An example memory subsystem 410 is illustrated according to an embodiment of the present disclosure, which includes a memory subsystem for transmitting data 101 to a receiver 430 (eg, Figure 1A and 1B Memory device 130) of transmitter 415 (e.g., Figure 1A and 1B The receiver 430 includes a direct decision feedback equalizer 134 for generating digital samples corresponding to the received data 105. In an embodiment, the transmitted data 101 may be transmitted by a host system (e.g., Figure 1A ) is provided to the transmitter 415 and involves a memory device (eg, Figure 1A and 1B According to an embodiment, transmitter 415 may include a memory subsystem controller communicatively coupled to the memory device via communication channel 103, which may include any suitable communication medium, including but not limited to traces, cables, circuit boards, etc.

[0070] According to an embodiment, receiver 430 is a single-ended receiver including direct DFE 134 that receives transmitted data 101 “directly” as input and performs nonlinear equalization to produce digital output 105 that includes decisions regarding bit values ​​(e.g., bit values ​​“0” or “1”) corresponding to the incoming or transmitted signal, such as decisions regarding Figure 5 Describe in more detail.

[0071] Figure 5 The direct decision feedback equalizer (DFE) 134 according to an embodiment of the present disclosure is described. Figure 5, the direct DFE 134 includes two data detector circuits (i.e., a first slicer 550 and a second slicer 552) that each generate a digital output that includes a digital decision related to the bit value of a corresponding sample of the incoming signal received from the transmitter. In an embodiment, a clock generator generates a clock signal 503 for use by the first slicer 550 and the second slicer 552 to collect a set of time-based samples (e.g., a first sample, a second sample, a third sample, a fourth sample, a fifth sample, a sixth sample, etc.) of the incoming signal. For example, the first slicer 550 may acquire a first subset of samples (e.g., a first sample, a third sample, a fifth sample, etc.) corresponding to a first set of sample points based on the clock signal 503 (e.g., a first sample at time Tn, a third sample at time Tn+2, and so on). Similarly, in this example, the second limiter 552 can acquire a second subset of samples (e.g., the second sample, the fourth sample, the sixth sample, etc.) corresponding to the second group of sample points based on the clock signal 503 (e.g., acquiring the second sample at time Tn+1, acquiring the fourth sample at time Tn+3, and so on).

[0072] like Figure 5 , the direct DFE 134 includes a reference voltage generator 503 that generates a first reference voltage (Vref1) for use by a first slicer 550 and a second reference voltage (Vref2) for use by a second slicer 552. For example, the first slicer 550 compares a voltage level associated with a sample acquired from an incoming signal (Vslicer1(Tn)) at a first time (e.g., Tn) with the first reference voltage (Vref1) to generate a digital sample (e.g., a bit value "0" or "1" corresponding to the incoming signal at time Tn). Continuing with this example, the second slicer 552 compares a voltage level associated with a sample acquired from an incoming signal (Vslicer2(Tn+1)) at a second time (e.g., Tn+1) with the second reference voltage (Vref2) to generate a digital sample (e.g., a bit value "0" or "1" corresponding to the incoming signal at time Tn+1).

[0073] According to an embodiment, generating separate and different reference voltages and supplying them to the respective limiters (i.e., the first limiter 550 and the second limiter 552) compensates for any offset between the first limiter 550 and the second limiter 552. Advantageously, using two different reference voltages (Vref1 supplied to the first limiter 550 and Vref2 supplied to the second limiter 552) to compensate for limiter offset eliminates the need to include dedicated offset compensation circuitry within the signal path. This results in an increase in the data processing speed of the direct DFE 134.

[0074] Figure 6A direct DFE (eg, Figure 1A , 1B , 4 and 5) of the direct DFE 134) of the example single tap data detector 650 (e.g., Figure 5 The first limiter 550 or Figure 5 second limiter 552). Although Figure 6 The elements of the first limiter or the second limiter of the direct DFE according to the embodiment of the present disclosure are described, but the following description refers to the first limiter (eg, Figure 5 The first limiter 550) is an element of the embodiment of the present invention. Figure 6 , the data detector 650 includes a first tap voltage generator that generates a first tap voltage (e.g., a tap coefficient) that controls a first tap switch and a second tap voltage generator that controls a second tap voltage (e.g., a tap coefficient) of a second tap switch to control a bit feedback loop of the single-tap data detector 650. In an embodiment, a single-tap voltage generator may be used to generate both the first tap voltage and the second tap voltage.

[0075] As illustrated, one or more tap voltage generators are arranged in a circuit branch in parallel with the corresponding signal path. Thus, the tap path and the signal path are parallel to each other, so that the tap switch and the tap voltage generator are arranged in parallel with the signal path (i.e., outside the signal path). As described above, parallel path tap voltage generation in a multi-tap configuration allows the removal of capacitive circuits in the signal path. Since the tap coefficient branch is in parallel with the signal path, the speed of the corresponding signal path is increased.

[0076] like Figure 6 As described in FIG. 6 , the data detector 650 receives data from a clock generator (eg, Figure 5 The clock signal of the clock generator 501) and the corresponding reference voltage (for example, Figure 5 The Vref1 of the first limiter 550 or Figure 5 Vref2 of the second limiter 552).

[0077] Figure 7 A direct DFE (eg, Figure 1A , 1B , 4 and 5) of the direct DFE 134) of the example multi-tap data detector 750 (e.g., Figure 5 The first limiter 550 or Figure 5 The second limiter 552). Figure 7, the multi-tap data detector 750 includes multiple taps (e.g., tap1 and tap2). According to an embodiment, the multi-tap detector 750 may include any number of taps. In an embodiment, the multi-tap data detector 750 includes one or more tap voltage generators that generate tap voltages that control switches associated with the multiple taps. In an embodiment, a single tap voltage generator may be used to generate tap voltages for both tap1, tap2, and so on.

[0078] As mentioned above Figure 6 As described, one or more tap voltage generators are arranged in one or more circuit branches in parallel with the corresponding signal path. Thus, the tap path and the signal path are parallel to each other, so that the tap switches and the tap voltage generators are arranged in parallel with the signal path (i.e., outside the signal path). Advantageously, compared to certain DFE architectures, the two data detectors 650 of the direct DFE 134 of the present disclosure do not include capacitive circuits in the signal path. Thus, by having independent tap voltage generators in parallel with the signal path, the speed of the corresponding signal path is increased.

[0079] like Figure 6 As described in FIG. 6 , the data detector 650 receives data from a clock generator (eg, Figure 5 The clock signal of the clock generator 501) and the corresponding reference voltage (for example, Figure 5 The Vref1 of the first limiter 550 or Figure 5 Vref2 of the second limiter 552).

[0080] Figure 8 800 is a flow chart of an example method for generating a set of detected bit values ​​corresponding to an incoming data signal received from a transmitter via a communication channel. According to an embodiment, method 800 may be performed by a system or subsystem that includes a transmitter that receives a data signal via a communication channel (e.g., Figure 4 The communication channel 103 of the memory subsystem is coupled to a circuit system (eg, a single-ended receiver (eg, a memory device of the memory subsystem) of a transmitter (eg, a memory subsystem controller of the memory subsystem). Figure 1A , 1B , 4 and 5 of the direct decision feedback equalizer 134). Although shown in a particular order or sequence, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0081] At operation 810, a signal is received. For example, the system (e.g., Figure 1A , 1B, 4, and 5) may receive a data signal via a communication channel. According to an embodiment, the data signal may include data associated with one or more memory access operations to be performed on the memory device (e.g., data to be programmed to at least a portion of a memory array of the memory device). In an embodiment, the data signal may be received by a memory subsystem controller (e.g., Figure 1A and 1B In an embodiment, the data signal may be an analog signal communicated via a communication channel (eg, a trace, a circuit board, a cable, etc.) and received "directly" (ie, without pre-processing) by the direct DFE.

[0082] At operation 820, a first subset of values ​​is generated. For example, a first data detector circuit having one or more taps of a direct DFE (i.e., a first slicer) may generate a first subset of detected bit values ​​corresponding to the data signal using a first reference voltage. According to an embodiment, the first data detector circuit may compare a voltage level associated with a sample of the data signal (e.g., a first sample acquired at a first time Tn) to a first reference voltage level. In an embodiment, based on the comparison, the first data detector circuit generates corresponding detected bit values ​​(e.g., if the sampled voltage level is greater than the first reference voltage level, then the detected bit value is equal to "1", and if the sampled voltage level is less than or equal to the first reference voltage level, then the detected bit value is equal to "0"). According to an embodiment, the first subset of detected bit values ​​corresponds to a first subset of samples acquired by the first data detector (e.g., samples acquired at times Tn, Tn+2, Tn+4, etc.).

[0083] At operation 830, a second subset of values ​​is generated. For example, a second data detector circuit having one or more taps of a direct DFE (i.e., a second slicer) may generate a second subset of detected bit values ​​corresponding to the data signal using a second reference voltage. According to an embodiment, the second data detector circuit may compare a voltage level associated with a sample of the data signal (e.g., a sample acquired at time Tn+1) to a second reference voltage level. In an embodiment, based on the comparison, the second data detector circuit generates corresponding detected bit values ​​(e.g., if the sampled voltage level is greater than the second reference voltage level, then the detected bit value is equal to "1", and if the sampled voltage level is less than or equal to the second reference voltage level, then the detected bit value is equal to "0"). According to an embodiment, the second subset of detected bit values ​​corresponds to a second subset of samples acquired by the first data detector (e.g., samples acquired at times Tn+1, Tn+3, Tn+5, etc.).

[0084] According to an embodiment, the first reference voltage and the second reference voltage are different from each other, such as Figure 5Advantageously, the use of two different reference voltages (ie, one for each slicer) results in offset cancellation between the two slicers, thereby enhancing the data rate of the direct DFE by eliminating dedicated offset correction circuitry from the signal path.

[0085] Fig. 9 An example machine illustrating a computer system 900 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 900 may correspond to a host system (e.g., Figure 1A 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110 of the embodiment of the present invention may be used to perform the operation of the controller (for example, to execute the operating system to perform the operation corresponding to the above reference Figure 1A , Figure 1B and Figures 4 to 8 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0086] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0087] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 918, which communicate with each other via a bus 930.

[0088] The processing device 902 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. The computer system 900 may further include a network interface device 908 for communicating over a network 920.

[0089] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 926 or software embodying any one or more of the methodologies or functionality described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or the main memory 904 may correspond to Figure 1A Memory subsystem 110.

[0090] In one embodiment, instructions 926 include instructions for implementing the Figure 1A , Figure 1B and Figures 4 to 8 The machine-readable storage medium 924 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0091] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally considered herein to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Mainly for common purposes, it sometimes proves convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0092] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's page buffers and memories into other data similarly represented as physical quantities within the computer system's memory or page buffers or other such information storage systems.

[0093] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0094] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0095] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0096] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a memory subsystem controller for transmitting data signals via a communication channel; A receiver, configured to receive the data signal from the memory subsystem controller via an interface, the receiver comprising a decision feedback equalizer (DFE) subsystem, the DFE subsystem comprising: a first data detector circuit comprising a first tap circuit, wherein the first data detector circuit generates a first subset of detected bit values ​​corresponding to the data signal using a first reference voltage; and A second data detector circuit includes a second tap circuit, wherein the second data detector circuit generates a second subset of detected bit values ​​corresponding to the data signal using a second reference voltage. 2 . The system of claim 1 , wherein the DFE subsystem further comprises one or more reference voltage generation circuits for generating the first reference voltage and the second reference voltage.

3. The system of claim 1, wherein the first reference voltage is different from the second reference voltage.

4. A system according to claim 1, wherein the first data detector circuit includes a tap voltage generating circuit for generating a first tap voltage for controlling a first tap switch of the first tap circuit of the first data detector circuit and a second tap voltage for controlling a second tap switch of the first tap circuit of the first data detector circuit. 5 . The system of claim 4 , wherein the tap voltage generating circuit is arranged in parallel with a first path corresponding to the data signal.

6. The system of claim 1, wherein the receiver comprises a memory device comprising an array of memory cells.

7. The system of claim 6, wherein the data signal comprises data to be programmed into at least a portion of the memory cell array.

8. A memory device comprising: a memory array comprising a set of memory cells; and A decision feedback equalizer (DFE) subsystem, the DFE subsystem comprising: a first data detector circuit comprising a first tap circuit, wherein the first data detector circuit generates a first subset of detected bit values ​​corresponding to the data signal using a first reference voltage; and A second data detector circuit includes a second tap circuit, wherein the second data detector circuit generates a second subset of detected bit values ​​corresponding to the data signal using a second reference voltage.

9. The memory device of claim 8, wherein the DFE subsystem further comprises one or more reference voltage generation circuits to generate the first reference voltage and the second reference voltage.

10. The memory device of claim 8, wherein the first reference voltage is different from the second reference voltage.

11. The memory device of claim 8, wherein the first reference voltage and the second reference voltage offset an offset between the first data detector circuit and the second data detector circuit.

12. A memory device according to claim 8, wherein the first data detector circuit includes a tap voltage generating circuit for generating a first tap voltage for controlling a first tap switch of the first tap circuit of the first data detector circuit and a second tap voltage for controlling a second tap switch of the first tap circuit of the first data detector circuit.

13. The memory device of claim 12, wherein the tap voltage generating circuit is arranged in parallel with a first path corresponding to the data signal.

14. A method comprising: receiving a data signal via an interface coupled to a memory subsystem controller; generating, by a first data detector circuit including a first tap circuit, a first subset of detected bit values ​​corresponding to the data signal using a first reference voltage; and A second subset of detected bit values ​​corresponding to the data signal is generated by a second data detector circuit including a second tap circuit using a second reference voltage. 15 . The method of claim 14 , further comprising generating the first reference voltage and the second reference voltage by one or more reference voltage generating circuits.

16. The method according to claim 14 further includes generating, by a tap voltage generating circuit, a first tap voltage for controlling a first tap switch of the first tap circuit of the first data detector circuit and a second tap voltage for controlling a second tap switch of the first tap circuit of the first data detector circuit. The method of claim 14 , wherein the first reference voltage is different from the second reference voltage.

18. The method of claim 14, wherein the first reference voltage and the second reference voltage offset an offset between the first data detector circuit and the second data detector circuit.

19. The method according to claim 14 further includes generating, by a tap voltage generating circuit, a first tap voltage for controlling a first tap switch of the first tap circuit of the first data detector circuit and a second tap voltage for controlling a second tap switch of the first tap circuit of the first data detector circuit.

20. The method of claim 19, wherein the tap voltage generating circuit is arranged in parallel with a first path corresponding to the data signal.

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