659 bus input board test method based on boundary scan

Abstract

The invention relates to the technical field of airborne equipment internal circuit testing, in particular to a 659 bus input board testing method based on boundary scan, which comprises the following steps: step 1, designing a 659 bus main control board and a testing resource board, and designing a time sequence and control logic and an industrial personal computer testing control program; step 2, connecting the 659 bus main control board, the test resource board and the boundary scan controller with the industrial personal computer, and respectively connecting the 659 bus main control board, the test resource board and the boundary scan controller with the tested board; step 3, performing a 659 bus test; 4, carrying out input acquisition testing, wherein the input acquisition testing comprises AD conversion testing and discrete input testing; and step 5, performing a self-checking mode function test. According to the 659 bus input board fault positioning method, rapid fault positioning of the 659 bus input board can be achieved, waste in the production process is reduced to a great extent, resources are saved, and cost is reduced; the structure is simple, the work is reliable, and the applicability is strong; and the test and maintenance capability of aviation airborne products is improved.

Description

Technical Field

[0001] The invention relates to the technical field of internal circuit testing of airborne equipment, in particular to a 659 bus input board testing method based on boundary scanning. Background Art

[0002] With the increasing integration and modularization of new aircraft's onboard systems, a large number of high-reliability backplane buses are used within the products for communication between modules. As a new backplane bus in new aircraft, Arinc659 bus is used in new aircraft products. Due to its high transmission rate and strong error correction capability, it is currently also widely used in airborne products.

[0003] At present, airborne equipment is becoming more and more complex and integrated in terms of functions, and the maintenance costs are also increasing. Since each airborne module is the basic component unit of electronic products, its functions are complex, its usage characteristics vary, and its failure mode uncertainty is high. The outstanding problem is that the performance intervention test diagnosis method is difficult to quickly and accurately test the module performance and diagnose module failures. Analog signals cannot be completely replaced by digital signals in electronic circuits. The mixed signal technology of digital circuits and analog circuits is also developing rapidly and being widely used. According to the statistics of module failures, the failure rate of analog circuits is relatively high.

[0004] The architecture of the Arinc659 bus board is complex, which is typical of 659 bus boards. It includes multiple analog inputs, multiple discrete inputs, Arinc659 backplane bus, Actel encrypted FPGA (APA600), no FPGA control logic, various internal self-tests, HK659 does not support boundary scan, etc., and cannot be tested based on a single technology.

[0005] Based on the above reasons, the present invention proposes a 659 bus input board testing method based on boundary scan, which can be separated from the entire airborne device and tested independently. Summary of the invention

[0006] In order to solve the above technical problems, the present invention proposes a 659 bus input board testing method based on boundary scan. Based on the boundary scan test technology, by designing a basic 659 bus main control board, designing related hardware resource circuits and software programs, the input board will be self-tested and tested. The present invention is suitable for fault location and performance detection of functional board circuits based on boundary scan test technology and Arinc659 backplane bus, which can effectively reduce costs and is simple to operate.

[0007] The technical problem to be solved by the present invention is achieved by adopting the following technical solutions:

[0008] A 659 bus input board testing method based on boundary scanning comprises the following steps:

[0009] Step 1: Design the 659 bus main control board and test resource board, design the timing and control logic and industrial computer test control program;

[0010] Step 2: Connect the 659 bus main control board, the test resource board, and the boundary scan controller to the industrial computer, and connect the 659 bus main control board, the test resource board, and the boundary scan controller to the board under test respectively;

[0011] Step 3: After power-on, keep the boundary scan controller in the default state, the FPGA in the board under test works normally, the industrial computer communicates with the 659 bus main control board through Ethernet, and performs 659 bus testing;

[0012] Step 4: The industrial computer communicates with the test resource board via USB, and the analog signal and the connection channel to be sent on the program-controlled test resource board are sent to the input port of the board under test, and the output self-test voltage is set to 0V to perform input acquisition test, which includes AD conversion test and discrete input test;

[0013] Step 5: The industrial computer communicates with the test resource board via USB, programs the analog signals of all channels to be 0V, sets the self-test output voltage to a fixed value, and sends it to the self-test voltage input port of the board under test to perform a self-test mode function test.

[0014] As a further improvement of the present invention, the 659 bus main control board described in step 1 is based on a GJB289BRM controller, has a built-in SOC chip, a PCI bus master, and runs a VXWORKS operating system.

[0015] As a further improvement of the present invention, the test resource board described in step one is based on an STM32F407 controller, and the STM32F407 controls the FPGA chip to process data.

[0016] As a further improvement of the present invention, the timing and control logic described in step one includes an internal control program of a test resource board STM32F407 controller, a test resource board FPGA control logic, and a 659 bus main control board program.

[0017] As a further improvement of the present invention, the 659 bus test in step 3 is specifically as follows:

[0018] Step 1: Under the control of the industrial computer, the 659 bus main control board is connected to the 659 bus of the board under test;

[0019] Step 2: Read register data, determine the working status of the 659 bus, and implement tests such as the HK659 bus controller and transceiver.

[0020] As a further improvement of the present invention, the AD conversion test in step 4 is specifically as follows:

[0021] Step 1: Call the boundary scan controller to use FPGA to select the analog channel to be tested;

[0022] Step 2: Call the boundary scan controller to use FPGA to start AD conversion control, read the output data of AD conversion after delay and analyze the results;

[0023] Step 3: Complete the test of 32 AD conversion channels in sequence according to the above test method.

[0024] As a further improvement of the present invention, the discrete input test in step 4 is specifically as follows:

[0025] Step 1: The industrial computer controls the discrete quantity and connection channel to be sent by the test resource board and sends them to the input port of the board under test;

[0026] Step 2: Use FPGA to control the self-test control to be turned off by calling the boundary scan controller, and use FPGA to select the discrete input channels to be tested. There are six groups of discrete input channels, each with 16 discrete input channels.

[0027] Step 3: Then call the boundary scan controller to read the digital signal of the corresponding port and analyze the result;

[0028] Step 4: Follow the above test steps to complete the test of six groups of 96 discrete inputs in total.

[0029] As a further improvement of the present invention, the self-checking mode function test in step 5 is specifically as follows:

[0030] Step 1: Use FPGA to select any channel of analog quantity group A to be tested by calling the boundary scan controller;

[0031] Step 2: Then call the boundary scan controller to use FPGA to start AD conversion control, read the output data of AD conversion after delay and analyze the results;

[0032] Step 3: Complete the test of the AD conversion channel of group B according to the above test method and analyze the results;

[0033] Step 4: The industrial computer controls all the output discrete quantities of the test resource board to be disconnected;

[0034] Step 5: Then call the boundary scan controller to use FPGA to control the self-test control to the start state, and use FPGA to select the discrete input channels to be tested, 16 at a time;

[0035] Step 6: Then call the boundary scan controller to read the six groups of discrete input digital signals in sequence and analyze the results.

[0036] The beneficial effects of the present invention are:

[0037] The present invention provides a 659 bus input board testing method based on boundary scanning, which can realize rapid fault location of 659 bus input board components, greatly reducing waste in the production process, saving resources and reducing costs; and has simple structure, reliable operation, strong applicability and good practicality; it also reduces the workload of personnel and improves the testing and maintenance capabilities of aviation airborne products. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention is further described below in conjunction with the accompanying drawings and embodiments:

[0039] Figure 1 This is a schematic diagram of the connection of the test equipment during the test of the present invention;

[0040] In the figure: 1. Industrial computer; 2. 659 bus main control board; 3. Test resource board; 4. Boundary scan controller; 5. Board under test. DETAILED DESCRIPTION

[0041] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below with reference to the accompanying drawings and embodiments.

[0042] A 659 bus input board testing method based on boundary scanning comprises the following steps:

[0043] Step 1: Design the 659 bus main control board 2 and the test resource board 3, design the timing and control logic and the industrial computer test control program.

[0044] The 659 bus main control board 2 is based on the GJB289BRM controller, has a built-in SOC chip, a PCI bus master, runs the VXWORKS operating system, and communicates with an external industrial computer based on Ethernet. The GJB289BRM interacts with the HK659 chip through the PCI bus, controls the 659 backplane bus, and provides the 659 backplane bus control for the board under test.

[0045] The test resource board 3 is based on the STM32F407 controller and communicates with the industrial computer based on USB2.0. The STM32F407 controls the FPGA chip to process data, and uses an optical coupler to realize 84 low-open outputs and 12 27V open outputs; uses a DA converter and an analog switch to realize 36 analog outputs, and uses 74LS245 to realize 16 digital IO and other test resources. At the same time, the test resources are connected to the tested 659 bus input board and the 659 backplane bus control mainboard connection socket (only providing the transmission channel of the 659 backplane bus, without level processing) through a connector. It is used to provide each input signal of the tested board.

[0046] The timing and control logic mainly include:

[0047] Test resource board STM32F407 controller internal control program: analyze and test industrial computer USB control commands, data exchange with FPGA, USB interface driver, DA conversion and channel switching, etc.

[0048] Test resource board FPGA control logic: interface with STM32F407 controller, data exchange, control output relays, optocoupler output, digital IO, etc.

[0049] 659 backplane bus control motherboard program: This program runs based on the VxWorks operating system, including Ethernet driver, PCI driver, HK659 driver, backplane bus control, Ethernet command processing, etc.

[0050] The industrial computer test control program mainly controls data communication between the main board and the test resource board with the 659 backplane bus and realizes program control, calls the boundary scan controller API interface control program to control the FPGA of the board under test, and forms the entire automated test program according to the test method.

[0051] Step 2: Connect the 659 bus main control board 2, the test resource board 3, and the boundary scan controller 4 to the industrial computer 1, and connect the 659 bus main control board 2, the test resource board 3, and the boundary scan controller 4 to the board under test 5 respectively. Figure 1 As shown, the industrial computer 1 is used as the core control unit. The industrial computer 1 communicates with the 659 bus main control board 2 through the host computer software; controls the boundary scan controller 4; and connects and program-controls the test resource board 3. At the same time, the industrial computer 1 comprehensively controls and collects various types of data, collects test results, and generates test reports.

[0052] The boundary scan controller 4 controls the FPGA chip of the main control board based on the IEEE1149.1 protocol, and controls the analog quantity part based on the internal resources of the board under test 5. The boundary scan controller 4 communicates with the industrial computer 1 based on USB2.0.

[0053] Step 3: After power-on, keep the boundary scan controller 4 in the default state, the FPGA in the tested board 5 works normally, the industrial computer 1 communicates with the 659 bus main control board 2 through Ethernet to perform 659 bus testing; under the control of the industrial computer 1, the 659 bus main control board 2 is connected to the 659 bus of the tested board 5; read the register data, determine the working status of the 659 bus, and implement tests such as the HK659 bus controller and transceiver.

[0054] Step 4: The industrial computer 1 communicates with the test resource board 3 via USB, and the analog signal and the connection channel to be sent on the program-controlled test resource board 3 are sent to the input port of the board under test 5, and the output self-test voltage is set to 0V to perform input acquisition test, which includes AD conversion test and discrete input test;

[0055] AD conversion test;

[0056] Call the boundary scan controller 4 to use FPGA to select the analog channel to be tested; call the boundary scan controller 4 to use FPGA to start AD conversion control, read the output data of AD conversion after delay and analyze the result; complete the test of 32 AD conversion channels in sequence according to the above test method.

[0057] Discrete input testing;

[0058] The industrial computer 1 controls the discrete quantity and connection channel to be sent by the test resource board 3, and sends them to the input port of the board under test 5; then the boundary scan controller 4 is called to use the FPGA to control the self-test control to be closed, and the discrete input channel to be tested is selected by the FPGA. There are six groups of discrete input channels, each with 16 discrete input channels; then the boundary scan controller 4 is called to read the digital signal of the corresponding port and analyze the result; according to the above test steps, the test of six groups of 96 discrete inputs is completed in sequence.

[0059] Step 5: The industrial computer 1 communicates with the test resource board 3 via USB, and the analog signals of all channels are programmed to be 0V, and the self-test output voltage is set to a fixed value, and sent to the self-test voltage input port of the board 5 under test to perform a self-test function test. By calling the boundary scan controller 4, use FPGA to select any channel of the analog quantity group A to be tested; then call the boundary scan controller 4 to use FPGA to start AD conversion control, read the output data of AD conversion after a delay and analyze the results; complete the test of the AD conversion channel of group B and analyze the results according to the above test method.

[0060] The industrial computer 1 controls all the output discrete quantities of the test resource board 3 to be disconnected; then the boundary scan controller 4 is called to use the FPGA to control the self-test control to be started, and the FPGA is used to select the discrete input channels to be tested, 16 at a time; then the boundary scan controller 4 is called to read the digital signals of the six groups of discrete inputs in turn, and the results are analyzed.

[0061] Integrate the control instructions of the 659 backplane bus control motherboard, the boundary scan API interface and the program control method of the test resource board to form an automatic test program to achieve fully automatic testing of the 659 bus input board.

[0062] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A 659 bus input board testing method based on boundary scan, characterized in that: The following steps are involved: Step 1: Design the 659 bus main control board (2) and the test resource board (3), design the timing and control logic and the industrial computer test control program; Step 2: Connect the 659 bus main control board (2), the test resource board (3), and the boundary scan controller (4) to the industrial computer (1), and connect the 659 bus main control board (2), the test resource board (3), and the boundary scan controller (4) to the board under test (5) respectively; Step 3: After power-on, keep the boundary scan controller (4) in the default state, the FPGA in the tested board (5) works normally, the industrial computer (1) communicates with the 659 bus main control board (2) via Ethernet, and performs a 659 bus test; Step 4: The industrial computer (1) communicates with the test resource board (3) via USB, and the analog signal and the connection channel to be sent on the program-controlled test resource board (3) are sent to the input port of the board under test (5), and the output self-test voltage is set to 0V to perform an input acquisition test, which includes an AD conversion test and a discrete input test; Step 5: The industrial computer (1) communicates with the test resource board (3) via USB, programs the analog signals of all channels to be 0V, and sets the self-test output voltage to a fixed value, which is sent to the self-test voltage input port of the board under test (5) to perform a self-test mode function test.

2. A 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The 659 bus main control board (2) described in step 1 is based on a GJB289BRM controller, has a built-in SOC chip, a PCI bus master, and runs a VXWORKS operating system.

3. A 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The test resource board (3) described in step 1 is based on an STM32F407 controller, and the STM32F407 controls the FPGA chip to process data.

4. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The timing and control logic described in step 1 include the internal control program of the test resource board STM32F407 controller, the test resource board FPGA control logic, and the 659 bus main control board program.

5. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The 659 bus test in step 3 is as follows: Step 1: Under the control of the industrial computer (1), the 659 bus main control board (2) is connected to the 659 bus of the board under test (5); Step 2: Read register data, determine the working status of the 659 bus, and implement tests such as the HK659 bus controller and transceiver.

6. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The AD conversion test in step 4 is as follows: Step 1: Call the boundary scan controller (4) to use the FPGA to select the analog channel to be tested; Step 2: Call the boundary scan controller (4) to start AD conversion control using FPGA, read the output data of AD conversion after a delay and analyze the result; Step 3: Complete the test of 32 AD conversion channels in sequence according to the above test method.

7. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The discrete input test in step 4 is as follows: Step 1: The industrial computer (1) controls the discrete quantity and the connection channel to be sent by the test resource board (3) and sends them to the input port of the board under test (5); Step 2: By calling the boundary scan controller (4), the FPGA is used to control the self-test control to be turned off, and the FPGA is used to select the discrete input channels to be tested. There are six groups of discrete input channels, each with 16 discrete input channels. Step 3: Then call the boundary scan controller (4) to read the digital signal of the corresponding port and analyze the result; Step 4: Follow the above test steps to complete the test of six groups of 96 discrete inputs in total.

8. The 659 bus input board testing method based on boundary scan according to claim 1, characterized in that: The self-check function test in step 5 is as follows: Step 1: Use FPGA to select any channel of analog quantity group A to be tested by calling boundary scan controller (4); Step 2: Then call the boundary scan controller (4) to start AD conversion control using FPGA, read the output data of AD conversion after delay and analyze the result; Step 3: Complete the test of the AD conversion channel of group B according to the above test method and analyze the results; Step 4: The industrial computer (1) controls the test resource board (3) to disconnect all output discrete quantities; Step 5: Then, by calling the boundary scan controller (4), the FPGA is used to control the self-test control to the start state, and the FPGA is used to select the discrete input channels to be tested, 16 at a time; Step 6: Then call the boundary scan controller (4) to read the six groups of discrete input digital signals in sequence and analyze the results.

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