Multi-core processor event monitoring method and device, equipment, storage medium and product

Abstract

The invention provides a multi-core processor event monitoring method and device, equipment, a storage medium and a product. Performance data collected by a PMU of each core are synchronously received through a PMU unified management interface; wherein the performance data comprises an event count and an event type corresponding to each performance event to be monitored; according to the event type of each to-be-monitored performance event, summarizing and analyzing performance data collected by the PMU of each core, and calculating the sum of event counts of each event type in different cores and the minimum event count value and the maximum event count value corresponding to each event type; and performing performance evaluation and system optimization on the multi-core processor system according to the sum of the event counts of each event type in different cores and the event count minimum value and the event count maximum value corresponding to each event type. According to the scheme, the accuracy and efficiency of performance analysis and optimization of the multi-core processor system are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a multi-core processor event monitoring method, device, equipment, storage medium and product. Background Art

[0002] The Performance Monitoring Unit (PMU) is a hardware component in the Central Processing Unit (CPU) that is used to track and count low-level hardware events in the system. It is integrated into ARM architecture processors and is used to monitor and measure key indicators of processor and system performance.

[0003] A multi-core processor is a microprocessor that integrates two or more independent processing cores that can perform computing tasks in parallel. Multi-core technology is a way to improve computing performance and efficiency. It enables multiple threads or processes to be executed on different cores at the same time, thereby significantly improving the computing power and response speed of the processor.

[0004] In a multi-core processor system, each core is usually equipped with its own PMU to monitor the performance indicators of the core. However, the existing technology cannot coordinate and manage these scattered PMUs, resulting in the inability to accurately and efficiently perform system-level performance analysis and optimization. It can be seen that in the existing technology, the accuracy and efficiency of performance analysis and optimization of multi-core processor systems are poor. Summary of the invention

[0005] The present invention provides a multi-core processor event monitoring method, device, equipment, storage medium and product, which are used to solve the defects of poor accuracy and efficiency in performance analysis and optimization of multi-core processor systems in the prior art, and to achieve accurate and efficient system-level performance analysis and optimization.

[0006] The present invention provides a multi-core processor event monitoring method, comprising the following steps.

[0007] Synchronously receiving performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored; According to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type are calculated; Performance evaluation and system tuning of the multi-core processor system are performed based on the total event count of each event type in different cores and the minimum and maximum event counts corresponding to each event type.

[0008] According to a multi-core processor event monitoring method provided by the present invention, before synchronously receiving the performance data collected by the PMU of each core through the unified interface, the method further includes: Initializing the PMU unified management interface, where the PMU unified management interface is used to manage and coordinate the PMU interface of each core; Through the PMU unified management interface, configure the performance events to be monitored of the PMU of each core and the counters corresponding to each performance event to be monitored; The PMU of each core is started through the PMU unified management interface, so that the PMU of each core starts to collect the performance data.

[0009] According to a multi-core processor event monitoring method provided by the present invention, before synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the method further includes: Receive custom performance events sent by users; The custom performance event is defined as a performance event to be monitored through the PMU unified management interface, and a counter corresponding to the custom performance event is configured.

[0010] According to a multi-core processor event monitoring method provided by the present invention, after synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the method further includes: Compare the event counts of each event type in different cores to identify the load balancing status among the cores; According to the load balancing status among the cores, the load of each core is distributed to balance the load of each core.

[0011] According to a multi-core processor event monitoring method provided by the present invention, the method further includes: Through the PMU unified management interface, the following functions of the PMU of each core are configured: opening and closing events, pausing and resuming events, and overflow recording of events.

[0012] According to a multi-core processor event monitoring method provided by the present invention, the performance event to be monitored includes at least one of the following: a central processing unit event, a cache event, and an address translation backup buffer event.

[0013] The present invention also provides a multi-core processor event monitoring device, comprising the following modules.

[0014] A receiving module, used to synchronously receive performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored; A calculation module, used to summarize and analyze the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and calculate the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type; The processing module is used to perform performance evaluation and system tuning on the multi-core processor system according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type.

[0015] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, any of the multi-core processor event monitoring methods described above is implemented.

[0016] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the multi-core processor event monitoring method as described above is implemented.

[0017] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the multi-core processor event monitoring methods described above.

[0018] The multi-core processor event monitoring method, device, equipment, storage medium and product provided by the present invention synchronously receive the performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; according to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type are calculated; according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type, the multi-core processor system is subjected to performance evaluation and system tuning. The scheme of the present invention, on the one hand, provides a PMU unified management interface to uniformly receive the performance data collected by the PMU of each core, realizes the coordination and management of the PMU of each core, and can realize the cross-core performance monitoring capability. On the other hand, the received data is summarized and analyzed, and the overall performance evaluation and system tuning of the entire system can be accurately and efficiently performed. Therefore, the scheme of the present invention improves the accuracy and efficiency of performance analysis and optimization of the multi-core processor system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a flow chart of the multi-core processor event monitoring method provided by the present invention.

[0021] Figure 2 This is a diagram of the interaction between the PMU unified management interface and the single-core PMU provided by the present invention.

[0022] Figure 3 It is a structural schematic diagram of the multi-core processor event monitoring device provided by the present invention.

[0023] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The following specific embodiments are used to describe in detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The multi-core processor event monitoring method of the present invention is described below in conjunction with the accompanying drawings.

[0026] In practical applications, the execution subject of the multi-core processor event monitoring method can be a multi-core processor event monitoring device. There are many ways to implement the multi-core processor event monitoring device, for example, it can be implemented through a computer program, such as application software, etc.; or, for example, a chip, etc. It can also be implemented as a medium storing relevant computer programs, such as a USB disk, a cloud disk, etc.; or, it can also be implemented through a physical device integrated or installed with relevant computer programs, such as a server, etc.

[0027] Figure 1 is a flow chart of a multi-core processor event monitoring method provided by the present invention, such as Figure 1 As shown, the method includes the following: Step 101: synchronously receive performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored.

[0028] In this embodiment, the performance event to be monitored refers to the processor behavior that can be tracked and measured by the PMU or other monitoring tools. These events are helpful for performance analysis, system debugging and software optimization. In one example, the performance event to be monitored includes at least one of the following: a CPU event, a cache event, and an address translation lookaside buffer event.

[0029] As an example, a central processing unit (CPU) event refers to an event related to the CPU, such as the number of instructions executed, the number of exceptions caught, the number of clock cycles, etc. A cache event refers to an event related to the cache, for example, events related to the cache include the number of cache accesses, the number of misses, etc. Translation Lookaside Buffer (TBL) events include the number of TLB hits, the number of TLB misses, etc.

[0030] In this embodiment, a corresponding PMU is provided for each core in the multi-core processor. In actual applications, the PMU of each core independently collects performance data and stores the collected performance data in a storage data structure corresponding to each core.

[0031] The present invention not only ensures independent control of the PMU of each core, but also provides a PMU unified management interface, which greatly simplifies the performance monitoring configuration and management process of the multi-core processor. The design of the PMU unified management interface provides a centralized solution, so that the upper layer application can configure and control the PMU of all cores through a single entrance, without having to set up the PMU of each core one by one.

[0032] The solution of the present invention is used to coordinate the PMUs of each core in a multi-core processor to achieve more accurate and comprehensive performance monitoring. Specifically, Figure 2 This is a diagram of the interaction between the PMU unified management interface and the single-core PMU provided by the present invention, such as Figure 2 As shown, the PMU of each core is used to independently collect performance data, and the performance data is aggregated to a central node, i.e., a multi-core processor event monitoring device, through a unified PMU management interface for analysis. It can be understood that since the central node can synchronously aggregate PMU data from each core, the monitoring result is more accurate, reducing erroneous analysis caused by time inconsistency or data deviation, and improving the accuracy of monitoring.

[0033] It can be understood that the PMU of each core independently collects performance data, which is then centrally aggregated and analyzed through the central node. This mechanism not only ensures the decentralization of data collection to reduce the risk of single point failure, but also realizes the centralized processing of data for easy analysis and reporting.

[0034] In actual applications, the PMU unified management interface supports the selection of events to be monitored and the setting of counters. It can be understood that the PMU unified management interface ensures the consistency of event types and counter numbers recorded on all cores, which is crucial for cross-core performance analysis, avoids possible ambiguity during data comparison and integration, and improves the accuracy and reliability of multi-core processor event monitoring.

[0035] In this embodiment, the PMU unified management interface has a built-in synchronization mechanism to ensure that during the multi-core processor event monitoring process, the PMUs of all cores can start and end event recording at the same time, and synchronously send performance data to the multi-core processor event monitoring device through the PMU unified management interface, thereby avoiding monitoring errors caused by time inconsistencies and improving the accuracy and reliability of multi-core processor event monitoring.

[0036] Step 102: According to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and maximum event count corresponding to each event type are calculated.

[0037] In practical applications, the multi-core processor event monitoring device is a structure that sums the event counts recorded by each core and is responsible for processing and storing event data from all cores. The structure of the multi-core processor event monitoring device also includes the bit segments with the most and least counts of the same event type for each core. This structure not only stores the count information of the event, but may also contain metadata such as timestamps and event types, providing rich context information for subsequent data analysis.

[0038] Specifically, according to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores is calculated. For example, a multi-core processor includes core 1, core 2, core 3 and core 4, and the multi-core processor event monitoring device synchronously receives the performance data collected by core 1, core 2, core 3 and core 4 respectively through the PMU unified management interface. The event types to be monitored corresponding to each core include event A, event B and event C. For event A, the event count collected by the PMU of core 1 is 3, the event count collected by the PMU of core 2 is 5, the event count collected by the PMU of core 3 is 2, and the event count collected by the PMU of core 4 is 6. The total event count of event A in different cores is calculated to be 16.

[0039] Specifically, the minimum event count and the maximum event count corresponding to each event type are calculated. As an example, the event counts collected by different cores under each event type are summarized, and the minimum event count and the maximum event count corresponding to each event type are determined by comparison.

[0040] Step 103: Perform performance evaluation and system tuning on the multi-core processor system according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type.

[0041] It is understandable that the sum of event counts in different cores for each event type can evaluate the performance of the entire system, not just a single core. The sum of event counts can help understand the overall utilization of system resources (such as CPU, memory), thereby discovering where resources are wasted or underutilized. For example, comparing the total number of cache miss events with the total number of cache hit events, if the total number of cache miss events is high, it may indicate a performance bottleneck or anomaly in the cache system.

[0042] In real applications, if the sum of counts for a certain event type is abnormally high, it may indicate a performance bottleneck or anomaly. For example, a high number of cache misses may mean that you need to optimize data access patterns or increase cache capacity.

[0043] Specifically, performance bottlenecks or anomalies can be identified through the minimum event count and the maximum event count corresponding to each event type. As an example, the minimum event count indicates that the corresponding core or area is bearing the largest processing load. For example, if a core has the highest cache miss count, this may indicate that the core is facing a cache performance bottleneck or anomaly. Correspondingly, the minimum event count may indicate that some cores are not fully utilized or that their workload is much lower than other cores. As an example, by comparing the event counts of different cores, it is possible to evaluate whether the system is effectively balancing the load. If there is a significant difference between the maximum and minimum values, this may indicate that tasks need to be reallocated to achieve a more even load distribution.

[0044] Combined with the above description, the performance of the entire system and each core can be evaluated based on the total event count of each event type in different cores and the minimum and maximum event counts corresponding to each event type. Furthermore, based on the performance evaluation results, the system can be tuned, such as optimizing code, adjusting task scheduling, optimizing resource utilization, balancing the load of each core, etc.

[0045] In actual applications, the monitoring time can be pre-configured. During the monitoring time, the system performance is continuously monitored to ensure continuous performance optimization and reasonable allocation of resources.

[0046] In the solution of this embodiment, on the one hand, a PMU unified management interface is provided to uniformly receive the performance data collected by the PMU of each core, so as to coordinate and manage the PMU of each core and realize the cross-core performance monitoring capability. On the other hand, the received data is summarized and analyzed, so as to accurately and efficiently comprehensively evaluate the performance of the entire system and optimize the system. Therefore, the solution of this embodiment improves the accuracy and efficiency of the performance analysis and optimization of the multi-core processor system.

[0047] In addition, for the configuration process of the PMU of each core, in a possible implementation manner, before step 101, the multi-core processor event monitoring method further includes: Initialize the PMU unified management interface, which is used to manage and coordinate the PMU interface of each core; Through the PMU unified management interface, configure the performance events to be monitored for each core's PMU and the counters corresponding to each performance event to be monitored; Start the PMU of each core through the PMU unified management interface so that the PMU of each core starts to collect performance data.

[0048] In practical applications, in multi-core processor systems, initializing the PMU unified management interface during the system deployment phase is a key step. This step involves configuring and preparing the PMU to facilitate monitoring of processor performance. As an example, initializing the PMU unified management interface includes: detecting whether the PMU hardware of each core is available, configuring the PMU resources of each core, setting the operating mode of the PMU, such as enabling or disabling certain specific monitoring functions, setting synchronization mechanisms, user permissions and security settings, testing and verification, etc.

[0049] Furthermore, the performance events to be monitored of the PMU of each core and the counters corresponding to each performance event to be monitored are configured through the PMU unified management interface. Specifically, the performance events to be monitored of the PMU of each core are defined using the configuration command line tool, such as CPU cycles, number of instruction executions, cache hit rate, etc., and counters are set for the PMU of each core to record the number of occurrences of different performance events to be monitored.

[0050] Further, the PMU of each core is started through the PMU unified management interface so that the PMU of each core starts to collect performance data. Specifically, the PMU of each core independently collects performance data and records the collected performance data into respective structures.

[0051] In actual applications, at a predetermined time interval or when a specific event is triggered, the PMUs of all cores will synchronously send the collected performance data to the multi-core processor event monitoring device through the PMU unified management interface. Furthermore, the multi-core processor event monitoring device summarizes and analyzes the received performance data to perform performance evaluation and system tuning on the multi-core processor system.

[0052] In this implementation, unified configuration of PMUs of multiple cores is achieved through a unified PMU management interface, which simplifies the configuration and monitoring process, enables rapid deployment of monitoring configurations to all cores, and improves operational efficiency.

[0053] As an example, in a multi-core processor system, in addition to event selection and counter configuration for each core through the PMU unified management interface, the configuration of each core may also include: monitoring mode definition, such as whether to enable real-time monitoring, whether to record event timestamps, etc.; resources and permissions, such as configuring necessary resources and permissions according to the operating system and security policies to allow monitoring tools to access the PMU; synchronization mechanisms, such as configuring synchronization mechanisms to ensure that monitoring events for all cores start and end at the same time; data collection and reporting, such as configuring the method and frequency of data collection, and how to generate and format performance reports; performance tuning parameters, for example, depending on the performance monitoring objectives, specific tuning parameters may need to be configured, such as adjusting core frequency, optimizing cache usage, etc.; exception and interrupt handling, for example, configuring how to handle exceptions and interrupts related to performance monitoring, such as cache errors, memory access violations, etc.

[0054] In practical applications, the PMU unified management interface not only supports basic monitoring event selection and counter setting, but also retains the same functional interface in the single-core PMU. As an example, in a possible implementation, the multi-core processor event monitoring method further includes: Through the PMU unified management interface, configure the following functions of each core's PMU: event opening and closing, event pause and resume, and event overflow recording.

[0055] Regarding the opening and closing of events, specifically, users can dynamically open or close specific performance event monitoring through the interface as needed, so that the monitoring process can be customized for specific performance issues. Users can freely select the number of events supported and counters supported by the hardware. Users can open or close the event recording of a single-core PMU by entering a command line.

[0056] Regarding the pause and resume of events, specifically, during the monitoring process, if you need to temporarily interrupt monitoring for system debugging or other operations, you can pause event collection through the interface, and then you can seamlessly continue data collection to ensure the continuity and integrity of monitoring. Users can pause or resume event recording of a single-core PMU by entering a command line.

[0057] For overflow records, specifically, when the performance counter reaches its maximum value, an interrupt will occur in the PMU hardware. Each core PMU will send a print of the PMU entering the interrupt, count an overflow in the structure of each core counting event, clear the counter, clear the interrupt, and continue counting. This helps avoid the loss of critical data when high-frequency events occur, and also ensures the reliability of long-term counting.

[0058] In actual applications, users can define event types and counters, turn on and off, pause and continue counting by configuring command line tools. This provides a fast and flexible way to set monitoring parameters, allowing users to easily adjust monitoring strategies as needed.

[0059] In addition, in a possible implementation manner, before the above step 101, the above multi-core processor event monitoring method further includes: Receive custom performance events sent by users; Define custom performance events as performance events to be monitored through the PMU unified management interface, and configure counters corresponding to the custom performance events.

[0060] The present invention supports user-defined performance events to be monitored. Users can define specific performance events to be monitored according to their own performance analysis requirements. The PMU will track and record these customized performance events to be monitored, thereby providing a more personalized performance monitoring service and improving the flexibility and practicality of multi-core processor event monitoring.

[0061] In addition, in a possible implementation manner, after the above step 101, the above multi-core processor event monitoring method further includes: Compare the event counts of each event type in different cores to identify the load balancing status among the cores; According to the load balancing status among the cores, the load of each core is distributed to balance the load of each core.

[0062] In practice, comparing the event counts of different cores can reveal performance differences between cores, which may be caused by uneven task distribution or hardware differences between cores. If the event counts of some cores are much higher than other cores, tasks may need to be redistributed to achieve a more balanced load.

[0063] In this implementation, after synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the event counts of each event type in different cores are compared, the load balancing status between the cores is identified, and the load of each core is distributed according to the load balancing status between the cores. This can avoid the situation where some cores are overloaded while other cores are idle. The system can achieve a more balanced load distribution, thereby improving overall performance and efficiency, and improving the reliability of the multi-core processor system.

[0064] The multi-core processor event monitoring method provided in this embodiment synchronously receives the performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; according to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type are calculated; according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type, the multi-core processor system is subjected to performance evaluation and system tuning. The scheme of this embodiment, on the one hand, provides a PMU unified management interface to uniformly receive the performance data collected by the PMU of each core, realizes the coordination and management of the PMU of each core, and can realize the cross-core performance monitoring capability. On the other hand, the received data is summarized and analyzed, which can accurately and efficiently comprehensively evaluate the performance of the entire system and optimize the system. Therefore, the scheme of this embodiment improves the accuracy and efficiency of performance analysis and optimization of the multi-core processor system.

[0065] The multi-core processor event monitoring device provided by the present invention is described below. The multi-core processor event monitoring device described below and the multi-core processor event monitoring method described above can be referenced to each other.

[0066] Figure 3 Schematic diagram of the structure of the multi-core processor event monitoring device provided by the present invention. Figure 3 As shown, the multi-core processor event monitoring device includes: a receiving module 31, a calculating module 32 and a processing module 33.

[0067] The receiving module 31 is used to synchronously receive the performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored.

[0068] In this embodiment, the performance event to be monitored refers to the processor behavior that can be tracked and measured by the PMU or other monitoring tools. These events are helpful for performance analysis, system debugging and software optimization. In one example, the performance event to be monitored includes at least one of the following: a CPU event, a cache event, and an address translation lookaside buffer event.

[0069] As an example, a central processing unit (CPU) event refers to an event related to the CPU, such as the number of instructions executed, the number of exceptions caught, the number of clock cycles, etc. A cache event refers to an event related to the cache, for example, events related to the cache include the number of cache accesses, the number of misses, etc. Translation Lookaside Buffer (TBL) events include the number of TLB hits, the number of TLB misses, etc.

[0070] In this embodiment, a corresponding PMU is provided for each core in the multi-core processor. In actual applications, the PMU of each core independently collects performance data and stores the collected performance data in a storage data structure corresponding to each core.

[0071] The present invention not only ensures independent control of the PMU of each core, but also provides a PMU unified management interface, which greatly simplifies the performance monitoring configuration and management process of the multi-core processor. The design of the PMU unified management interface provides a centralized solution, so that the upper layer application can configure and control the PMU of all cores through a single entrance, without having to set up the PMU of each core one by one.

[0072] The solution of the present invention is used to coordinate the PMUs of each core in a multi-core processor to achieve more accurate and comprehensive performance monitoring. Specifically, Figure 2 As shown, the PMU of each core is used to independently collect performance data, and the performance data is aggregated to a central node, i.e., a multi-core processor event monitoring device, through a unified PMU management interface for analysis. It can be understood that since the central node can synchronously aggregate PMU data from each core, the monitoring result is more accurate, reducing erroneous analysis caused by time inconsistency or data deviation, and improving the accuracy of monitoring.

[0073] It can be understood that the PMU of each core independently collects performance data, which is then centrally aggregated and analyzed through the central node. This mechanism not only ensures the decentralization of data collection to reduce the risk of single point failure, but also realizes the centralized processing of data for easy analysis and reporting.

[0074] In actual applications, the PMU unified management interface supports the selection of events to be monitored and the setting of counters. It can be understood that the PMU unified management interface ensures the consistency of event types and counter numbers recorded on all cores, which is crucial for cross-core performance analysis, avoids possible ambiguity during data comparison and integration, and improves the accuracy and reliability of multi-core processor event monitoring.

[0075] In this embodiment, the PMU unified management interface has a built-in synchronization mechanism to ensure that during the multi-core processor event monitoring process, the PMUs of all cores can start and end event recording at the same time, and synchronously send performance data to the multi-core processor event monitoring device through the PMU unified management interface, thereby avoiding monitoring errors caused by time inconsistencies and improving the accuracy and reliability of multi-core processor event monitoring.

[0076] The above-mentioned calculation module 32 is used to summarize and analyze the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and calculate the total event count of each event type in different cores and the minimum event count and maximum event count corresponding to each event type.

[0077] In practical applications, the multi-core processor event monitoring device is a structure that sums the event counts recorded by each core and is responsible for processing and storing event data from all cores. The structure of the multi-core processor event monitoring device also includes the bit segments with the most and least counts of the same event type for each core. This structure not only stores the count information of the event, but may also contain metadata such as timestamps and event types, providing rich context information for subsequent data analysis.

[0078] Specifically, the calculation module 32 summarizes and analyzes the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and calculates the total event count of each event type in different cores.

[0079] Specifically, the calculation module 32 calculates the minimum and maximum event counts corresponding to each event type. As an example, the event counts collected by different cores under each event type are summarized, and the minimum and maximum event counts corresponding to each event type are determined by comparison.

[0080] The processing module 33 is used to perform performance evaluation and system tuning on the multi-core processor system according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type.

[0081] It is understandable that the processing module 33 can evaluate the performance of the entire system, not just a single core, based on the sum of event counts of each event type in different cores. The sum of event counts can help understand the overall utilization of system resources (such as CPU, memory), thereby discovering where resources are wasted or underutilized. For example, the total number of cache miss events is compared with the total number of cache hit events. If the total number of cache miss events is high, it may indicate that there is a performance bottleneck or abnormality in the cache system.

[0082] In real applications, if the sum of counts for a certain event type is abnormally high, it may indicate a performance bottleneck or anomaly. For example, a high number of cache misses may mean that you need to optimize data access patterns or increase cache capacity.

[0083] Specifically, the processing module 33 can identify performance bottlenecks or abnormal situations through the minimum event count and the maximum event count corresponding to each event type. As an example, the minimum event count indicates that the corresponding core or area is bearing the largest processing load. For example, if a core has the highest cache miss count, this may indicate that the core is facing a cache performance bottleneck or abnormal situation. Correspondingly, the minimum event count may indicate that some cores are not fully utilized, or that their workload is much lower than other cores. As an example, the processing module 33 can evaluate whether the system has effectively balanced the load by comparing the event counts of different cores. If there is a significant difference between the maximum and minimum values, this may indicate that tasks need to be reallocated to achieve a more even load distribution.

[0084] In combination with the above description, the processing module 33 can evaluate the performance of the entire system and each core according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type. Further, the processing module 33 can tune the system according to the performance evaluation results, such as optimizing code, adjusting task scheduling, optimizing resource utilization, balancing the load of each core, etc.

[0085] In actual applications, the monitoring time can be pre-configured. During the monitoring time, the system performance is continuously monitored to ensure continuous performance optimization and reasonable allocation of resources.

[0086] In the solution of this embodiment, on the one hand, a PMU unified management interface is provided to uniformly receive the performance data collected by the PMU of each core, so as to coordinate and manage the PMU of each core and realize the cross-core performance monitoring capability. On the other hand, the received data is summarized and analyzed, so as to accurately and efficiently comprehensively evaluate the performance of the entire system and optimize the system. Therefore, the solution of this embodiment improves the accuracy and efficiency of the performance analysis and optimization of the multi-core processor system.

[0087] In addition, for the configuration process of the PMU of each core, in a possible implementation manner, the multi-core processor event monitoring device further includes: An initialization module is used to initialize the PMU unified management interface, which is used to manage and coordinate the PMU interface of each core; A configuration module, used to configure the performance events to be monitored of the PMU of each core and the counters corresponding to each performance event to be monitored through the PMU unified management interface; The startup module is used to start the PMU of each core through the PMU unified management interface, so that the PMU of each core starts to collect performance data.

[0088] In practical applications, in multi-core processor systems, initializing the PMU unified management interface during the system deployment phase is a key step. This step involves configuring and preparing the PMU to facilitate monitoring of processor performance. As an example, initializing the PMU unified management interface includes: detecting whether the PMU hardware of each core is available, configuring the PMU resources of each core, setting the operating mode of the PMU, such as enabling or disabling certain specific monitoring functions, setting synchronization mechanisms, user permissions and security settings, testing and verification, etc.

[0089] Furthermore, the configuration module configures the performance events to be monitored of the PMU of each core and the counters corresponding to each performance event to be monitored through the PMU unified management interface. Specifically, the configuration command line tool is used to define the performance events to be monitored of the PMU of each core, such as CPU cycles, number of instruction executions, cache hit rate, etc., and a counter is set for the PMU of each core to record the number of occurrences of different performance events to be monitored.

[0090] Furthermore, the startup module starts the PMU of each core through the PMU unified management interface, so that the PMU of each core starts to collect performance data. Specifically, the PMU of each core independently collects performance data and records the collected performance data into respective structures.

[0091] In actual applications, at a predetermined time interval or when a specific event is triggered, the PMUs of all cores will synchronously send the collected performance data to the multi-core processor event monitoring device through the PMU unified management interface. Furthermore, the multi-core processor event monitoring device summarizes and analyzes the received performance data to perform performance evaluation and system tuning on the multi-core processor system.

[0092] In this implementation, unified configuration of PMUs of multiple cores is achieved through a unified PMU management interface, which simplifies the configuration and monitoring process, enables rapid deployment of monitoring configurations to all cores, and improves operational efficiency.

[0093] As an example, in a multi-core processor system, the configuration module is also used for: monitoring mode definition, such as whether to enable real-time monitoring, whether to record event timestamps, etc.; resources and permissions, such as configuring necessary resources and permissions according to the operating system and security policies to allow monitoring tools to access the PMU; synchronization mechanism, such as configuring the synchronization mechanism to ensure that monitoring events of all cores start and end at the same time; data collection and reporting, such as configuring the method and frequency of data collection, and how to generate and format performance reports; performance tuning parameters, for example, depending on the performance monitoring objectives, specific tuning parameters may need to be configured, such as adjusting core frequency, optimizing cache usage, etc.; exception and interrupt handling, for example, configuring how to handle exceptions and interrupts related to performance monitoring, such as cache errors, memory access violations, etc.

[0094] In practical applications, the PMU unified management interface not only supports basic monitoring event selection and counter setting, but also retains the same functional interface in the single-core PMU. As an example, in one possible implementation, the above configuration module is also used to: Through the PMU unified management interface, configure the following functions of each core's PMU: event opening and closing, event pause and resume, and event overflow recording.

[0095] Regarding the opening and closing of events, specifically, users can dynamically open or close specific performance event monitoring through the interface as needed, so that the monitoring process can be customized for specific performance issues. Users can freely select the number of events supported and counters supported by the hardware. Users can open or close the event recording of a single-core PMU by entering a command line.

[0096] Regarding the pause and resume of events, specifically, during the monitoring process, if you need to temporarily interrupt monitoring for system debugging or other operations, you can pause event collection through the interface, and then you can seamlessly continue data collection to ensure the continuity and integrity of monitoring. Users can pause or resume event recording of a single-core PMU by entering a command line.

[0097] For overflow records, specifically, when the performance counter reaches its maximum value, an interrupt will occur in the PMU hardware. Each core PMU will send a print of the PMU entering the interrupt, count an overflow in the structure of each core counting event, clear the counter, clear the interrupt, and continue counting. This helps avoid the loss of critical data when high-frequency events occur, and also ensures the reliability of long-term counting.

[0098] In actual applications, users can define event types and counters, turn on and off, pause and continue counting by configuring command line tools. This provides a fast and flexible way to set monitoring parameters, allowing users to easily adjust monitoring strategies as needed.

[0099] In addition, in a possible implementation manner, the multi-core processor event monitoring device further includes: a custom module.

[0100] Custom module, used to receive custom performance events sent by users; The custom module is also used to define custom performance events as performance events to be monitored through the PMU unified management interface, and configure counters corresponding to the custom performance events.

[0101] The present invention supports user-defined performance events to be monitored. Users can define specific performance events to be monitored according to their own performance analysis requirements. The PMU will track and record these customized performance events to be monitored, thereby providing a more personalized performance monitoring service and improving the flexibility and practicality of multi-core processor event monitoring.

[0102] In addition, in a possible implementation manner, the multi-core processor event monitoring device further includes: A comparison module, used to compare the event counts of each event type in different cores and identify the load balancing status among the cores; The load balancing module is used to distribute the load of each core according to the load balancing status among the cores to balance the load of each core.

[0103] In practice, comparing the event counts of different cores can reveal performance differences between cores, which may be caused by uneven task distribution or hardware differences between cores. If the event counts of some cores are much higher than other cores, tasks may need to be redistributed to achieve a more balanced load.

[0104] In this implementation, after synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the event counts of each event type in different cores are compared, the load balancing status between the cores is identified, and the load of each core is distributed according to the load balancing status between the cores. This can avoid the situation where some cores are overloaded while other cores are idle. The system can achieve a more balanced load distribution, thereby improving overall performance and efficiency, and improving the reliability of the multi-core processor system.

[0105] The multi-core processor event monitoring device provided in this embodiment, the receiving module synchronously receives the performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; the calculation module summarizes and analyzes the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, calculates the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type; the processing module performs performance evaluation and system tuning on the multi-core processor system according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type. The scheme of this embodiment, on the one hand, provides a PMU unified management interface to uniformly receive the performance data collected by the PMU of each core, realizes the coordination and management of the PMU of each core, and can realize the cross-core performance monitoring capability. On the other hand, summarizing and analyzing the received data can accurately and efficiently comprehensively evaluate the performance of the entire system and optimize the system. Therefore, the scheme of this embodiment improves the accuracy and efficiency of performance analysis and optimization of the multi-core processor system.

[0106] Figure 4 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 4 As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420 and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute the multi-core processor event monitoring method, the method comprising: synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; according to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type are calculated; according to the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type, the multi-core processor system is subjected to performance evaluation and system tuning.

[0107] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0108] On the other hand, the present invention also provides a computer program product, which includes a computer program, and the computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the multi-core processor event monitoring method provided by the above methods, the method including: synchronously receiving performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored; according to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type are calculated; according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type, the multi-core processor system is performance evaluated and system tuned.

[0109] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the multi-core processor event monitoring method provided by the above-mentioned methods, the method comprising: synchronously receiving performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored; according to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type are calculated; according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type, performance evaluation and system tuning of the multi-core processor system are performed.

[0110] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0111] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-core processor event monitoring method, characterized in that: include: Synchronously receiving performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored; According to the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type are calculated; Performance evaluation and system tuning of the multi-core processor system are performed based on the total event count of each event type in different cores and the minimum and maximum event counts corresponding to each event type.

2. The multi-core processor event monitoring method according to claim 1, characterized in that: Before synchronously receiving the performance data collected by the PMU of each core through the unified interface, the method further includes: Initializing the PMU unified management interface, where the PMU unified management interface is used to manage and coordinate the PMU interface of each core; Through the PMU unified management interface, configure the performance events to be monitored of the PMU of each core and the counters corresponding to each performance event to be monitored; The PMU of each core is started through the PMU unified management interface, so that the PMU of each core starts to collect the performance data.

3. The multi-core processor event monitoring method according to claim 1, characterized in that: Before synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the method further includes: Receive custom performance events sent by users; The custom performance event is defined as a performance event to be monitored through the PMU unified management interface, and a counter corresponding to the custom performance event is configured.

4. The multi-core processor event monitoring method according to claim 1, characterized in that: After synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the method further includes: Compare the event counts of each event type in different cores to identify the load balancing status among the cores; According to the load balancing status among the cores, the load of each core is distributed to balance the load of each core.

5. The multi-core processor event monitoring method according to claim 2, characterized in that: The method further comprises: Through the PMU unified management interface, the following functions of the PMU of each core are configured: opening and closing events, pausing and resuming events, and overflow recording of events.

6. The multi-core processor event monitoring method according to any one of claims 1 to 5, characterized in that: The performance event to be monitored includes at least one of the following: a central processing unit event, a cache event, and an address translation backup buffer event.

7. A multi-core processor event monitoring device, characterized in that: include: A receiving module, used to synchronously receive performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes an event count and an event type corresponding to each performance event to be monitored; A calculation module, used to summarize and analyze the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and calculate the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type; The processing module is used to perform performance evaluation and system tuning on the multi-core processor system according to the total event count of each event type in different cores and the minimum event count and the maximum event count corresponding to each event type.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the multi-core processor event monitoring method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the multi-core processor event monitoring method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the multi-core processor event monitoring method according to any one of claims 1 to 6 is implemented.

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