Computing system, operating method of computing system, and CXL device

Abstract

The invention provides a computing system, an operation method of the computing system, and a CXL device. A computing system according to some embodiments comprises: a host, the host is configured to distribute and allocate process data for each of a plurality of processes to a plurality of logical addresses, determine a significant bit indicating whether a respective one of the plurality of processes corresponding to the respective one of the plurality of logical addresses is executing, and generating update information including the significant bit and the corresponding one of the plurality of logical addresses corresponding to the significant bit; and a storage device that receives the update information from the host.

Description

Technical Field

[0001] The present disclosure relates to a computing system and an operating method thereof. Background Art

[0002] Computing systems can provide various IT services to users. Recently, as the application fields using artificial intelligence and big data increase, the amount of data processed in computing systems is also increasing to provide various IT services to users. Various technologies are being developed to overcome the physical limitations of the memory capacity of computing systems. In particular, Compute ExpressLink (CXL) is a newly proposed interface for more efficiently utilizing accelerators, memory, and storage devices used with CPUs in high-performance computing systems. Summary of the invention

[0003] The present disclosure is directed to efficiently managing data stored in a computing system.

[0004] According to some embodiments, a computing system includes: a host, which distributes and assigns process data for each of a plurality of processes to a plurality of logical addresses, determines a valid bit indicating whether a corresponding one of the plurality of processes corresponding to a corresponding one of the plurality of logical addresses is being executed, and generates update information including the valid bit and the corresponding one of the plurality of logical addresses corresponding to the valid bit; and a storage device, which receives the update information from the host.

[0005] According to some embodiments, the operating method of the computing system includes: distributing and assigning process data for each of a plurality of processes to a corresponding logical address among a plurality of logical addresses; allocating a valid bit indicating whether a corresponding process among the plurality of processes corresponding to a logical address among the plurality of logical addresses is being executed; generating update information including the valid bit and the logical address corresponding to the valid bit; mapping a first logical address of a first type among the plurality of logical addresses to a storage address for a storage device including a non-volatile memory; and based on the update information, when the valid bit indicates that the process is not being executed, performing garbage collection on the storage device at the storage address corresponding to the first logical address.

[0006] A CXL device according to some embodiments includes: a CXL storage device including a non-volatile memory corresponding to a first logical address of a first type among a plurality of logical addresses, wherein the CXL storage device receives a valid bit indicating whether a process corresponding to the first logical address of the first type is being executed, and performs garbage collection on the non-volatile memory based on the valid bit; and a CXL memory including a volatile memory corresponding to a second logical address of a second type among the plurality of logical addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a computing system according to some embodiments.

[0008] Figure 2 is a block diagram illustrating a CXL storage device according to some embodiments.

[0009] Figure 3 is a block diagram illustrating in detail some components of a computing system according to some embodiments.

[0010] Figure 4 It is shown that according to Figure 1 A view of a memory area managed by a computing system.

[0011] Figure 5 It shows that according to Figure 1 A flowchart of a method of operating a computing system.

[0012] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a diagram of a mapping table illustrating the operation of a computing system according to some embodiments.

[0013] Fig.10 is a block diagram illustrating a computing system according to some embodiments.

[0014] Fig.11 is a block diagram illustrating a server system according to some embodiments. DETAILED DESCRIPTION

[0015] In the following detailed description, only certain embodiments of the present disclosure are shown and described by way of illustration. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0016] Therefore, the drawings and descriptions are considered to be illustrative in nature, rather than restrictive. Throughout the specification, the same reference numerals represent the same elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, some operations may be separated, and specific operations may not be performed.

[0017] In addition, unless an explicit expression such as "one" or "single" is used, expressions written in the singular may be understood in the singular or in the plural. Terms including ordinal numbers such as first, second, etc. will be used to describe various components and should not be interpreted as limiting these components. These terms may be used for the purpose of distinguishing one element from other elements.

[0018] Figure 1 is a block diagram illustrating a computing system according to some embodiments.

[0019] refer to Figure 1 , the computing system 100 may include a host 110, a host memory 120, and at least one CXL (Compute Express Link) device 130. CXL is an open standard for high-speed, high-capacity CPU-to-device and CPU-to-memory connections designed for high-performance data center computers. CXL is built on a serial PCI Express (PCIe) physical and electrical interface and includes a PCIe-based block input / output protocol (CXL.io) and a cache coherence protocol for accessing system memory (CXL.cache) and device memory (CXL.mem). Serial communication and pooling capabilities allow CXL memory to overcome the performance and slot packaging limitations of ordinary DIMM memory when implementing high storage capacity.

[0020] In some embodiments, the computing system 100 may be included in a user device such as a personal computer, a laptop computer, a server, a media player, a digital camera, etc., or in a vehicle device such as a navigation device, a black box, a vehicle electronic device, etc. It can be included in the same vehicle equipment. In some embodiments, the computing system 100 is a mobile system such as a portable communication terminal (mobile phone), a smart phone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an IOT (Internet of Things) device.

[0021] The host 110 may control the overall operation of the computing system 100. In some embodiments, the host 110 may be one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a data processing unit (DPU). In some embodiments, the host 110 may include a single-core processor or a multi-core processor.

[0022] In some embodiments, the host 110 may drive a plurality of processes. The host 110 may distribute and store data required to drive the plurality of processes in the host memory 120 and at least one CXL device 130. Hereinafter, the data required to drive the plurality of processes is referred to as process data. Specifically, when the host 110 requires a fast input / output speed, the process data may be stored in the host memory 120. When consistency is important, the host 110 may store the process data in at least one CXL device 130. That is, the host 110 may distribute and store data in a plurality of CXL storage devices 132, a plurality of CXL memories 133, and the host memory 120, respectively.

[0023] In some embodiments, while the host 110 is driving, running, or executing a plurality of processes, some processes may be terminated. When a process is terminated, data corresponding to the terminated process is referred to as invalid data. Additionally, data required to drive a process, run a process, or execute a process is referred to as valid data. The host 110 may determine a valid bit for each address of the plurality of CXL storage devices 132, the plurality of CXL memories 133, and the host memory 120. The valid bit may indicate whether the process data stored in the corresponding address is invalid data or valid data. In other words, the valid bit may indicate whether the process corresponding to the address is being driven, run, or executed. In some embodiments, when the valid bit is 1, it may indicate that the process is being driven or executed by the host 110, and when the valid bit is 0, it may indicate that the process is being terminated by the host 110. In some embodiments, when the valid bit changes, the host 110 may generate update information. The update information may include the changed valid bit and the address corresponding to the changed valid bit. For example, when the driving process, running process, or executing process is terminated, the host 110 may generate update information. The host 110 may transmit the update information to the CXL device 130a. In some embodiments, the host 110 may store the update information in the host memory 120. In some embodiments, the host memory 120 and the CXL memory 133a may be connected via a separate coherent interface. When the coherence between the host memory 120 and the CXL memory 133a is maintained, the CXL device 130a may refer to the update information in the CXL memory 133a even if the host 110 does not send the update information to the CXL device 130a.

[0024] Meanwhile, the host 110 may determine a valid bit for each address of the plurality of CXL memory devices 132. In this case, when the valid bit for each address of the plurality of CXL memory devices 132 changes, the host 110 may generate update information.

[0025] The host memory 120 may be used as a main memory or system memory of the computing system 100. In some embodiments, the main memory 120 may be a dynamic random access memory (DRAM) device and may be in the form of a dual in-line memory module (DIMM). However, the scope of the present disclosure is not limited thereto, and the memory 120 may include a non-volatile memory such as a flash memory, a PRAM, a RRAM, an MRAM, etc.

[0026] The host memory 120 may communicate directly with the host 110 through a double data rate (DDR) interface. In some embodiments, the host 110 may include a memory controller configured to control the host memory 120. However, the scope of the present disclosure is not limited thereto, and the host memory 120 may communicate with the host 110 through various interfaces.

[0027] The at least one CXL device 130 may be implemented as a separate memory device or memory module. Each of the at least one CXL device 130 may be connected to the CXL interface 115 via a different physical port.

[0028] The CXL device 130 a may include a CXL controller 131 a , a CXL storage device 132 a , and a CXL memory 133 a .

[0029] The CXL controller 131a may include an intellectual property (IP) circuit designed to implement an application specific integrated circuit (ASIC) and / or a field programmable gate array (FPGA). In various embodiments, the CXL controller 131 may be implemented to support a CXL protocol (e.g., a CXL 2.0 protocol or any other version). The CXL controller 131 may convert a CXL packet and a signal of a memory interface of the CXL memory 133a, and a CXL packet and a signal of a memory interface of the CXL storage device 132a. For example, the CXL controller 131a may convert a logical address received from the host 110 through the CXL interface 115 into a CXL address. At this time, the CXL address may include a CXL memory address for the CXL memory 133a and a CXL storage device address for the CXL storage device 132a. The CXL address may be an address managed by the CXL controller 131a.

[0030] The address mapping operation may be an operation of converting or mapping between a logical address managed by the host 110 and an address of the CXL memory 133 a in the CXL device 130 a or an address of the CXL storage device 132 a .

[0031] For example, the CXL controller 131 a may control the CXL storage device 132 a or the CXL memory 133 a so that a CXL data packet transmitted from the host 110 is stored in the CXL storage device 132 a or the CXL memory 133 a. Specifically, the CXL controller 131 a may convert data received from the host 110 to be stored in the CXL storage device 132 a or the CXL memory 133 a, or convert data stored in the CXL storage device 132 a or the CXL memory 133 a to be transmitted to the host 110.

[0032] The CXL memory device 132a may store data in a CXL memory device address received from the CXL controller 131a. Figure 2 and Figure 1 Refer to it together.

[0033] Figure 2 is a block diagram illustrating a CXL storage device according to some embodiments.

[0034] like Figure 2 As shown, the CXL memory device 132a may include a memory controller 200 and a non-volatile memory (NVM) 201. The CXL memory device 132a may store data or process data in response to a control signal of the CXL controller 131a.

[0035] The memory controller 200 may control the operation of the CXL memory device 132a. For example, the memory controller 200 may provide an address ADDR, a command CMD, a control signal CTRL, etc. to the nonvolatile memory 201 in response to a control signal received from the CXL controller 131a. That is, the memory controller 200 may provide a signal to the nonvolatile memory 201 to program data into the nonvolatile memory 201, or read data from the nonvolatile memory 201. Additionally, the memory controller 200 and the nonvolatile memory 201 may exchange data DATA.

[0036] Specifically, the storage controller 200 may include a processor 210 , a flash translation layer (FTL) 220 , a buffer memory 230 , a CXL interface 240 , and a memory interface 250 .

[0037] The processor 210 may control the overall operation of the storage controller 200. The processor 210 may control the storage controller 200 by driving, running, or executing firmware loaded on the FTL 220. In some embodiments, the processor 210 may include a central processing unit (CPU), a controller, or an application specific semiconductor (ASIC).

[0038] The processor 210 may drive various firmware or software driven on the storage controller 200. The processor 210 may use the buffer memory 230 as an operation memory of the processor 210. Additionally, the processor 210 may use the nonvolatile memory 201 as an operation memory of the processor 210.

[0039] Flash translation layer (FTL) 220 may include firmware or software for managing data programming, data reading, and sub-block and / or block erase operations of nonvolatile memory 201 , etc. The firmware of FTL 220 may be executed by processor 210 .

[0040] In some embodiments, FTL 220 may perform various maintenance operations to effectively use nonvolatile memory 201. Specifically, FTL 220 may perform various functions such as address mapping and garbage collection.

[0041] The FTL 220 may perform an address mapping operation of changing a CXL memory device address received from the CXL controller 131 a into a physical address for actually storing data in the nonvolatile memory 201. Specifically, the FTL 220 may map the CXL memory device address from the CXL controller 131 a and the physical address of the nonvolatile memory 201 by using an address mapping table. The address mapping operation may be an operation of converting or mapping between the CXL memory device address managed by the CXL controller 131 a and the address of the nonvolatile memory 201.

[0042] FTL 220 can perform garbage collection to ensure the capacity available in non-volatile memory 201. The garbage collection operation can be an operation of copying valid data in a block of non-volatile memory 201 to a new block and erasing an existing block so that the existing block can be reused. In other words, the operation of FTL 220 removing invalid pages and merging pages programmed with valid data is called garbage collection. Since non-volatile memory 201 cannot be rewritten, when a request to program new data in a page in which data is programmed is received from host 110, storage controller 200 can program new data in a new page of non-volatile memory 201. At this time, the page in which data was previously programmed may be invalid. As data is continuously written to flash memory, valid data may be scattered throughout the flash memory, and FTL 220 performs garbage collection to ensure storage space, i.e., free blocks, in which data programming is possible.

[0043] Meanwhile, the CXL storage device 132a may not know information about the process terminated in the host 110. Therefore, the CXL storage device 132a may perform garbage collection even on the page including invalid data. Performing garbage collection on the invalid data may cause the durability and performance (quality of service, QoS) of the CXL storage device 132a to deteriorate. Meanwhile, the host 110 according to some embodiments may change a valid bit corresponding to an address in which the invalid data is stored. The host 110 may generate an address corresponding to the changed valid bit and update information including the changed valid bit. The host 110 may send the update information to the CXL storage device 132a. The FTL 220 may perform garbage collection based on the valid bit in the update information. Specifically, the FTL 220 may perform garbage collection on the page including the valid data, and remove the page including the invalid data. Therefore, the performance (QoS) of the CXL storage device 132a may be improved, and the durability may be improved.

[0044] In some embodiments, the host 110 may store the generated update information in the host memory 120. If consistency between the host memory 120 and the CXL memory 133a is maintained, the CXL memory device 132a may perform garbage collection based on a valid bit in the update information in the CXL memory 133a.

[0045] In some embodiments, when the available memory area within the non-volatile memory 201 exceeds a predetermined garbage collection level, the FTL 220 may perform a garbage collection operation. The garbage collection level may be a predetermined threshold at which the FTL 220 determines the initiation of garbage collection. In some embodiments, the garbage collection operation may be performed by sub-block units as well as by block units. In some embodiments, the FTL 220 may perform garbage collection operations periodically, i.e., with a regular time period between performing garbage collection operations.

[0046] In some embodiments, the FTL 220 may receive a trim command from the host 110. The trim command may be a command notifying the CXL memory device 132a that data present in a specific area is no longer used in the CXL memory device 132a. In response to receiving the trim command from the host 110, the FTL 220 may perform garbage collection based on a valid bit in the update information.

[0047] In some embodiments, the FTL 220 may store data necessary for performing operations of the FTL 220. For example, the FTL 220 may store block information of the nonvolatile memory 201, a garbage collection level for performing garbage collection on the nonvolatile memory 201, an address mapping table for converting a CXL storage device address into a physical address of the nonvolatile memory 201, an address mapping table managed by garbage collection or wear leveling operations, etc. Meanwhile, the present disclosure is not limited thereto, and data for performing operations of the FTL 220 may be stored in the buffer memory 230, and may be stored in the nonvolatile memory 201.

[0048] The buffer memory 230 may store instructions and data executed and processed by the memory controller 200. The buffer memory 230 may temporarily store data stored in the nonvolatile memory 201 or data to be stored.

[0049] In some embodiments, the buffer memory 230 may be implemented as a volatile memory such as a dynamic random access memory (DRAM), a static RAM (SRAM), etc. However, without limitation thereto, the buffer memory 230 may be implemented as a resistive non-volatile memory such as a magnetic RAM (MRAM), a phase change RAM (PRAM), or a resistive RAM (ReRAM), a flash memory, various non-volatile memories such as a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), or a ferroelectric random access memory (FRAM), etc.

[0050] In some embodiments, the buffer memory 230 may store code data required for initial booting of the CXL memory device 132a. The buffer memory 230 may buffer CXL memory device addresses, request signals, data, commands, etc. received from the CXL controller 131a. The signals buffered in the buffer memory 230 may be sent to the nonvolatile memory 201 through the memory interface 250 to be used. For example, the data buffered in the buffer memory 230 may be programmed in the nonvolatile memory 201.

[0051] exist Figure 2 , the buffer memory 230 is illustrated as being disposed inside the memory controller 200 , but the present disclosure is not limited thereto, and the buffer memory 230 may be disposed outside the memory controller 200 and may be a part of the CXL memory 133 a .

[0052] A CXL interface (CXL I / F) 240 may send and receive data packets with the CXL controller 131 a. Data packets received from the CXL controller 131 a through the CXL interface 240 may include commands, data to be programmed in the nonvolatile memory 201, and a CXL memory device address for programming the data. Data packets sent from the memory controller 200 to the CXL controller 131 a through the CXL interface 240 may include responses to commands or data read from the nonvolatile memory 201.

[0053] The memory interface (NVM I / F) 250 may provide signal transmission and reception with the nonvolatile memory 201. The memory interface 250 may transmit data to be programmed into the nonvolatile memory 201, a command, a physical address into which data is to be programmed, and a control signal to the nonvolatile memory 201, or receive data read from the nonvolatile memory 201. This memory interface 250 may be implemented to comply with a standard protocol such as trigger or ONFI.

[0054] The non-volatile memory 201 may include multiple dies or multiple chips including a memory cell array. For example, the non-volatile memory 201 may include multiple chips, and each of the multiple chips may include multiple dies. In some embodiments, the non-volatile memory 201 may also include multiple channels, each of the multiple channels including multiple chips.

[0055] The nonvolatile memory 201 may include a NAND flash memory. In some embodiments, the nonvolatile memory 201 may include an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), a resistive RAM (ReRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), or a memory similar to them. Hereinafter, in the present disclosure, the nonvolatile memory 201 will be explained assuming that it is a NAND flash memory device.

[0056] Reference again Figure 1 , the CXL memory 133 a may store data in the CXL memory address received from the CXL controller 131 a .

[0057] In some embodiments, the CXL memory 133a may include one of dynamic random access memory (DRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, double data rate synchronous DRAM (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), or a combination thereof.

[0058] In some embodiments, the host 110 and the at least one CXL device 130 may be configured to share the same interface. For example, the host 110 and the at least one CXL device 130 may communicate with each other via the CXL interface 115. The host 110 may access the CXL memory 133 of the CXL device 130 via the CXL interface 115, and the CXL device 130 may also access the memory 120 of the host 110 and / or the CXL memory 133 of another CXL device 130 via the CXL interface 115.

[0059] In some embodiments, the CXL interface 115 may refer to a low-latency and high-bandwidth link that implements various connections between accelerators, memory devices, or various electronic devices by supporting consistency of input / output protocols (IO protocols), memory access, and dynamic protocol multiplexing. Hereinafter, for better understanding and ease of description, it is assumed that the host 110 and the CXL device 130 communicate with each other through the CXL interface 115. Meanwhile, the present disclosure is not limited to the CXL interface 115, and the host 110 and the CXL device 130 may communicate with each other based on various computing interfaces such as a GEN-Z protocol, an NVLink protocol, a CCIX protocol, an open CAPI protocol, etc.

[0060] CXL, which is an open communications industry standard based on Peripheral Component Interconnect Express (PCIe) 5.0, can provide fixed and / or relatively short packet sizes, resulting in relatively high bandwidth and relatively low fixed latency. Thus, CXL can support cache coherency, and CXL can be well suited for creating or generating connections to memory. CXL can be used in a server to provide connections between a host 110 and a CXL device 130 (e.g., an accelerator, a memory device, and a network interface circuit (or "network interface controller" or network interface card (NIC)).

[0061] Figure 3 is a detailed block diagram showing some constituent elements of a computer system according to some embodiments.

[0062] refer to Figure 3, the host 300 and the CXL devices 320a, 320b, ..., and 320h may communicate with each other through the CXL switch 310. The CXL switch 310 may be a component included in the CXL interface. The CXL switch 310 may be configured to mediate communication between the host 300 and the CXL device 320. For example, when the host 300 and the CXL device 320 communicate with each other, the CXL switch 310 may be configured to send information such as a request, data, response, or signal sent from the host 300 or the CXL device 320 to the CXL device 320 or the host 300. When the CXL devices 320a, 320b, ..., and 320h communicate with each other, the CXL switch 310 may be configured to transfer information such as a request, data, response, or signal between the CXL devices 320a, 320b, ..., and 320h.

[0063] Host 300 may include CXL controller 301. CXL controller 301 may communicate with CXL device 320 via CXL switch 310. CXL controller 301 may be connected to memory controller 302 and associated host memory 303.

[0064] The CXL switch 310 may be used to implement storage clustering through one-to-many and many-to-one switching between the connected CXL devices 320 a , 320 b , . . . , and 320 h .

[0065] In addition to providing packet switching functionality for CXL packets, CXL switch 310 may be used to connect CXL devices 320a, 320b, ..., and 320h to one or more hosts 300. CXL switch 310 (i) may allow CXL devices 320a, 320b, ..., and 320h to include different types of memory with different characteristics, (ii) may virtualize the memory of CXL devices 320a, 320b, ..., and 320h and allow data of different characteristics (e.g., access frequency) to be stored in the appropriate type of memory, and (iii) may support remote direct memory access (RDMA). Herein, "virtualizing" memory indicates that memory address translation is performed between processing circuits and memory.

[0066] like Figure 3As shown, a single CXL link may include three multiplexed sub-protocols. Specifically, the CXL link may include CXL.io, CXL.cache, and CXL.mem as coherence protocols. CXL.io is based on the Peripheral Component Interconnect Express (PCIe) specification and may be a protocol related to device discovery, configuration, register access, interrupts, etc. CXL.cache may be a protocol for configuring CXL device 320a to access host memory 303. CXL.mem may be a protocol for configuring host 300 to access CXL memory 322 and CXL storage device 323 of CXL device 320a.

[0067] The host 300 may manage the accessible memory space. Managing the memory space may include conversion between virtual addresses used by the host 300 and addresses recognized by the CXL device 320a (e.g., physical addresses or additional virtual addresses). In some embodiments, the host 300 may send commands (e.g., memory save / load commands) to the CXL storage device 323 and the CXL memory 322 through a first protocol (e.g., CXL.mem). The host 300 may recognize the CXL storage device 323 and the CXL memory 322 as the same type of memory.

[0068] Meanwhile, the present disclosure is not limited thereto, and the CXL devices (320a, 320b, ..., 320h) may communicate with the host 300 by using any type of storage interface and / or protocol such as Peripheral Component Interconnect Express (PCIe), NVMe, NVMe-oF (NVMe over Fiber), NVMe-KV (NVMe Key Value), SATA, SCSI, etc. In some embodiments, the CXL devices 320a, 320b, ..., 320h may implement consistency (e.g., memory consistency, cache consistency, etc.).

[0069] The CXL device 320a may include a CXL controller 321, a CXL storage device 323 including a storage controller 324 and a memory such as a CXL NVM 325. Other CXL devices 320b, ..., 320h may also include the same or similar components as the CXL device 320a.

[0070] CXL controller 321 may be connected to CXL switch 310. CXL controller 321 may communicate with host 300 and / or other CXL devices through CXL switch 310. CXL controller 321 may include a PCIe 5.0 (or other version) architecture for a CXL.io path, and may add CXL.cache and CXL.mem paths designated for CXL.

[0071] The CXL controller 321 may be configured to manage the CXL memory 322. In some embodiments, the CXL controller 321 may map a logical address received from the host 300 to a CXL memory address corresponding to the CXL memory 322. In some embodiments, the CXL controller 321 may store data received from the host 300 in the CXL memory 322 or read the stored data. In some embodiments, at least a portion of an area of ​​the CXL memory 322 may be allocated as a dedicated area for the CXL device 320a, and the remaining area may be used as an area accessible by the host 300 or other CXL devices 320b, ..., and 320h.

[0072] The CXL controller 321 may be configured to manage the CXL storage device 323. In some embodiments, the CXL controller 321 may map a logical address received from the host 300 to a CXL storage device address corresponding to the CXL storage device 323. In some embodiments, the CXL controller 321 may store data received from the host 300 in the CXL storage device 323, or read the stored data.

[0073] In some embodiments, CXL controller 321 may be implemented to comply with a standard protocol such as a DDR interface, a LPDDR interface, or the like.

[0074] The CXL memory 322 may store data received from the host 300 in a CXL memory address under the control of the CXL controller 321 .

[0075] The CXL storage device 323 may include a storage controller 324 and a CXL NVM 325. The storage controller 324 may map a CXL storage device address received through the CXL controller 321 to a physical address of the CXL NVM 325. The storage controller 324 may control the CXL NVM 325 so that data is stored in the CXL NVM 325 or data is read from the CXL NVM 325. The storage controller 324 may be configured to manage the CXL NVM 325. In some embodiments, the storage controller 324 may perform garbage collection periodically or at a regular time period.

[0076] Figure 4 It is shown that according to Figure 1 A view of a memory area managed by a computing system.

[0077] The host 110 may manage the host memory 120 and the memories of the CXL memory 133 a and the CXL storage device 132 a in at least one CXL device 130 a connected through the CXL interface 115 .

[0078] like Figure 4 As shown, the memory region 400 of the computing system 100 may include a host memory region 401, a CXL memory region 403, and a CXL storage region 405. The CXL memory region 403 and the CXL storage region 405 may be referred to as CXL regions.

[0079] Memory regions 400 may include a high-level memory address and a low-level memory address for each region. For example, the high-level memory address may be a logical address assigned by host 110. In some embodiments, host 110 may assign separate high-level memory addresses to host memory region 401, CXL memory region 403, and CXL storage region 405. For example, a first type of logical address may be assigned to host memory region 401, a second type of logical address may be assigned to CXL memory region 403, and a third type of logical address may be assigned to CXL storage region 405.

[0080] Meanwhile, the host 110 is described as generating update information when the operation of the process corresponding to the first type of logical address, the second type of logical address, and the third type of logical address changes, but the present disclosure is not limited thereto, and the host 110 may generate update information when the operation of the process corresponding to the third type of logical address changes. In other words, even if the operation of the process corresponding to the first type of logical address and the second type of logical address changes, the host 110 does not generate update information.

[0081] In some embodiments, when the operation of the processes corresponding to the first type logical address and the second type logical address changes, the host 110 may generate update information. The host 110 may not send update information for the first type logical address to the host memory 120, and may not send update information for the second type logical address to the CXL device 130a.

[0082] For example, the lower memory address may be a CXL address of CXL controller 131a. In some embodiments, the lower memory address may be a physical address within host memory 120, CXL memory 133a, and CXL storage device 132a.

[0083] The host 110 may distribute and allocate the process data to the host memory area 401, the CXL memory area 403, and the CXL storage area 405. Specifically, the host 110 may distribute and store the process data in the host memory area 401, the CXL memory area 403, and the CXL storage area 405 based on the input / output speed and consistency level of the process data. The consistency level may indicate the accuracy of the process data. For example, the host memory area 401 may include data that requires a fast input / output speed. The CXL memory area 403 or the CXL storage area 405 may include data that requires consistency.

[0084] Figure 5 It shows that according to Figure 1 A flowchart of a method of operating a computing system. Figure 6 , Figure 7 , Figure 8 and Fig. 9 is a diagram of a mapping table illustrating the operation of a computing system according to some embodiments.

[0085] First, the host 110 allocates a plurality of process data to a plurality of logical addresses (S501).

[0086] For example, the plurality of logical addresses may be logical addresses for the host memory 120 , the CXL memory 133 a , and the CXL storage device 132 a .

[0087] In some embodiments, the host 110 may generate a plurality of process information. The process information may be data indicating an address to which process data is dispatched. The host 110 may send the plurality of process information to the CXL device 130a.

[0088] refer to Figure 6 Step (S501) is described.

[0089] Figure 6 is a mapping table showing the logical addresses in which data for each process is stored.

[0090] The first mapping table 600 may store a logical address 603 corresponding to each of the plurality of process data 601. The host 110 may create the first mapping table 600 by distinguishing the logical address for each process. For example, the host 110 may distinguish the plurality of logical addresses into a logical address in which first process data required for a first process is stored, a logical address in which second process data required for a second process is stored, a logical address in which third process data required for a third process is stored, and the like to create the first mapping table 600.

[0091] like Figure 6As shown, the first process information 611 may indicate that the process data corresponding to the first process is allocated to the logical address (00-0F). At this time, the logical address (00-0F) may be a logical address included in the host memory 120.

[0092] The second process information 613 may indicate that process data corresponding to the second process is allocated to the logical address (20-2F). At this time, the logical address (20-2F) may be a logical address included in the CXL memory 133a.

[0093] The third process information 615 may indicate that process data corresponding to the third process is allocated to the logical address (10-1F). At this time, the logical address (10-1F) may be a logical address included in the CXL memory device 132a.

[0094] At the same time, if Figure 6 As shown, the host 110 can divide and allocate process data required to drive one process to the host memory 120, CXL memory 133a and CXL storage device 132a. Additionally, the host 110 can allocate process data required to drive different processes to one memory and also allocate them together to the same logical address in the memory.

[0095] The host 110 maps the CXL address to each of a plurality of logical addresses corresponding to the host memory 120 ( S503 ).

[0096] In some embodiments, the process information may also include a CXL address that maps to a logical address to which the process data is dispatched.

[0097] Thereafter, the CXL controller 131 a maps the CXL address to each of a plurality of logical addresses corresponding to the CXL memory 133 a and the CXL storage device 132 a ( S505 ).

[0098] Specifically, the CXL controller 131a may receive a plurality of process information from the host 110. The CXL controller 131a may map a CXL address to each of a plurality of logical addresses corresponding to the CXL memory 133a and the CXL storage device 132a.

[0099] Step (S503) and step (S505) are referred to together Figure 7 and Figure 8 .

[0100] Figure 7 is a mapping table showing CXL addresses corresponding to a plurality of logical addresses. Figure 8 It is a mapping table showing process data corresponding to CXL addresses.

[0101] The second mapping table 700 may store a logical address 703 and a CXL address 705 corresponding to each of the plurality of process data 701 . The CXL controller 131 a may receive the plurality of process information from the host 110 to create the second mapping table 700 .

[0102] like Figure 7 As shown, the first process information 711 may indicate that process data corresponding to the first process is allocated to a logical address (00-0F) and a CXL address (00-0F).

[0103] The second process information 713 may indicate that process data corresponding to the second process is allocated to a logical address (20-2F) and a CXL address (80-8F).

[0104] The third process information 715 may indicate that process data corresponding to the third process is allocated to a logical address (10-1F) and a CXL address (40-4F).

[0105] like Figure 8 As shown, the third mapping table 800 may store a plurality of process data 701 and CXL addresses 705. The CXL controller 131a may create the third mapping table 800 by aligning the second mapping table 700 with the CXL addresses included in the same memory region as a reference.

[0106] On the other hand, Figure 5 In the embodiment, it is described that the host 110 sequentially performs step S503 in which a plurality of logical addresses corresponding to the host memory 120 are mapped to CXL addresses and step S505 in which the CXL addresses are mapped to each of a plurality of logical addresses corresponding to the CXL memory 133 a and the CXL storage device 132 a, but the order of mapping the plurality of logical addresses to the CXL addresses is not limited thereto. For example, the computing system 100 may also simultaneously perform the step of the host 110 mapping the plurality of logical addresses for the host memory 120 to the CXL addresses and the step of the CXL controller 131 a mapping the plurality of logical addresses for the CXL memory 133 a and the CXL storage device 132 a to the CXL addresses.

[0107] The CXL storage device 132 a maps the physical address corresponding to the CXL address ( S507 ).

[0108] Specifically, the storage controller ( Figure 2 200 in FIG. 10 ) can receive the CXL address from the CXL controller 131a. The FTL ( Figure 2 220) can map the non-volatile memory corresponding to the CXL address ( Figure 2 The physical address in 201).

[0109] The host 110 may distinguish the CXL address for each memory region. For example, the host 110 may determine the valid bits for the CXL address included in the CXL memory device. Thereafter, the host 110 may send information including the CXL address and the valid bits corresponding to the CXL address to the CXL memory device 132a.

[0110] Thereafter, the host 110 updates a valid bit corresponding to the terminated process among the plurality of processes ( S509 ).

[0111] When the valid bit changes, the host 110 may generate update information. In some embodiments, when the valid bit corresponding to the logical address included in the CXL storage device 132a changes, the host 110 may create or generate update information. The host 110 may send the update information to the CXL storage device 132a through the CXL controller 131a. The update information may include the changed valid bit and the logical address corresponding to the changed valid bit. The CXL controller 131a may determine the CXL address corresponding to the logical address based on the second mapping table 700 and the third mapping table 800. At this time, the CXL controller 131a may select a CXL address included in the CXL storage device 132a from among the CXL addresses. The CXL controller 131a may send the selected CXL address to the CXL storage device 132a. The storage controller ( Figure 2 200) in the example embodiment may update a valid bit corresponding to a CXL address received from CXL controller 131a.

[0112] refer to Fig. 9 Step (S507) is described. Fig. 9 is a mapping table showing physical addresses and valid bits corresponding to CXL addresses.

[0113] The CXL memory device 132 a may create a fourth mapping table 900 for CXL addresses included in the CXL memory device 132 a .

[0114] The fourth mapping table 900 may store CXL addresses 905 , process data 901 corresponding to the CXL addresses 905 , and a physical address 907 corresponding to each CXL address 905 .

[0115] like Fig. 9 As shown, the first process information 911 may indicate that process data corresponding to the fourth process is allocated to a CXL address (30-3F) and a physical address (00-0F).

[0116] The second process information 913 may indicate that process data corresponding to the third process is allocated to a CXL address (40-4F) and a physical address (10-1F).

[0117] The third process information 915 may indicate that process data corresponding to the fourth process is allocated to the CXL address (50-5F) and the physical address (20-2F).

[0118] Meanwhile, the fourth mapping table 900 may also store a valid bit corresponding to each CXL address 905. In some embodiments, when the valid bit is 1, it may indicate that the process is being driven, run, or executed, and when the valid bit is 0, it may indicate that the process is terminated. Since each of the plurality of processes may be being driven, run, or executed, all valid bits corresponding to the plurality of CXL addresses (30-3F, 40-4F, 50-5F) may be 1.

[0119] For example, assuming that the fourth process is terminated, the host 110 may generate update information including a logical address corresponding to the fourth process among the plurality of logical addresses and a changed valid bit. That is, update information including the logical address (00-0F) of the CXL storage device 132a corresponding to the fourth process in the first mapping table 600, the logical address (10-1F) of the CXL storage device 132a, and the logical address (20-2F) of the CXL memory 133a may be created.

[0120] The CXL controller 131a may determine that the logical address (00-0F) of the CXL storage device 132a corresponds to the CXL address (30-3F), the logical address (10-1F) of the CXL storage device 132a corresponds to the CXL address (50-5F), and the logical address (20-2F) of the CXL memory 133a corresponds to the CXL address (60-6F). At the same time, the CXL controller 131a may select the CXL address included in the CXL storage device 132a among the CXL addresses. That is, the CXL controller 131a may select the CXL address (30-3F) and the CXL address (50-5F). The storage controller 200 may update the valid bits corresponding to the CXL address (30-3F) and the CXL address (50-5F). Therefore, the storage controller 200 may change the valid bits included in the first process information 911 and the valid bits included in the third process information 915 from 1 to 0 in the fourth mapping table 900.

[0121] At the same time, Fig. 9 , the fourth mapping table 900 is illustrated as including physical addresses, but the present disclosure is not limited thereto, and the fourth mapping table 900 may not include physical addresses.

[0122] The CXL storage device 132 a performs garbage collection on the nonvolatile memory based on the valid bit ( S511 ).

[0123] Specifically, the memory controller 200 may perform garbage collection of removing pages storing invalid data therein and merging pages storing valid data therein based on valid bits corresponding to the CXL addresses.

[0124] In summary, when a process is terminated, the host 110 may change a valid bit corresponding to a logical address including data for the terminated process, and create or generate update information including the changed valid bit and the corresponding logical address. In some embodiments, the host 110 may change a valid bit corresponding to a CXL address including data about the terminated process, and generate update information including the changed valid bit and the corresponding CXL address. The host 110 may send the update information to the CXL controller 131a. Thereafter, the storage controller 200 may determine a physical address corresponding to the CXL address, and perform garbage collection on the determined physical address.

[0125] Therefore, the CXL store 132 a may perform garbage collection on pages including data for the terminated process, and thus may efficiently manage the data.

[0126] Although as an example reference Figures 6 to 9 Mapping tables are described, but this is for illustration purposes, and the computing system 100 is not required to create the mapping tables. Additionally, the data included in each mapping table may also be changed appropriately.

[0127] Meanwhile, the present disclosure is not limited thereto, and the host 110 may generate a separate trim command based on the valid bit. The trim command may be a command to notify the CXL memory device 132a that data existing in a specific area is no longer used for the CXL memory device 132a. The CXL memory device 132a may perform garbage collection when it receives the trim command from the host 110.

[0128] Fig.10 is a block diagram illustrating a computing system according to some embodiments.

[0129] refer to Fig.10 The computing system 1000 may include a first CPU 1010 a , a second CPU 1010 b , a GPU 1030 , an NPU 1040 , a CXL switch 1015 , a CXL memory 1050 , a CXL storage device 1052 , a PCIe device 1054 , and an accelerator (CXL device) 1056 .

[0130] The first CPU 1010 a , the second CPU 1010 b , the GPU 1030 , the NPU 1040 , the CXL memory 1050 , the CXL storage device 1052 , the PCIe device 1054 , and the accelerator 1056 may be commonly connected to the CXL switch 1015 , and may communicate with each other through the CXL switch 1015 , respectively.

[0131] In some embodiments, the first CPU 1010a, the second CPU 1010b, the GPU 1030, and the NPU 1040 may be reference 1010a, 1010b, 1030, and 1040, respectively. Figures 1 to 9 The hosts described herein may each be directly connected to a separate memory 1020a, 1020b, 1020c, 1020d and / or 1020e.

[0132] In some embodiments, CXL memory 1050, CXL storage device 1052, and accelerator 1056 may be reference Figures 1 to 9 Work may be distributed to the CXL memory 1050, the CXL storage device 1052, and the accelerator 1056 by one or more of the first CPU 1010a, the second CPU 1010b, the GPU 1030, and the NPU 1040, and work may be distributed to the CXL memory 1050, the CXL storage device 1052, and the accelerator 1056 by one or more of the CXL memory 1050, the CXL storage device 1052, and the accelerator 1056.

[0133] In some embodiments, the CXL switch 1015 may be connected to a PCIe device 1054 or an accelerator 1056 configured to support various functions, and the PCIe device 1054 or the accelerator 1056 may communicate with each of the first CPU 1010 a, the second CPU 1010 b, the GPU 1030, and the NPU 1040 through the CXL switch 1015, or access the CXL memory 1050 and the CXL storage device 1052.

[0134] In some embodiments, CXL switch 1015 may be connected to an external network 1060 or fabric such as a switch fabric, and may be configured to communicate with external servers through external network 1060 or fabric.

[0135] Fig.11 is a block diagram illustrating a server system according to some embodiments.

[0136] refer to Fig.11, the data center 1100 (which is a facility for collecting various data and providing services) may also be referred to as a data storage center. The data center 1100 may be a system for operating a search engine and a database, and may be a computer system used in a government or a corporate institution such as a bank. The data center 1100 may include application servers 1110a, 1110b, ..., 1110h and storage servers 1120a, 1120b, ..., 1120h. According to some embodiments, a plurality of application servers and a plurality of storage servers may be selected differently and may be different from each other.

[0137] Hereinafter, the configuration of the first storage server 1120a will be mainly described. Each of the application servers 1110a, ..., 1110h and the storage servers 1120a, ..., 1120h may have a similar structure to each other, and may communicate with each other through the network NT.

[0138] The first storage server 1120a may include a processor 1121, a memory 1122, a switch 1123, a CXL device 1125, and a network interface card (NIC) 1126. The processor 1121 may control the overall operation of the first storage server 1120a, and may access the memory 1122 to execute instructions or process data loaded in the memory 1122. The processor 1121 and the memory 1122 may be directly connected, and the number of processors 1121 and the number of memories 1122 included in one storage server 1120a may be variously selected.

[0139] In some embodiments, the processor 1121 and the memory 1122 may provide a processor-memory pair. In some embodiments, the number of processors 1121 and the number of memories 1122 may be different. The processor 1121 may include a single-core processor or a multi-core processor. The above description of the storage server 1120 may be similarly applied to each of the application servers 1110a, ..., and 1110h.

[0140] The switch 1123 may be configured to mediate or route communications between various components included in the first storage server 1120a. In some embodiments, the switch 1123 may be Figure 2 and Figure 5 In other words, the switch 1123 may be a switch implemented based on the CXL protocol.

[0141] The CXL device 1125 may be a reference Figures 1 to 9 The CXL device 1125 may include a CXL interface circuit CXL_IF, a controller CTRL, a NAND flash NAND, and a CXL memory.

[0142] The CXL device 1125 may be connected to the switch 1123. The CXL device 1125 may store data or output the stored data according to a request of the processor 1121.

[0143] In the first storage server 1120a according to some embodiments, the processor 1121 may generate update information when the connection relationship with some application servers among the connected application servers 1110a, ..., 1110h changes. The controller CTRL may perform a garbage collection operation of the NAND flash NAND based on the update information. For example, the controller CTRL may remove a page including data corresponding to an application server whose connection has been terminated, and may program a page including data corresponding to an application server whose connection has not been terminated into a new page. Therefore, the CXL device 1125 may effectively manage the data stored in the NAND flash NAND.

[0144] In some embodiments, the application servers 1110a, ..., 1110h may not include a storage device.

[0145] A network interface card (NIC) 1126 may be connected to the CXL switch 1123. The NIC 1126 may communicate with other storage servers 1120a, ..., 1120h or other application servers 1110a, ..., 1110h through a network (NT).

[0146] In some embodiments, the NIC 1126 may include a network interface card, a network adapter, etc. The NIC 1126 may be connected to the network NT through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 1126 may include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to the processor 1121 and / or the switch 1123 through the host bus interface. In some embodiments, the NIC 1126 may be integrated with at least one of the processor 1121, the switch 1123, or the CXL device 1125.

[0147] In some embodiments, the network NT may be implemented using Fibre Channel (FC), Ethernet, etc. In this case, FC as a medium for relatively high-rate data transmission may use an optical switch that provides high performance and high availability. Depending on the access method of the network NT, the storage server may be provided as a file storage device, a block storage device, or an object storage device.

[0148] In some embodiments, the network NT may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to an FC protocol (FC protocol, FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to an iSCSI (SCSI or Internet SCSI over TCP / IP) protocol. In some embodiments, the network NT may be a general network, such as a TCP / IP network. For example, the network NT may be implemented according to protocols such as FC over ethernet (FCoE), network attached storage (NAS), and NVMe over fabrics (NVMe-oF).

[0149] In some embodiments, at least one of the application servers 1110a, ..., and 1110h may store data stored in one of the storage servers 1120a, ..., and 1120h by a user or client requesting through the network NT. At least one of the application servers 1110a, ..., and 1110h may obtain data read from one of the storage servers 1120a, ..., and 1120h by a user or client requesting through the network NT. For example, at least one of the application servers 1110a, ..., and 1110h may be implemented as a web server or a database management system (DBMS).

[0150] In some embodiments, at least one of the application servers 1110a, ..., and 1110h may access a memory, CXL memory, or storage device included in another application server through the network NT, or may access a memory, CXL memory, or storage device included in the storage servers 1120a, ..., and 1120h through the network NT. Therefore, at least one of the application servers 1110a, ..., and 1110h may perform various operations on data stored in other application servers and / or storage servers. For example, at least one of the application servers 1110a, ..., and 1110h may execute a command to move or copy data between other application servers and / or storage servers. In this case, the data may be moved from the storage device of the storage server to the memory or CXL memory of the application server directly or through the memory or CXL memory of the storage server. For security or privacy, the data moved over the network may be encrypted.

[0151] In some embodiments, reference Figures 1 to 11 Each component described or a combination of two or more components may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), etc.

[0152] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the purview of the appended claims.

Claims

1. A computing system, comprising: a host configured to distribute and assign process data for each of a plurality of processes to a plurality of logical addresses, determine a valid bit indicating whether a corresponding one of the plurality of processes corresponding to a corresponding one of the plurality of logical addresses is being executed, and generate update information including the valid bit and the corresponding one of the plurality of logical addresses corresponding to the valid bit; as well as A storage device is configured to receive the update information from the host.

2. The computing system of claim 1, wherein: The storage device includes a plurality of non-volatile memories, and the storage device is further configured to perform garbage collection on the plurality of non-volatile memories based on the update information.

3. The computing system of claim 1, wherein: The host is further configured to generate the update information when the valid bit changes.

4. The computing system according to claim 1, further comprising: A CXL device, the CXL device being logically connected to the host via a CXL interface, wherein the CXL device comprises the storage device, and The CXL controller of the CXL device is configured to map a first logical address of a first type among the plurality of logical addresses to a storage address for the storage device.

5. The computing system of claim 4, wherein: The CXL device further includes a CXL memory including a volatile memory corresponding to a second logical address of a second type among the plurality of logical addresses, and the CXL controller is further configured to map the second logical address of the second type to a CXL memory address for the CXL memory.

6. The computing system of claim 5, wherein: The computing system further includes: A host memory is logically connected to the host and includes a volatile memory corresponding to a third logical address of a third type among the plurality of logical addresses.

7. The computing system of claim 6, wherein: The valid bit corresponds to the corresponding one of the plurality of logical addresses selected from a first logical address of the first type, a second logical address of the second type, or a third logical address of the third type.

8. The computing system of claim 1, wherein: The host is further configured to distribute and assign the process data to the plurality of logical addresses based on consistency and input / output speed of the process data.

9. A method for operating a computing system, the method comprising: distributing and assigning process data for each of a plurality of processes to a corresponding logical address of a plurality of logical addresses; assigning a valid bit indicating whether a corresponding process among the plurality of processes corresponding to a corresponding logical address among the plurality of logical addresses is being executed; generating update information including the valid bit and the corresponding logical address corresponding to the valid bit; mapping a first logical address of a first type among the plurality of logical addresses to a storage address for a storage device including a non-volatile memory; as well as Based on the update information, when the valid bit indicates that the process is not executing, performing garbage collection on the storage device at the storage address corresponding to the first logical address.

10. The operating method of the computing system according to claim 9, further comprising: A second logical address of a second type among the plurality of logical addresses is mapped to a CXL memory address for a CXL memory including a volatile memory.

11. The operating method of the computing system according to claim 10, further comprising: A third logical address of a third type among the plurality of logical addresses is mapped to a CXL memory address for a host memory including a volatile memory.

12. The operating method of the computing system according to claim 11, wherein: The generating of the update information includes: generating the update information including the valid bits corresponding to the corresponding logical addresses selected from the first logical address of the first type, the second logical address of the second type or the third logical address of the third type among the multiple logical addresses.

13. The operating method of the computing system according to claim 9, wherein: The distributing and allocating the process data to the plurality of logical addresses includes distributing and allocating the process data to the plurality of logical addresses based on consistency and input / output speed of the process data.

14. The operating method of the computing system according to claim 9, wherein: The generating the update information includes generating the update information when the valid bit changes.

15. A CXL device, comprising: a CXL storage device including a non-volatile memory corresponding to a first logical address of a first type among a plurality of logical addresses, the CXL storage device being configured to receive a valid bit indicating whether a process corresponding to the first logical address of the first type is being executed, and to perform garbage collection on the non-volatile memory based on the valid bit; as well as A CXL memory includes a volatile memory corresponding to a second logical address of a second type among the plurality of logical addresses.

16. The CXL device of claim 15, further comprising: A CXL controller is configured to map first logical addresses of the first type to CXL memory addresses for the CXL memory and to map second logical addresses of the second type to CXL memory addresses for the CXL memory.

17. The CXL device of claim 16, wherein: The CXL memory device includes a flash translation layer that maps the CXL memory device addresses to physical addresses of the non-volatile memory.

18. The CXL device of claim 17, wherein: The flash translation layer performs the garbage collection at the CXL storage device address of the CXL storage device corresponding to the valid bit indicating that the process is not executing.

19. The CXL device of claim 16, wherein: The CXL controller is further configured to receive the valid bit via a CXL interface.

20. The CXL device of claim 15, wherein: The CXL store is further configured to receive the valid bit when the execution of the process changes.

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