Distributed data path combination equivalence verification method and distributed server

Abstract

The invention provides a distributed data path combination equivalence verification method and a distributed server. The method comprises: rewriting two data path circuits to be verified to obtain two circuit description files with similar circuit structures; constructing a Miter circuit according to the circuit description file; performing random logic simulation on the Miter circuit to obtain internal potential equivalent nodes and storing them in an equivalent node queue; selecting potential equivalent node pairs from the equivalent node queue and extracting their fan-in cones, and constructing a sub-miter circuit according to two groups of fan-in cones; selecting a verification mode according to the density of XOR blocks in the sub-miter circuit and verifying the sub-miter circuit; if the verification is successful, merging the corresponding potential equivalent nodes and the corresponding fan-in cones, otherwise continuing to verify other potential equivalent node pairs until all potential equivalent nodes are verified; using a SAT solver to perform the final equivalence verification and return the verification result, so as to efficiently realize the data path combination equivalence verification.

Description

Technical Field

[0001] The present invention relates to the technical field of combinational circuit equivalence verification, and in particular to a distributed data path combinational equivalence verification method and a distributed server. Background Art

[0002] The combinatorial equivalence verification (CEC) problem of circuits is to verify the equivalence of two circuits. It is extremely important in the field of electronic design automation (EDA) in terms of synthesis, testing and other aspects. Among them, the datapath circuit contains a large number of multiplication, addition, multiplexer and other devices, making the related verification the biggest challenge in the field.

[0003] Miter circuit: A circuit with the same number of inputs and outputs can construct a corresponding miter circuit by directly connecting the corresponding input pins, connecting the outputs through an exclusive OR (XOR) gate, and then exporting them through an OR (OR) gate. Two circuits are equivalent if and only if the constructed miter circuit has an OR output of 0 under any input.

[0004] The propositional satisfiability problem (SAT) is a problem of determining whether a given propositional logic formula is consistent. The input is generally in the form of conjunctive normal form (CNF). The equivalence problem of two circuits, that is, whether the output of the miter circuit is always 0, can be naturally solved by using tseitin encoding CNF and reducing it to the SAT problem. The results of formula solution are either satisfiable ("SAT", which needs to be distinguished from the SAT problem above by context, and the solution results are marked with quotation marks) or unsatisfiable ("UNSAT"). A formula (parent problem) can be split into two sub-problems by assigning 0 and 1 to one of the variables respectively. If the parent problem is "UNSAT", then if both sub-problems are solved and return "UNSAT", it can be proved that the parent problem is "UNSAT". If the parent problem is "SAT", then if any of the two sub-problems finds a set of consistent assignments, it can be proved that the parent problem is "SAT".

[0005] The current mainstream method engine for CEC problem is mainly propositional satisfiability problem (SAT) solver. The existing solution framework for solving CEC problem has the following limitations:

[0006] SAT-sweeping framework: First, calculate the internal equivalent point pairs through logic simulation, and then use the SAT solver to verify the equivalence of these point pairs in topological order. If they are equivalent, merge the point pairs and the corresponding Fan-in cone; otherwise, continue verification. This technology is the most mainstream method at present. The related parallel technology mainly verifies the equivalence of different point pairs in parallel or verifies the equivalence of different output bits in parallel. For control circuits, it is more applicable because the verification of each equivalent point pair is relatively simple. However, the difficulty of the datapath circuit lies in the huge difficulty of verifying the point pairs where the multiplication and addition calculation units are located, and it is even impossible to give the verification results within a reasonable time. Therefore, relying solely on the SAT-sweeping framework cannot effectively solve the problem of datapath combination equivalence verification.

[0007] Algebraic methods: Model the circuit as a high-dimensional search space, model it as a set of Groebner bases, and model the output equivalence as a formula. Therefore, the final problem becomes a membership testing problem to determine whether the formula is in the space spanned by the Groebner base. This problem can verify some multipliers and adders relatively quickly, but it is limited to the verification of complete and simple computing units. It is not effective on incomplete computing units and units that have been comprehensively optimized. In addition, this type of method performs poorly on equivalence problems.

[0008] Method based on single encoding: This method encodes the original problem into a logical formula at one time and then submits it to SAT, BDD (binary decision tree problem), or ATPG problem for solution. Currently, it is less practical and weaker than the method based on SAT-sweeping.

[0009] Precise simulation: By exhaustively enumerating all possible inputs to determine whether the problem is equivalent or meets the constraints, it is only applicable to complex circuits with a small number of inputs. Relying solely on precise simulation cannot effectively solve the problem of data path combination equivalence verification. Summary of the invention

[0010] In view of the above problems, the present invention is proposed to provide a distributed data path combination equivalence verification method and a distributed server that overcome the above problems or at least partially solve the above problems.

[0011] One aspect of the present invention provides a distributed data path combination equivalence verification method, the method comprising:

[0012] S11, rewriting two data path circuit description files to be verified to obtain two circuit description files with similar circuit structures;

[0013] S12, constructing a Miter circuit file according to two circuit description files with similar circuit structures;

[0014] S13, performing random logic simulation on the Miter circuit file, obtaining potential equivalent nodes in the Miter circuit file, and storing the potential equivalent nodes belonging to the same equivalence class in the same equivalent node queue;

[0015] S14, for each equivalent node queue, select a potential equivalent node pair from it, extract the fan-in cone of the current potential equivalent node pair, and construct a sub-miter circuit file according to the fan-in cone of the current potential equivalent node pair;

[0016] S15, selecting a verification mode for verifying the sub-miter circuit file according to the density of the XOR block in the sub-miter circuit file and verifying the sub-miter circuit file, wherein the verification mode includes a Gray arrangement complete simulation mode and a distributed circuit satisfiability solution mode;

[0017] S16, if the verification is successful, then merge the corresponding potential equivalent nodes and the corresponding fan-in cone to achieve circuit simplification of the Miter circuit file, otherwise return to step S14 to continue verifying other potential equivalent node pairs in the current equivalent node queue until all potential equivalent nodes are verified;

[0018] S17, using a SAT solver to solve the equivalent simplified circuit finally updated in step S16, and determining whether the two data path circuits to be verified are equivalent according to the solution result.

[0019] Furthermore, before step S14, the method further includes:

[0020] Structural hashing technology is used to judge the fan-in cone structure of two groups of potential equivalent node pairs stored in different equivalent node queues. If the two groups of fan-in cone structures corresponding to the two groups of potential equivalent node pairs are consistent, the potential equivalent node pairs ranked later in the circuit topology order will be deleted from the queue.

[0021] Furthermore, the verification mode for verifying the sub-miter circuit file is selected according to the density of the XOR block in the sub-miter circuit file, including:

[0022] Based on the total number of CPU cores in the current distributed solution system , the number of XOR interconnected blocks k in the sub-miter circuit file and the size of each XOR interconnected block Calculate the first estimated verification run time :

[0023] ,in is the preset parameter;

[0024] Based on the total number of CPU cores in the current distributed solution system and the number of input leads that affect the cone Calculate the second estimated verification run time :

[0025] ;

[0026] if ,in is the preset parameter, the Gray arrangement complete simulation mode is selected, otherwise the distributed circuit satisfiability solution mode is selected.

[0027] Furthermore, when the sub-miter circuit file is verified using the Gray arrangement complete simulation mode, the verification method includes:

[0028] Get the input node bit width |PI| of the sub-miter circuit file, where the input node bit width |PI| is determined by the gray bit width , Node Width and SIMD bit width composition;

[0029] Get the number of CPU cores C that can be controlled in the distributed solution system, and calculate the node width based on the number of CPU cores C that can be controlled : ;

[0030] Get the machine instruction width when using SIMD technology to solve the problem serially , according to the machine instruction width Calculating SIMD bit width : , It is a preset parameter to improve utilization;

[0031] According to the input node width |PI|, node width and SIMD width Calculate Gray Bit Width : ;

[0032] According to the Gray bit width Generate Gray code input sequences for each simulation batch for simulation calculation and perform equivalence verification of potential equivalent node pairs, wherein the simulation batch currently executed by each CPU core has only one bit opposite to the Gray code input sequence of the previous simulation batch;

[0033] If the verification result returned in the simulation round of one of the CPU cores is verification failure, the potential equivalent node pair is not equivalent; if the verification results returned in the simulation rounds of all the CPU cores are verification success, the potential equivalent node pair is equivalent.

[0034] Furthermore, the method further comprises:

[0035] When performing equivalence verification of potentially equivalent node pairs, the value of each node in the previous simulation batch is recorded, and when calculating the next simulation batch, the different bits from the previous simulation round are found according to the Gray code sequence, and only the internal node values ​​of the fan-out influence cone related to the input bit are calculated and modified in the simulation.

[0036] Furthermore, when the distributed circuit satisfiability solution mode is adopted to verify the sub-miter circuit file, the verification method includes:

[0037] Start the master node in the distributed solution system , by the host machine node The master distributed controller starts the currently available slave machine nodes To run the slave node The slave distributed controller in;

[0038] The sub-miter circuit files to be solved are distributed to the slave distributed controllers through the master distributed controller, and the offline events of the slave distributed controllers are monitored in real time, so as to reconnect and synchronize the task relationship tree when the slave distributed controllers are offline;

[0039] Each machine node Start the main thread to synchronize the task relationship tree and solve the subtasks of the sub-miter circuit file verification task that the current machine node is responsible for. If it is detected that the current machine node has an unloaded slave thread, select a split point from the sub-miter circuit file to be verified to split the circuit verification task into two subtasks, and schedule the corresponding number of slave threads to solve the split subtasks.

[0040] During the task solving process, when any machine node After a thread has completed its task, all its related subtasks will be terminated. If all subtasks of its parent node have been solved, its parent task will be terminated. When the main thread of the host machine node completes the task and the result is "unsatisfiable", the task of the current machine node is solved, and the distributed controller of the current machine node will feedback the solution result to the parent machine node of the current machine node according to the synchronization task relationship tree; if the main thread of the host machine node completes the task and the result is "unsatisfiable", the task is solved. If any machine node If the solution result returned by any thread is "satisfiable", the task solution is completed and the result is returned.

[0041] Furthermore, the method further comprises:

[0042] If the number of idle slave threads on the current machine node is insufficient to allocate the split subtasks, the main thread will be suspended and wait for idle slave threads to be allocated;

[0043] While waiting for an unloaded slave thread, if an external machine node has an unloaded slave thread and requests a task to be solved, a corresponding subtask is selected and assigned to the external machine node for solution, and the suspended main thread is awakened. The selection rule of the subtask can be to assign the subtask with the smallest subsequent scoring value calculation model, that is, the subtask with the lowest degree of simplification and the greatest difficulty to be solved to the external machine node for solution.

[0044] Furthermore, the selecting of a split point from the sub-miter circuit file to be verified to split the circuit verification task into two sub-tasks includes:

[0045] A random sampling method is used to select split points from the sub-miter circuit file, and the value of each split point is assigned to 0 and 1 respectively to split the sub-miter circuit into two sub-circuits;

[0046] The difficulty of solving each subcircuit is judged according to the propagation cone of each subcircuit after splitting, and the split point where the subcircuit is easiest to solve after splitting is selected as the segmentation point.

[0047] Further, judging the difficulty of solving each subcircuit according to the propagation cone of each subcircuit after splitting, and selecting the split point of the subcircuit that is easiest to solve after splitting as the segmentation point, includes:

[0048] The number of gates without outgoing edges in the AIG AND NOT graph format description file of the subcircuit , the number of NOT gates on the outgoing edge , the number of non-gates on the input edge And the number of NOT gates on the input side Conduct gate node statistics;

[0049] According to the gate node statistics, the first forward propagation estimate and the first backward propagation estimate are calculated when the split point is assigned to 0:

[0050] The first forward propagation estimate is ,

[0051] The first backpropagation estimate is ,

[0052] According to the gate node statistics, the second forward propagation estimated value and the second backward propagation estimated value when the split point is assigned to 1 are calculated:

[0053] The second forward propagation estimate is ,

[0054] The second backpropagation estimate is ,

[0055] in, is the probability of a positive outgoing edge appearing in the subcircuit, and The distance between the current split point and the input and output;

[0056] The current split point is scored according to the first forward propagation estimated value, the first backward propagation estimated value, the second forward propagation estimated value, and the second backward propagation estimated value, and the split point with the highest score is selected as the segmentation point. The scoring value calculation model is as follows:

[0057] A=(A F,0 +A F,1 )(A B,0 +A B,1 ).

[0058] Furthermore, the method further comprises:

[0059] The estimated verification running time of the circuit to be verified before and after the circuit splitting is calculated according to the total number of CPU cores in the distributed cluster, the number of XOR blocks in the circuit to be verified before and after the circuit splitting, and the size of each XOR block;

[0060] The change in the expected verification run time of the circuit to be verified before and after the circuit is split As a scoring value The correction coefficient is used to correct the optimization score, and the split point with the highest optimization score is selected as the segmentation point.

[0061] In a second aspect, the present invention further provides a distributed server, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned distributed data path combination equivalence verification method when executing the computer program.

[0062] The distributed data path combination equivalence verification method and distributed server provided in the embodiment of the present invention propose a CEC verification method that deeply combines two computing power engines, namely the Gray arrangement complete simulation mode or the distributed circuit satisfiability solution mode. The present invention determines whether the Gray arrangement complete simulation mode or the distributed circuit satisfiability solution mode should be used for solution verification by the density of the XOR blocks in the sub-circuit to be verified involved in the data path combination equivalence verification process. It can use the large-scale computing power advantage on a distributed cluster to more efficiently verify the equivalence of two data path circuits, and has significant advantages in the verification problem of data path circuits.

[0063] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0065] Figure 1 A flow chart of a distributed data path combination equivalence verification method provided by an embodiment of the present invention;

[0066] Figure 2 A schematic diagram of the structure of a distributed circuit satisfiability solving system proposed in an embodiment of the present invention;

[0067] Figure 3 A schematic diagram of a task management tree proposed in an embodiment of the present invention;

[0068] Figure 4 A flow chart of solving and verifying using a distributed circuit satisfiability solving mode provided in an embodiment of the present invention;

[0069] Figure 5 A schematic diagram of the principle of a cutting point selection method based on propagation cone prediction provided by an embodiment of the present invention;

[0070] Figure 6 A flowchart of solving and verifying the solution using the Gray arrangement complete simulation mode provided in an embodiment of the present invention;

[0071] Figure 7 A schematic diagram of a Gray code input sequence when a Gray arrangement complete simulation is adopted in an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0073] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0074] Those skilled in the art will understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0075] In view of the defects of existing data path combinatorial equivalence verification (CEC) tools, the present invention provides a distributed data path combinatorial equivalence verification method and a distributed server. The distributed data path combinatorial equivalence verification method provided by the present invention is a CEC verification method that deeply combines two computing power engines: Gray arrangement complete simulation mode and distributed circuit satisfiability solution mode. Among them, the distributed circuit satisfiability system is a divide-and-conquer SAT algorithm based on the characteristics of the circuit, and the Gray arrangement precise simulation is an input exhaustive technology based on SIMD technology and carefully constructed simulation order. The present invention is aimed at the most difficult data path circuit combinatorial equivalence verification, is more efficient than existing algorithms, and has significant advantages in the verification problem of data path circuits.

[0076] Figure 1 The flowchart of the distributed data path combination equivalence verification method according to one embodiment of the present invention is schematically shown. Figure 1 The distributed data path combination equivalence verification method of the embodiment of the present invention specifically includes the following steps:

[0077] S11. Rewrite two data path circuit description files to be verified to obtain two circuit description files with similar circuit structures.

[0078] In this embodiment, the input of the verification system is a combinatorial equivalence circuit description file with two identical input and output numbers, including circuit description files C1 and C2, preferably in the form of an AIG. Specifically, by preprocessing the input circuit description files C1 and C2, reverse engineering technology is used to identify the addition links and partial products therein. If successfully identified, the partial products or multipliers therein are replaced with equivalent structures, exposing the leads missing in the circuit due to comprehensive optimization, and retaining the identified XOR gates and MAJ gates for subsequent calculations. This step rewrites C1 and C2 to increase the similarity of the two circuits as much as possible, and ultimately obtains two circuit description files with similar circuit structures.

[0079] S12. Construct a Miter circuit file based on two circuit description files with similar circuit structures.

[0080] In this embodiment, a Miter circuit file M1 is constructed by using two circuit description files with similar circuit structures obtained based on C1 and C2. The specific construction method of the Miter circuit is: for two circuits with the same number of inputs and outputs, a corresponding miter circuit can be constructed by directly connecting the corresponding input pins, connecting the outputs through an exclusive OR (XOR) gate, and then deriving through an OR (OR) gate. Two circuits are equivalent if and only if the output of the constructed miter circuit is 0 under any input.

[0081] S13, performing random logic simulation on the Miter circuit file, obtaining potential equivalent nodes in the Miter circuit file, and storing the potential equivalent nodes belonging to the same equivalence class in the same equivalent node queue.

[0082] Specifically, multiple groups of input vectors can be randomly generated for M1, which can be 100,000 groups, and the present invention does not limit this. Then, the assignment of internal nodes in M1 is calculated one by one by using logic simulation. Nodes with the same assignment in all rounds of simulation will be classified into an equivalence class, and all equivalence classes will be sorted from input to output according to the topological order of the circuit. The point pairs in the equivalence class are called potential equivalent nodes, and the potential equivalent nodes belonging to the same equivalence class are stored in the same equivalence node queue.

[0083] S14, for each equivalent node queue, select a potential equivalent node pair from it, extract the fan-in cone of the current potential equivalent node pair, and construct a sub-miter circuit file according to the fan-in cone of the current potential equivalent node pair. Specifically, the potential equivalent node pairs can be selected from the equivalent node queue in sequence or randomly from the equivalent node queue, and the present invention does not make specific limitations on this.

[0084] S15. Select a verification mode for verifying the sub-miter circuit file according to the density of the XOR blocks in the sub-miter circuit file and verify the sub-miter circuit file. The verification mode includes a Gray arrangement complete simulation mode and a distributed circuit satisfiability solution mode.

[0085] S16. If the verification is successful, the corresponding potential equivalent nodes and the corresponding fan-in cones are merged to achieve circuit simplification of the Miter circuit file. Otherwise, return to step S14 to continue verifying other potential equivalent node pairs in the current equivalent node queue until all potential equivalent nodes are verified.

[0086] Specifically, when the sub-miter circuit file is successfully verified, that is, the current potential equivalent node pair is equivalent, the potential equivalent node pair and the corresponding fan-in cone are merged in the miter circuit to achieve circuit simplification of the Miter circuit file. Furthermore, after circuit simplification, the new Miter circuit file can be re-simulated with random logic to improve the accuracy of the potential equivalent node pairs obtained subsequently.

[0087] S17, using a SAT solver to solve the equivalent simplified circuit finally updated in step S16, and determining whether the two data path circuits to be verified are equivalent according to the solution result.

[0088] In this embodiment, after the potential equivalent nodes belonging to the same equivalence class are stored in the same equivalent node queue, the potential equivalent node pairs will be selected from the above queue in turn for judgment. First, the present invention extracts the fan-in cone of the potential equivalent node pair and constructs a sub-miter circuit file for judgment. Then, according to the density of the XOR block in the sub-circuit, the "distributed circuit satisfiability solution mode" (abbreviated as SAT) or the "Gray arrangement complete simulation mode" (abbreviated as GES) is selected and the sub-miter circuit file is verified according to the selection result. If the verification is successful, the equivalent nodes and the corresponding fan-in cones are merged to realize the circuit simplification of the Miter circuit file to reduce the verification overhead of the subsequent potential equivalent node pairs. If the verification fails, the potential equivalent node pairs behind the queue will continue to be verified. After all potential equivalent node pairs are verified, the present invention uses the SAT solver to perform a final equivalent verification on the equivalent simplified circuit and returns the verification result.

[0089] The distributed data path combination equivalence verification method provided by the embodiment of the present invention proposes a CEC verification method that deeply combines two computing power engines, the Gray arrangement complete simulation mode or the distributed circuit satisfiability solution mode. The present invention determines whether the Gray arrangement complete simulation mode or the distributed circuit satisfiability solution mode should be used for solution verification by the density of the XOR blocks in the sub-circuit to be verified involved in the data path combination equivalence verification process. It can use the large-scale computing power advantage on a distributed cluster to more efficiently verify the equivalence of two data path circuits, and has significant advantages in the verification of data path circuits.

[0090] In one embodiment of the present invention, before selecting potential equivalent node pairs from the equivalent node queue, a structural hashing technique can be used to perform fan-in cone structure judgment on two groups of potential equivalent node pairs stored in different equivalent node queues. If the two groups of fan-in cone structures corresponding to the two groups of potential equivalent node pairs are consistent, the potential equivalent node pairs that are ranked later in the circuit topology order will be deleted from the queue.

[0091] Specifically, structural hashing technology can be used to perform fan-in cone structure judgment on two groups of potential equivalent node pairs stored in different equivalent node queues in turn. A certain degree of randomness can also be introduced to look ahead to a subsequent potential equivalent node pair, or even the last potential equivalent node, to quickly judge the equivalence of the entire circuit.

[0092] In this embodiment, the fan-in cones of the potential equivalent node pairs in the equivalent node queue will be pre-checked. If the structural hashing technology is used to find that the two sets of fan-in cone structures corresponding to the two sets of potential equivalent node pairs are consistent, the potential equivalent node pairs at the back of the queue will be deleted from the queue to prevent multiple equivalence judgments for the same structure.

[0093] In one embodiment of the present invention, in step S15, the verification mode for verifying the sub-miter circuit file is selected according to the density of the XOR block in the sub-miter circuit file, and the specific selection method is as follows:

[0094] According to the total number of CPU cores of the distributed cluster in the current distributed solution system , the number of XOR interconnected blocks k in the sub-miter circuit file and the size of each XOR interconnected block Calculate the first estimated verification run time :

[0095] ,in is the preset parameter;

[0096] The value of can be obtained by statistics of the actual time when the small circuit with the same structure is solved by SAT and GES, and the default value is 1;

[0097] According to the total number of CPU cores of the distributed cluster in the current distributed solution system and the number of input leads that affect the cone Calculate the second estimated verification run time :

[0098] ;

[0099] if , then the Gray arrangement complete simulation mode is selected, otherwise the distributed circuit satisfiability solution mode is selected. is the preset parameter, The value of can be obtained by statistically analyzing the actual time it takes to solve the isomorphic small circuit using SAT and GES respectively, and the default value is 0.15.

[0100] The identification of the XOR interconnection block is performed by identifying the XOR gates in the circuit, and combining the gates with direct connection relationship between the XOR gates together to form an XOR interconnection block.

[0101] Figure 2 A structural diagram of a distributed circuit satisfiability solution system is given. The distributed circuit satisfiability solution system is used to verify the sub-miter circuit file using a distributed circuit satisfiability solution mode. The distributed solution system will run a parallel solution system on each machine node and interact through a distributed controller. Among them, the machine node that directly interacts with the upper server is called the master node, and the other machine nodes controlled by the master node and indirectly interacting with the upper server through the master node are called slave nodes. The distributed controller is used to distribute and synchronize task solution results between machine nodes. If the connection is interrupted, the controller will also reconnect. The controller on each machine node will be responsible for interacting with the internal parallel engine. The main thread is responsible for maintaining the task management tree, synchronizing with the distributed controller of the current machine node, and monitoring the slave thread to perform the actual solution task. The slave thread is responsible for executing the actual solution task and returning the solution information.

[0102] Figure 3 The diagram of the task management tree is given. The main thread of the parallel engine of each machine node has a task management tree, which is synchronized through the distributed controller. The tree contains two types of tasks, internal tasks and external tasks. Indicates that external tasks are The root of the tree is special, and has two identifiers. Indicates which thread the task is solved on. Identifies the server that represents the source of the task solved by this node. If If the flag is empty, it further indicates that it is the main machine node. Indicates which thread the task is solved in. Indicates which external machine node the task is solved on, and the task is solved by the root thread of the external machine node. The task of any node on the tree is equal to the sum of the tasks of its child nodes, that is, the child node is split from the parent node. Solving the parent problem and its split child problems together can effectively avoid invalid lookahead. If the child problem under the parent problem is single, the split depth is deep, and the difficulty of the underlying child problems is significantly lower than that of the parent problem, the parent problem will also be suspended, that is, the computing resources will be given up and it will not be solved temporarily. Among them, the difficulty of the subproblem can be and the degree of reduction in the size of variables, It indicates the estimated verification running time of the circuit to be verified before and after circuit splitting, which is calculated based on the total number of CPU cores in the distributed cluster, the number of XOR blocks in the circuit to be verified before and after circuit splitting, and the size of each XOR block.

[0103] It is understandable that for the solution of the entire problem, if any thread returns SAT, then the original problem is SAT. If there is a cut set on the task management tree of the master node, and all nodes on it return UNSAT, then the original problem is UNSAT. The cut set is a set of points that separate the root of the tree and all leaf nodes.

[0104] like Figure 4 As shown, in one embodiment of the present invention, when the distributed circuit satisfiability solution mode is used to verify the sub-miter circuit file, the verification method specifically includes:

[0105] S21. Start the master node in the distributed solution system , by the host machine node The master distributed controller starts the currently available slave machine nodes To run the slave node A slave distributed controller in .

[0106] S22. The sub-miter circuit file to be solved is distributed to the slave distributed controller through the master distributed controller, and the offline events of the slave distributed controller are monitored in real time, so as to reconnect and synchronize the task relationship tree when the offline event occurs in the slave distributed controller.

[0107] S23. Each machine node Start the main thread to synchronize the task relationship tree and solve the subtasks of the sub-miter circuit file verification task that the current machine node is responsible for. If it is detected that the current machine node has an unloaded slave thread, select a split point from the sub-miter circuit file to be verified to split the circuit verification task into two subtasks, and schedule the corresponding number of slave threads to solve the split subtasks. The number of scheduled slave threads is determined according to the minimum value of the number of unsolved tasks in the current split and the number of CPU unloaded cores.

[0108] Furthermore, if the idle slave threads of the current machine node are insufficient to allocate the split subtasks, the main thread will be suspended and wait for idle slave threads to be allocated; while waiting for idle slave threads, if there are idle slave threads on an external machine node and request task solving, a corresponding subtask will be selected and allocated to the external machine node for solving, and the suspended main thread will be awakened. Specifically, the selection rule of the subtask can be to calculate the model with the smallest subsequent scoring value, that is, the subtask with the lowest degree of simplification and the greatest difficulty in solving is allocated to the external machine node for solving. That is, the most difficult subtask in the task pool queue of the current machine node is handed over for solving, and the task solution is waited for to be completed.

[0109] In one embodiment, the solution task is assigned to the main machine node After solving, the master node will start the available slave nodes , each machine will start the distributed controller, the master distributed controller will use the tree broadcast form to distribute the circuit file to be solved to the slave distributed controller, and when synchronization is required later, it will be distributed in the form of a task management tree and the actual solution file will be calculated in each machine to reduce communication overhead. If one of the machine nodes is offline, Will be responsible for reconnecting and synchronizing the task management tree. After initialization is completed, The main distributed controller will notify the internal main thread M to solve the problem. When starting, it will be based on the number of CPU cores in the current machine node Manage the internal parallel engine. First, the main thread will immediately start a thread , directly solve the main task that the machine node is responsible for. If there is an idle CPU, the main thread will occupy one of the CPUs, and use the propagation cone prediction technology to select the split point, and occupy the idle CPU to solve the subtask. If the split subtask cannot be arranged on a CPU, the main thread will be suspended and wait for an idle CPU to be allocated and then terminated. At this time, if an external node is unloaded and requests a task to be solved, the corresponding task will be thrown out and handed over to the external machine for solution. This process will wake up the suspended main thread and execute it through the distributed controller.

[0110] During the task solving process, when any machine node After a thread has finished solving a task, all its related subtasks will be terminated. If all subtasks of its parent node have been solved, its parent task will be terminated. The parent task will also be judged similarly. If the task is solved, it means that the task of this machine node is solved, and the distributed controller will feedback to the relevant machine according to the corresponding label. If the main node thread is solved, the task is solved.

[0111] When any slave node Thread When the solution task is completed and the solution result is "unsatisfiable", the task solution of the current machine node is completed, and the distributed controller of the current machine node will feedback the solution result to the relevant machine node, that is, the father machine node of the current machine node according to the synchronization task relationship tree; if the main thread of the main machine node completes the task solution and the result is "unsatisfiable", the task solution is completed.

[0112] Furthermore, if there is only one child task left of the parent task, and there is also one child task left of the child task, similarly longer links are generated. For example, by default, the total depth of these links exceeds Half of the link, any problem in the link is solved, the top parent task is solved, and then it will be solved through And / or the variable scale reduction degree measurement method measures the difficulty of the sub-problems, suspends the top parent task, and solves a problem with low difficulty on the link.

[0113] Furthermore, the above description assumes that the task to be solved is "UNSAT". In particular, if the solution result returned by one of the machine nodes is "SAT", the main thread is directly notified, all tasks are completed, and the results are returned. That is, if any machine node If the solution result returned by any thread is "SAT", the task solution is completed and the result is returned.

[0114] In this embodiment, the specific implementation method of selecting a split point from the sub-miter circuit file to be verified to split the circuit verification task into two sub-tasks is as follows: a split point is selected from the sub-miter circuit file by a random sampling method, and the value of each split point is assigned to 0 and 1 respectively to split the sub-miter circuit into two sub-circuits; the difficulty of solving each sub-circuit is judged according to the propagation cone of each sub-circuit after the split, and the split point that is easiest to solve after the split sub-circuit is selected as the split point.

[0115] Figure 5The schematic diagram of the principle of the cutting point selection method based on propagation cone prediction is shown. The problem to be solved can be expressed in the form of a circuit. The present invention uses a sampling method to select a split point from the circuit, assigns the value of the point to 0 and 1 respectively to split it into two sub-problems, and then further measures the influence area (influence cone) of the sub-problems after the split, and selects the point where the problem is easiest to solve after the split as the split point.

[0116] The present invention uses a technology based on propagation prediction when measuring the difficulty, that is, the product of the number of assignments can be roughly fixed forward (output side) and backward (input side) when the assignment is 0 or 1. The prediction is performed on the circuit structure.

[0117] The present invention will count the incoming and outgoing edges of the gate nodes under the AND-NOT graph (AIG), and count whether there is a NOT gate on the lead of the line. Specifically, the difficulty of solving each subcircuit is judged according to the propagation cone of each subcircuit after splitting, and the split point that is easiest to solve after splitting is selected as the segmentation point, which specifically includes:

[0118] The number of gates without outgoing edges in the AIG AND NOT graph format description file of the subcircuit , the number of NOT gates on the outgoing edge , the number of non-gates on the input edge And the number of NOT gates on the input side Conduct gate node statistics;

[0119] According to the gate node statistics, the first forward propagation estimate and the first backward propagation estimate are calculated when the split point is assigned to 0:

[0120] The first forward propagation estimate is ,

[0121] The first backpropagation estimate is ,

[0122] According to the gate node statistics, the second forward propagation estimated value and the second backward propagation estimated value when the split point is assigned to 1 are calculated:

[0123] The second forward propagation estimate is ,

[0124] The second backpropagation estimate is ,

[0125] in, is the probability of a positive outgoing edge appearing in the subcircuit, and The distance between the current gate, i.e. the current split point, and the input and output;

[0126] The current split point is scored according to the first forward propagation estimated value, the first backward propagation estimated value, the second forward propagation estimated value, and the second backward propagation estimated value, and the split point with the highest score is selected as the segmentation point. The scoring value calculation model is as follows:

[0127] A=(A F,0 +A F,1 )(A B,0 +A B,1 ).

[0128] Furthermore, the method further comprises:

[0129] The estimated verification running time of the circuit to be verified before and after the circuit splitting is calculated according to the total number of CPU cores in the distributed cluster, the number of XOR blocks in the circuit to be verified before and after the circuit splitting, and the size of each XOR block;

[0130] The change in the expected verification run time of the circuit to be verified before and after the circuit is split As a scoring value The correction coefficient is used to correct the optimization score, and the split point with the highest optimization score is selected as the segmentation point.

[0131] Exact complete simulation (EPS) is a technique that exhaustively enumerates all input assignments in lexicographic order and observes the circuit output. When solving in series, SIMD technology is used to compress multiple groups of inputs and execute them in one simulation to improve the inspection efficiency. The present invention uses the Gray arrangement complete simulation mode to verify the sub-miter circuit file, which can further improve the similarity of input assignments in two adjacent rounds of SIMD simulations to reduce the overhead caused by repeated calculations.

[0132] like Figure 6 As shown, in one embodiment of the present invention, when the sub-miter circuit file is verified using the Gray arrangement complete simulation mode, the verification method includes:

[0133] S31, obtaining the input node bit width |PI| of the sub-miter circuit file, wherein the input node bit width |PI| is determined by the Gray bit width , Node Width and SIMD bit width composition.

[0134] like Figure 7 As shown in the schematic diagram, taking 3-bit Gray coding as an example, there will be multiple bit differences between the upper and lower groups of bit vectors in the traditional lexicographical coding, while after Gray coding, there is only one bit difference between all adjacent bit vectors. Assume that, given a circuit with input |PI|, the present invention will divide it into Gray bit width , Node Width and SIMD bit width Three groups, where the node width The SIMD bit width is related to the number of CPU cores C that can be controlled in the distributed hardware system. The machine instruction width related.

[0135] S32, obtain the number of CPU cores C that can be currently controlled in the distributed solution system, and calculate the node width according to the number of CPU cores C that can currently be controlled : .

[0136] S33, obtain the machine instruction width when using SIMD technology to solve serially , according to the machine instruction width Calculating SIMD bit width : , These are preset parameters to improve utilization.

[0137] S34, according to the input node bit width |PI|, node bit width and SIMD bit width Calculate Gray Bit Width : .

[0138] S35, according to the Gray bit width Generate Gray code input sequences for each simulation batch for simulation calculation and perform equivalence verification of potential equivalent node pairs. The simulation batch currently executed by each CPU core has only one bit opposite to the Gray code input sequence of the previous simulation batch.

[0139] Furthermore, when performing equivalence verification of potentially equivalent node pairs, the value of each node in the previous simulation batch is recorded, and when calculating the next round of simulation batches, the different bits from the previous round of simulation are found according to the Gray code sequence, and only the internal node values ​​of the fan-out influence cone (propagation influence area) related to the input bit are calculated and modified in the simulation.

[0140] In this embodiment, the node bit width and SIMD bit width are calculated based on the number of CPU cores and the expected compressed instruction length of SIMD, and the Gray bit width is further calculated to represent the simulation batch that the CPU needs to execute, and the corresponding Gray code sequence is generated. For each CPU core, each batch that the algorithm needs to execute is opposite to the previous batch by only one bit. Therefore, the present invention will record the value of each node during the previous simulation, and in the next round of simulation calculation, only the internal node value of the actual impact area (fan-out impact cone) of the bit is calculated to reduce the actual calculation overhead. In actual calculations, the assignment of relevant areas is also calculated using SIMD technology.

[0141] Specifically, if the verification result returned in the simulation round of one of the CPU cores is verification failure, the potential equivalent node pair is not equivalent; if the verification results returned in the simulation rounds of all the CPU cores are verification success, the potential equivalent node pair is equivalent.

[0142] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0143] In addition, an embodiment of the present invention also provides a distributed server, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned distributed data path combination equivalence verification method when executing the computer program.

[0144] In addition, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above distributed data path combination equivalence verification method are implemented.

[0145] In this embodiment, if the distributed data path combination equivalence verification method is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device that can carry the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal and software distribution medium.

[0146] The distributed data path combination equivalence verification method and distributed server provided in the embodiment of the present invention propose a CEC verification method that deeply combines two computing power engines, namely the Gray arrangement complete simulation mode or the distributed circuit satisfiability solution mode. The present invention determines whether the Gray arrangement complete simulation mode or the distributed circuit satisfiability solution mode should be used for solution verification by the density of the XOR blocks in the sub-circuit to be verified involved in the data path combination equivalence verification process. It can use the large-scale computing power advantage on a distributed cluster to more efficiently verify the equivalence of two data path circuits, and has significant advantages in the verification problem of data path circuits.

[0147] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, any one of the claimed embodiments may be used in any combination.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A distributed data path combination equivalence verification method, characterized in that: The method comprises: S11, rewriting two data path circuit description files to be verified to obtain two circuit description files with similar circuit structures; S12, constructing a Miter circuit file according to two circuit description files with similar circuit structures; S13, performing random logic simulation on the Miter circuit file, obtaining potential equivalent nodes in the Miter circuit file, and storing the potential equivalent nodes belonging to the same equivalence class in the same equivalent node queue; S14, for each equivalent node queue, select a potential equivalent node pair from it, extract the fan-in cone of the current potential equivalent node pair, and construct a sub-miter circuit file according to the fan-in cone of the current potential equivalent node pair; S15, selecting a verification mode for verifying the sub-miter circuit file according to the density of the XOR block in the sub-miter circuit file and verifying the sub-miter circuit file, wherein the verification mode includes a Gray arrangement complete simulation mode and a distributed circuit satisfiability solution mode; the verification mode for verifying the sub-miter circuit file according to the density of the XOR block in the sub-miter circuit file includes: Based on the total number of CPU cores in the current distributed solution system , the number of XOR interconnected blocks k in the sub-miter circuit file and the size of each XOR interconnected block Calculate the first estimated verification run time : ， in is the preset parameter; Based on the total number of CPU cores in the current distributed solution system and the number of input leads that affect the cone Calculate the second estimated verification run time : ； if ,in If it is a preset parameter, the Gray arrangement complete simulation mode is selected, otherwise the distributed circuit satisfiability solution mode is selected; S16, if the verification is successful, then merge the corresponding potential equivalent nodes and the corresponding fan-in cone to achieve circuit simplification of the Miter circuit file, otherwise return to step S14 to continue verifying other potential equivalent node pairs in the current equivalent node queue until all potential equivalent nodes are verified; S17, using a SAT solver to solve the equivalent simplified circuit finally updated in step S16, and determining whether the two data path circuits to be verified are equivalent according to the solution result.

2. The method according to claim 1, characterized in that: Before step S14, the method further includes: Structural hashing technology is used to judge the fan-in cone structure of two groups of potential equivalent node pairs stored in different equivalent node queues. If the two groups of fan-in cone structures corresponding to the two groups of potential equivalent node pairs are consistent, the potential equivalent node pairs ranked later in the circuit topology order will be deleted from the queue.

3. The method according to any one of claims 1 to 2, characterized in that: When the Gray arrangement complete simulation mode is used to verify the sub-miter circuit file, the verification method includes: Get the input node bit width |PI| of the sub-miter circuit file, where the input node bit width |PI| is determined by the gray bit width , Node Width and SIMD bit width composition; Get the number of CPU cores C that can be controlled in the distributed solution system, and calculate the node width based on the number of CPU cores C that can be controlled : ; Get the machine instruction width when using SIMD technology to solve the problem serially , according to the machine instruction width Calculating SIMD bit width : , It is a preset parameter to improve utilization; According to the input node width |PI|, node width and SIMD width Calculate Gray Width : ; According to the Gray bit width Generate Gray code input sequences for each simulation batch for simulation calculation and perform equivalence verification of potential equivalent node pairs, wherein the simulation batch currently executed by each CPU core has only one bit opposite to the Gray code input sequence of the previous simulation batch; If the verification result returned in the simulation round of one of the CPU cores is verification failure, the potential equivalent node pair is not equivalent; if the verification results returned in the simulation rounds of all the CPU cores are verification success, the potential equivalent node pair is equivalent.

4. The method according to claim 3, characterized in that The method further comprises: When performing equivalence verification of potentially equivalent node pairs, the value of each node in the previous simulation batch is recorded, and when calculating the next simulation batch, the different bits from the previous simulation batch are found according to the Gray code sequence, and only the internal node values ​​of the fan-out influence cone related to the bits in the Gray code input sequence that are different from the previous simulation batch are calculated and modified in the simulation.

5. The method according to any one of claims 1-2, characterized in that: When the distributed circuit satisfiability solution mode is used to verify the sub-miter circuit file, the verification method includes: Start the master node in the distributed solution system , by the host machine node The master distributed controller starts the currently available slave machine nodes To run the slave node The slave distributed controller in; The sub-miter circuit files to be solved are distributed to the slave distributed controllers through the master distributed controller, and the offline events of the slave distributed controllers are monitored in real time, so as to reconnect and synchronize the task relationship tree when the slave distributed controllers are offline; Each machine node Start the main thread to synchronize the task relationship tree and solve the subtasks of the sub-miter circuit file verification task that the current machine node is responsible for. If it is detected that the current machine node has an unloaded slave thread, select a split point from the sub-miter circuit file to be verified to split the circuit verification task into two subtasks, and schedule the corresponding number of slave threads to solve the split subtasks. During the task solving process, when any machine node After a thread has completed its task, all its related subtasks will be terminated. If all subtasks of its parent node have been solved, its parent task will be terminated. When the main thread of the host node completes the task and the result is "unsatisfiable", the task of the current machine node is solved, and the distributed controller of the current machine node will feedback the solution result to the parent machine node of the current machine node according to the synchronization task relationship tree; if the main thread of the host machine node completes the task and the result is "unsatisfiable", the task is solved. If any machine node If the solution result returned by any thread is "satisfiable", the task solution is completed and the result is returned.

6. The method according to claim 5, characterized in that The method further comprises: If the number of idle slave threads on the current machine node is insufficient to allocate the split subtasks, the main thread will be suspended and wait for idle slave threads to be allocated; While waiting for an unloaded slave thread, if an external machine node has an unloaded slave thread and requests task solution, a subtask is selected and assigned to the external machine node for solution, and the suspended main thread is awakened.

7. The method according to claim 5, characterized in that The step of selecting a split point from the sub-miter circuit file to be verified to split the circuit verification task into two sub-tasks includes: A random sampling method is used to select split points from the sub-miter circuit file, and the value of each split point is assigned to 0 and 1 respectively to split the sub-miter circuit into two sub-circuits; The difficulty of solving each subcircuit is judged according to the propagation cone of each subcircuit after splitting, and the split point where the subcircuit is easiest to solve after splitting is selected as the segmentation point.

8. The method according to claim 7, characterized in that The step of judging the difficulty of solving each subcircuit according to the propagation cone of each subcircuit after splitting, and selecting the split point of the subcircuit that is easiest to solve after splitting as the segmentation point, includes: The number of gates without outgoing edges in the AIG AND NOT graph format description file of the subcircuit , the number of NOT gates on the outgoing edge , the number of non-gates on the input edge And the number of NOT gates on the input side Conduct gate node statistics; According to the gate node statistics, the first forward propagation estimate and the first backward propagation estimate are calculated when the split point is assigned to 0: The first forward propagation estimate is , The first backpropagation estimate is , According to the gate node statistics, the second forward propagation estimated value and the second backward propagation estimated value when the split point is assigned to 1 are calculated: The second forward propagation estimate is , The second backpropagation estimate is , in, is the probability of a positive outgoing edge appearing in the subcircuit, and The distance between the current split point and the input and output; The current split point is scored according to the first forward propagation estimated value, the first backward propagation estimated value, the second forward propagation estimated value, and the second backward propagation estimated value, and the split point with the highest score is selected as the segmentation point. The scoring value calculation model is as follows: 。 9. A distributed server, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 8 when executing the computer program.

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