Circuit for realizing BP neural network forward propagation
By designing a circuit including parameter configuration module, input layer module and single-layer neural network module, the problem that the existing BP neural network forward propagation implementation solution cannot run quickly, independently and miniaturize, and the BP neural network is realized. Rapid, independent and miniaturized operations in industrial environments.
Patent Information
- Application Number
- CN202311019031.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-14
- Publication Date
- 2025-02-21
AI Technical Summary
The existing BP neural network forward propagation implementation solution cannot work stably in a specific working environment quickly, independently and miniaturize.
A circuit including a parameter configuration module, an input layer module and a single-layer neural network module is designed to realize the forward propagation of the BP neural network by multiplying the accumulation and activation function units. This circuit uses ROM memory to store weight parameters and dynamically adjusts the structure and parameters of the neural network to adapt to the needs of different environments.
It realizes the rapid, independent and miniaturized operation of BP neural networks in industrial environments, and can dynamically adjust the neural network structure and parameters according to requirements to adapt to the needs of different environments.
Smart Images
Figure CN119494374A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of integrated circuit design, and in particular to a circuit for realizing forward propagation of a BP neural network. Background Art
[0002] BP neural network has important application scenarios in the fields of petroleum engineering and oilfield informationization, oilfield analytical instruments, and transformer fault diagnosis. It is suitable for various industrial environments that require the use of neural networks for regression or pattern recognition.
[0003] However, the existing BP neural network forward propagation implementation scheme is usually implemented by PC high-level language programming, which cannot work quickly, independently and miniaturizedly as a hardware entity in a specific working environment. Summary of the invention
[0004] The purpose of the present invention is to provide a BP neural network circuit that can adjust parameters such as the number of circuit inputs and outputs according to changes in the environment to meet user needs.
[0005] In order to solve the above technical problems, an embodiment of the present invention provides a circuit for realizing forward propagation of a BP neural network, comprising: a parameter configuration module, which is used to obtain the number of input interfaces of the input layer and the number of output interfaces of a single-layer neural network; an input layer module, which is used to obtain input data of the number of input interfaces; a single-layer neural network module, which has neurons of the number of output interfaces, and is used to perform linear multiplication and accumulation operations on the weight of each neuron and all the input data respectively, and then perform nonlinear conditioning on the output data of all neurons to obtain output data of the number of output interfaces.
[0006] Preferably, the single-layer neural network module includes: a neural network, which is used to configure a corresponding number of neuron resources and a corresponding number of storage units according to the number of output interfaces; a storage unit, which is used to store weight parameters of corresponding neurons; a multiplication-accumulation unit, which is used to perform multiplication-accumulation operations on each input data and the neuron weight corresponding to the current round of iteration during a single round of iteration, obtain the single-round multiplication-accumulation calculation result of the current single round of iteration and store it in the corresponding neuron resource, so that after completing the iteration of the number of output interfaces, each neuron resource stores the corresponding single-round multiplication-accumulation calculation result; an activation function unit, which is used to perform nonlinear processing on the single-round multiplication-accumulation calculation results of each neuron.
[0007] Preferably, the multiplication-accumulation unit carries out a single round of iteration according to the following steps: step S1, sending a read instruction to the storage unit corresponding to the neuron of the current single round of iteration; step S2, obtaining the neuron weight, and multiplying the neuron weight with the first input data to obtain the first multiplication-accumulation result; step S3, multiplying the neuron weight with the next input data, and adding the current multiplication operation result with the multiplication-accumulation result obtained in the previous clock cycle to obtain the multiplication-accumulation result of the current clock cycle; step S4, judging whether all input data have completed the multiplication-accumulation operation, if yes, taking the multiplication-accumulation result of the current clock cycle as the single round of multiplication-accumulation calculation result, if not, returning to step S3 to continue the multiplication-accumulation operation on the next input data.
[0008] Preferably, the storage address of the corresponding storage unit is stored in each neuron resource, wherein the read instruction contains the read address information of the current storage unit.
[0009] Preferably, the activation function unit is selected from one of a reLU function unit, a sigmoid function unit and a tanh function unit.
[0010] Preferably, the reLU function unit includes: a sign bit diagnostic device, which is used to perform sign bit judgment on the input data to use the current output result as the output data of the current unit.
[0011] Preferably, the sigmoid function unit includes: a first exponential operator, which is used to perform a first type of exponential operation on the input data; a first division operator, which is connected to the output end of the first exponential operator, and is used to first add one to the first type of exponential calculation result, and then calculate the inverse of the current addition result, so as to use the current calculation result as the output data of the current unit.
[0012] Preferably, the tanh function unit includes: a second exponential operator, which is used to perform a first type of exponential operation on the input data; a third exponential operator, which has the same input interface as the second exponential operator, and is used to perform a second type of exponential operation on the input data; an adder, which is used to add the result of the second type of exponential operation to the result of the first type of exponential operation; a subtractor, which is used to subtract the result of the second type of exponential operation from the result of the first type of exponential operation; and a second divider, which is used to divide the result of the subtraction operation by the result of the addition operation, so as to use the current calculation result as the output data of the current unit.
[0013] Preferably, the parameter configuration module is also used to obtain the number of input interfaces of the input layer, the configuration number of the single-layer neural network modules and the number of output interfaces of each single-layer neural network, wherein the circuit includes: at least two single-layer neural network modules, and the number of output interfaces of the previous single-layer neural network module matches the number of input interfaces of the next single-layer neural network module.
[0014] Preferably, the storage unit is constructed as a specific storage location of a memory, and the storage units in each single-layer neural network module are integrated in the same memory, wherein the parameter configuration module is also used to obtain a series of configuration parameters while also obtaining weight data about each neuron in each single-layer neural network module, and then write the weight data of each neuron in different single-layer neural network modules into the memory, and write the storage address of the corresponding storage unit into each neuron resource, and the memory adopts a ROM memory.
[0015] Compared with the prior art, one or more embodiments of the above scheme may have the following advantages or beneficial effects:
[0016] The present invention proposes a circuit for realizing forward propagation of BP neural network. The circuit is suitable for various industrial environments that need to use neural network for regression or pattern recognition. The circuit includes a single-layer neural network design module, which includes an input layer, a multiplication-accumulation operation, a ROM storage module and an output layer. In addition, the current circuit also includes an activation function design module. In actual use, N input vectors are first read out of the data stored in ROM and multiplied and accumulated by the single-layer neural network to obtain M outputs, and the M outputs are then obtained by the activation function operation module. M output vectors are obtained to realize the nonlinear BP neural network forward propagation circuit design. In addition, the forward propagation of the BP neural network in the present invention can also be constructed by more than multiple layers of operation modules, and the user can dynamically adjust the number of input and output neurons of the neural network, the weights or biases stored in the ROM and other parameters according to the needs, so as to meet the needs of different environments. The present invention has a simple structure, and the hardware circuit and the data stored in the ROM can be freely adjusted according to the required BP neural network structure, and the whole invention has strong portability; in addition, the clock cycle required for calculation will also vary according to the number of neurons in a specific circuit.
[0017] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0019] Figure 1 This is a schematic diagram of the overall structure of the first example of a circuit for implementing forward propagation of a BP neural network according to an embodiment of the present application.
[0020] Figure 2 This is a schematic diagram of the structure of a single-layer neural network module in a circuit for implementing forward propagation of a BP neural network according to an embodiment of the present application.
[0021] Figure 3 The present invention is a schematic diagram of the calculation flow of the sigmoid function unit in the circuit for implementing the forward propagation of the BP neural network according to an embodiment of the present application.
[0022] Figure 4 The present invention is a schematic diagram of the calculation flow of the tanh function unit in the circuit for implementing the forward propagation of the BP neural network according to an embodiment of the present application.
[0023] Figure 5 This is a schematic diagram of the overall structure of a second example of a circuit for implementing forward propagation of a BP neural network according to an embodiment of the present application. DETAILED DESCRIPTION
[0024] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.
[0025] In addition, the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in a sequence different from that here.
[0026] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.
[0027] BP neural network has important application scenarios in the fields of petroleum engineering and oilfield informationization, oilfield analytical instruments, and transformer fault diagnosis. It is suitable for various industrial environments that require the use of neural networks for regression or pattern recognition.
[0028] However, the existing BP neural network forward propagation implementation scheme is usually implemented by PC high-level language programming, which cannot work quickly, independently and miniaturizedly as a hardware entity in a specific working environment.
[0029] In order to solve the above technical problems, the embodiment of the present application proposes a circuit for realizing the forward propagation of a BP neural network. The circuit uses ROM storage, activation function and multiplication and accumulation module of the neural network to complete the design of the forward propagation circuit of the BP neural network. The present invention can also set parameters such as the number of network layers, parameters and number of neurons according to user needs, thereby adjusting the general structure of the BP network.
[0030] Figure 1 FIG. 1 is a schematic diagram of the overall structure of the first example of a circuit for implementing forward propagation of a BP neural network according to an embodiment of the present application. Figure 1 As shown, the circuit for implementing BP neural network forward propagation (also called “BP neural network circuit”) described in the embodiment of the present invention includes: a parameter configuration module 30, an input layer module 10 and a single-layer neural network module 20.
[0031] The parameter configuration module 30 is used to obtain configuration parameters inputted by the user. In one embodiment, the parameter configuration module 30 is used to obtain the number of input interfaces of the input layer and the number of output interfaces of the single-layer neural network.
[0032] When constructing the input layer module 10, a corresponding number of input interfaces will be generated according to the number of input interfaces. The input layer module 10 is used to obtain input data of the number of input interfaces.
[0033] When constructing the single-layer neural network module 20, the output end of the current single-layer neural network module is constructed to have output interfaces that match the number of output interfaces according to the number of output interfaces of the current single-layer neural network. In addition, the single-layer neural network module 20 has neurons with the number of output interfaces.
[0034] The single-layer neural network module 20 is used to first perform linear multiplication and accumulation operations on the weight of each neuron and all input data, and then perform nonlinear conditioning on all neuron output data to obtain output data of the number of output interfaces. In this way, the forward propagation of the single-layer network in the BP neural network is realized.
[0035] In another embodiment, in order to achieve the scalability of the hardware circuit, the BP neural network circuit described in the embodiment of the present invention includes at least two single-layer neural network modules 20 connected in series. Figure 5 FIG. 1 is a schematic diagram of the overall structure of a second example of a circuit for implementing forward propagation of a BP neural network according to an embodiment of the present application. Figure 5 As shown, the number of output interfaces of the previous single-layer neural network module 20 matches the number of input interfaces of the next single-layer neural network module 20.
[0036] Further, in the case where the BP neural network circuit includes at least two single-layer neural network modules, the parameter configuration module 30 described in the embodiment of the present invention is also used to obtain a series of configuration parameters including the number of input interfaces of the input layer, the configuration number of single-layer neural network modules and the number of output interfaces of each single-layer neural network.
[0037] Since the internal structure of each single-layer neural network module 20 connected in series is the same, the embodiment of the present invention only takes one single-layer neural network module 20 as an example to illustrate its internal structure.
[0038] Figure 2 Schematic diagram of the structure of a single-layer neural network module in a circuit for implementing forward propagation of a BP neural network according to an embodiment of the present application. Figure 2 As shown, in one embodiment, the single-layer neural network module 20 includes: a neural network 21, a storage unit 22, a multiplication and accumulation unit 23 and an activation function unit 24.
[0039] The neural network 21 is used to configure (form) a corresponding number of neuron resources 211 according to the number of output interfaces, and to configure (form) a corresponding number of storage units 22. Each neuron (resource) corresponds to a corresponding storage unit 22. The storage unit 22 is used to store the weight parameters of the corresponding neuron.
[0040] The multiplication-accumulation unit 23 is used to perform multiplication-accumulation operations on each input data and the neuron weight corresponding to the current round of iteration during a single round of iteration, obtain the single round of multiplication-accumulation calculation result of the current single round of iteration and store the single round of multiplication-accumulation calculation result in the corresponding neuron resource, so that after completing the output interface number round iteration, each neuron resource stores the corresponding single round of multiplication-accumulation calculation result.
[0041] In one embodiment, the multiplication-accumulation unit 23 performs each single-round iterative processing according to the following steps:
[0042] Step S1, sending a read instruction to the storage unit 22 corresponding to the neuron of the current single-round iteration;
[0043] Step S2, obtaining the neuron weight sent from the storage unit 22, and multiplying the neuron weight with the first input data to obtain a first multiplication-accumulation result;
[0044] Step S3, multiplying the current neuron weight by the next input data, and adding the current multiplication result to the multiplication-accumulation result obtained in the previous clock cycle to obtain the multiplication-accumulation result of the current clock cycle;
[0045] Step S4, determine whether all input data have completed the multiplication and accumulation operation. If so, use the multiplication and accumulation result of the current clock cycle as the single-round multiplication and accumulation calculation result. If not, return to step S3 to continue multiplication and accumulation operation processing on the next input data.
[0046] In one embodiment, the storage address of the corresponding storage unit 22 is stored in each neuron resource 211. The read instruction sent in step S1 includes the read address information of the storage unit 22 corresponding to the current single round iteration.
[0047] Specifically, for a single-layer neural network module with any number of inputs N and any number of outputs M, when performing forward propagation calculations, each clock cycle sends the corresponding read address information to the storage unit 22 corresponding to the current single-round iteration process, and the stored weight data (for example, weights or bias information) can be continuously obtained after two clock cycles. One clock cycle completes the product of an input neuron Ni and the current weight Wj, and calculates the cumulative addition (MAC) operation of the last multiplication output result, and the first output value is obtained after N clock cycles. Ni (i∈ (1, n)) is the i-th input of the single-layer neural network, such as Figure 1 As shown, Figure 1 Here, Mk (k∈(1, j)) is the kth neuron (resource) 211 in the neural network 21 in the single-layer neural network module. Since each neuron Mk is obtained by multiplying and accumulating all inputs and their weights, and each multiplication and accumulation operation takes one clock cycle, then n inputs require n clocks to obtain the output value of a neuron Mk (i.e., the result of a single-round multiplication and accumulation calculation). This is repeated M times, and the final cumulative result is the output result of the single-layer neural network, i.e., M single-round multiplication and accumulation calculation results are obtained.
[0048] Since the M rounds of multiplication and accumulation operations of the single-layer neural network module 20 result in a linear relationship and cannot adapt to all application scenarios, the embodiment of the present invention also requires a nonlinear module to simulate the nonlinear relationship.
[0049] Furthermore, the activation function unit 24 is used to perform nonlinear processing on the single-round multiplication and accumulation calculation results of each neuron, so as to obtain the output vectors of M single-layer neural network modules.
[0050] In the embodiment of the present invention, the activation function unit 24 is selected from one of the reLU function unit, the sigmoid function unit and the tanh function unit. In this way, the output result of the single-layer neural network designed in the embodiment of the present invention will be further activated by one of the activation functions reLU, sigmoid and tanh, and the design of the nonlinear neural network can be completed.
[0051] In one embodiment, the reLU function unit includes: a sign bit diagnostic device. The sign bit diagnostic device is used to perform sign bit judgment on the input data to use the current output result as the output data (output vector) of the current unit.
[0052] Figure 3 The figure is a schematic diagram of the calculation flow of the sigmoid function unit in the circuit for realizing the forward propagation of the BP neural network according to the embodiment of the present application. Figure 3 As shown, the sigmoid function unit includes: a first exponential operator and a first division operator.
[0053] Specifically, the first exponential operator is used to perform a first type of exponential operation on the input data (the result of each single round of multiplication and accumulation calculation). In one embodiment, the transfer function of the first type of exponential operation is: In the formula, x1 and y1 represent the input and output of the current function respectively.
[0054] The input end of the first divider is connected to the output end of the first exponential operator. The first divider is used to first add the first type of exponential calculation result, and then calculate the inverse of the current addition result, so as to use the current calculation result as the output data of the sigmoid function unit. In this way, the output data (output vector) of the M single-layer neural network modules are obtained.
[0055] Figure 4 Schematic diagram of the calculation flow of the tanh function unit in the circuit for implementing the forward propagation of the BP neural network in the embodiment of the present application. Figure 4 As shown, the tanh function unit includes: a second exponential operator, a third exponential operator, an adder operator, a subtractor operator and a second divider operator.
[0056] Specifically, the third exponential operator has the same input interface as the second exponential operator. The second exponential operator is used to perform a first type of exponential operation on the input data (each single round of multiplication and accumulation calculation results). The third exponential operator is used to perform a second type of exponential operation on the input data (each single round of multiplication and accumulation calculation results).
[0057] In one embodiment, the transfer function of the second type of exponential operation is: Where x2 and y2 represent the input and output of the current function respectively.
[0058] The input end of the adder is connected to the output end of the third exponential operator and the output end of the second exponential operator at the same time. The adder is used to add the second type of exponential operation result (i.e., the output data of the third exponential operator) to the first type of exponential operation result (i.e., the output data of the second exponential operator). The subtractor is used to subtract the second type of exponential operation result (i.e., the output data of the third exponential operator) from the first type of exponential operation result (i.e., the output data of the second exponential operator).
[0059] The input end of the second divider is connected to the output end of the adder and the output end of the subtracter at the same time. The second divider is used to divide the current subtraction result (i.e., the output data of the subtracter) by the current addition result (i.e., the output data of the adder) to use the current division result as the output data (output vector) of the tanh function unit.
[0060] In this way, the output data of M single-layer neural network modules are obtained.
[0061] In addition, it should be noted that the storage unit 22 described in the embodiment of the present invention is constructed as a specific storage location of the memory, and each storage unit 22 in each single-layer neural network module 20 is integrated in the same memory. Among them, the parameter configuration module 30 described in the embodiment of the present invention is also used to obtain a series of configuration parameters while also obtaining weight data about each neuron in each single-layer neural network module 20, and then write each neuron weight data in different single-layer neural network modules into the memory, and at the same time, write the storage address of the corresponding storage unit to each neuron resource.
[0062] In one embodiment, in order to ensure the stability of the configured BP neural network circuit, the memory described in the embodiment of the present invention adopts ROM memory.
[0063] The present invention discloses a circuit for realizing forward propagation of a BP neural network. The circuit is suitable for various industrial environments that require the use of neural networks for regression or pattern recognition. The circuit includes a single-layer neural network design module, which includes an input layer, a multiplication-accumulation operation, a ROM storage module, and an output layer. In addition, the current circuit also includes an activation function design module. In actual use, N input vectors are first read out of the data stored in the ROM and are subjected to multiplication-accumulation operations of the single-layer neural network to obtain M outputs, and the M outputs are then subjected to the activation function operation module to obtain M output vectors, thereby realizing the design of a nonlinear forward propagation circuit of a BP neural network. In addition, the forward propagation of the BP neural network in the present invention can also be constructed by constructing more than multiple layers of operation modules, and the user can dynamically adjust the number of input and output neurons of the neural network, the weights or biases stored in the ROM, and other parameters according to the needs, so as to meet the needs of different environments. The present invention has a simple structure, and the hardware circuit and the data stored in the ROM can be freely adjusted according to the required BP neural network structure, and the whole invention has strong portability; in addition, the clock cycle required for calculation will also vary according to the number of neurons in a specific circuit.
[0064] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person familiar with the technology within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
[0065] In the description of the present invention, unless otherwise specified, "plurality" means two or more than two; the orientations or positional relationships indicated by the terms "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0066] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0067] It should be understood that the embodiments disclosed in the present invention are not limited to the specific structures, processing steps or materials disclosed herein, but should be extended to equivalent substitutions of these features understood by ordinary technicians in the relevant field. It should also be understood that the terms used herein are only used for the purpose of describing specific embodiments and are not meant to be limiting.
[0068] The "one embodiment" or "embodiment" mentioned in the specification means that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "one embodiment" or "embodiment" appearing in various places throughout the specification do not necessarily refer to the same embodiment.
[0069] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.
Claims
1. A circuit for implementing forward propagation of a BP neural network, characterized in that: include: A parameter configuration module, which is used to obtain the number of input interfaces of the input layer and the number of output interfaces of the single-layer neural network; An input layer module, which is used to obtain input data of the number of input interfaces; A single-layer neural network module has neurons of the number of output interfaces, which is used to perform linear multiplication and accumulation operations on the weight of each neuron and all input data respectively, and then perform nonlinear conditioning on all neuron output data to obtain output data of the number of output interfaces.
2. The circuit according to claim 1, characterized in that The single-layer neural network module comprises: A neural network, configured to configure a corresponding number of neural resources and a corresponding number of storage units according to the number of output interfaces; A storage unit, which is used to store the weight parameters of the corresponding neurons; A multiplication-accumulation unit, which is used to perform multiplication-accumulation operations on each input data and the neuron weight corresponding to the current round of iteration during a single round of iteration, obtain the single round of multiplication-accumulation calculation result of the current single round of iteration and store it in the corresponding neuron resource, so that after completing the output interface number round of iteration, each neuron resource stores the corresponding single round of multiplication-accumulation calculation result; The activation function unit is used to perform nonlinear processing on the single-round multiplication and accumulation calculation results of each neuron.
3. The circuit according to claim 2, characterized in that The multiplication-accumulation unit performs a single round of iteration according to the following steps: Step S1, sending a read instruction to the storage unit corresponding to the neuron of the current single-round iteration; Step S2, obtaining a neuron weight, and multiplying the neuron weight with the first input data to obtain a first multiplication-accumulation result; Step S3, multiplying the neuron weight with the next input data, and adding the current multiplication result with the multiplication-accumulation result obtained in the previous clock cycle to obtain the multiplication-accumulation result of the current clock cycle; Step S4, determine whether all input data have completed the multiplication and accumulation operation. If so, use the multiplication and accumulation result of the current clock cycle as the single-round multiplication and accumulation calculation result. If not, return to step S3 to continue multiplication and accumulation operation processing on the next input data.
4. The circuit according to claim 3, characterized in that The storage address of the corresponding storage unit is stored in each neuron resource, wherein the read instruction contains the read address information of the current storage unit.
5. The circuit according to any one of claims 2 to 4, characterized in that: The activation function unit is selected from one of a reLU function unit, a sigmoid function unit and a tanh function unit.
6. The circuit according to claim 5, characterized in that The reLU function unit includes: The sign bit diagnostic device is used to perform sign bit judgment on the input data so as to use the current output result as the output data of the current unit.
7. The circuit according to claim 5, characterized in that The sigmoid function unit includes: A first exponential operator, which is used to perform a first type of exponential operation on the input data; The first divider is connected to the output end of the first exponential operator and is used to first add the first type of exponential calculation result and then calculate the reciprocal of the current addition result to use the current calculation result as the output data of the current unit.
8. The circuit according to claim 5, characterized in that The tanh function unit comprises: A second exponential operator, which is used to perform a first type of exponential operation on the input data; a third exponential operator, which has the same input interface as the second exponential operator and is used to perform a second type of exponential operation on the input data; an adder for adding the result of the second type of exponential operation to the result of the first type of exponential operation; a subtractor for subtracting a result of the second type of exponential operation from a result of the first type of exponential operation; The second divider is used to divide the subtraction result and the addition result to use the current calculation result as the output data of the current unit.
9. The circuit according to any one of claims 2 to 8, characterized in that: The parameter configuration module is also used to obtain the number of input interfaces of the input layer, the configuration number of the single-layer neural network modules and the number of output interfaces of each single-layer neural network, wherein the circuit includes: at least two single-layer neural network modules, and the number of output interfaces of the previous single-layer neural network module matches the number of input interfaces of the next single-layer neural network module.
10. The circuit according to claim 9, characterized in that The storage unit is constructed as a specific storage location of the memory, and the storage units in each single-layer neural network module are integrated in the same memory, wherein the parameter configuration module is also used to obtain a series of configuration parameters while also obtaining weight data about each neuron in each single-layer neural network module, and then write the weight data of each neuron in different single-layer neural network modules into the memory, and write the storage address of the corresponding storage unit into each neuron resource, and the memory adopts ROM memory.