An in-memory computing circuit based on BNN algorithm acceleration

Abstract

The present invention relates to an in-memory computing circuit based on BNN algorithm acceleration, belonging to the field of integrated circuit technology, and solves the problems of large circuit area, high energy consumption, and low memory and computing energy efficiency in the prior art. The circuit includes: selecting a first algorithm network and a second algorithm network in a flexible RRAM memory and computing array; inputting multiple rows of data into the first algorithm network and a multiplication and accumulation module, obtaining a multiplication and accumulation result and inputting it into a shifter; the shifter shifts the multiplication and accumulation result, outputs the shifted result to an adder and subtractor, obtains a sum calculation result and outputs it to a comparator; the comparator performs binary processing on the sum calculation result and outputs it to the second algorithm network, calculates the output column cumulative current again, and sends it to a maximum value comparison output module; the maximum value comparison output module determines that the column with the maximum value of the column sum is the classification result. While maintaining the accuracy of the original network, it achieves a significant reduction in the required circuit area, reduces energy consumption, and improves the energy efficiency of the overall memory and computing circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an in-memory computing circuit based on accelerated implementation of a binary neural network (BNN) algorithm. Background Art

[0002] With the rapid development of deep neural network technology in artificial intelligence, the high memory consumption and low computational speed of current floating-point (real-valued) neural networks need to be addressed urgently. Developers hope to apply neural network models to embedded devices or mobile scenarios to solve real-time issues and enable on-the-go use. Binarized neural networks (BNNs) have emerged as a result.

[0003] A binarized neural network (BNN) uses only +1 and -1 values ​​to represent weights and activations. Compared to full-precision neural networks, convolution operations can be implemented using a simple combination like XNOR+popcount instead of float32 multiplication and accumulation. This saves significant memory and computation, greatly facilitating model deployment on resource-constrained devices and making it ideal for edge computing applications. However, due to the limited amount of information that can be expressed in binary values, BNN model accuracy has always been significantly lower than full-precision models. Current research on BNNs focuses on two major areas: improving BNN accuracy and effectively deploying them on low-power, resource-constrained platforms. Traditional von Neumann architectures are limited by the "memory wall bottleneck," resulting in high power consumption and slow speed. In-memory computing technology, however, enables more efficient computing systems and reduces power consumption. Since convolution operations, which involve numerous multiplications and additions, are a core component of deep learning algorithms, in-memory computing and logic are well-suited for deep neural network applications in artificial intelligence (AI), such as BNNs, and AI-based big data technologies.

[0004] Currently, RRAM memory computing arrays mostly implement BNN algorithms through XNOR-based operations, which require the use of 2T2R structured RRAM arrays and peripheral circuits. Therefore, in order to further improve energy efficiency without losing accuracy, an in-memory computing circuit based on BNN algorithm acceleration is urgently needed. Summary of the Invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide an in-memory computing circuit based on BNN algorithm acceleration to solve the problems of large circuit area, high energy consumption and low memory computing efficiency in existing circuits.

[0006] On the one hand, an embodiment of the present invention provides an in-memory computing circuit based on BNN algorithm acceleration, the circuit comprising: a flexible RRAM memory computing array, a multiplication and accumulation module, a shifter, a comparator, and a maximum comparison output module;

[0007] According to the BNN network structure and input data, two areas are selected in the flexible RRAM storage and computing array as the first algorithm network and the second algorithm network;

[0008] Input multiple rows of data of each bit into the first algorithm network and the multiplication-accumulation module. The first algorithm network outputs the accumulated current of each column of the storage and calculation unit to the multiplication-accumulation module. The multiplication-accumulation module obtains the multiplication-accumulation result of each column based on the multiple rows of data and the accumulated current of each column, and inputs the multiplication-accumulation result of each column into the shifter.

[0009] The shifter shifts the multiplication and accumulation results of each column by the corresponding number of bits according to the bits of each row of input data, and outputs the shifted results to the adder-subtractor in the multiplication and accumulation module. The adder-subtractor adds and calculates the shifted results of different bits of each column, and outputs the summed calculation results of each column to the comparator;

[0010] The comparator performs binarization processing on the sum calculation results of each column to obtain a binarized result, outputs the binarized result to the second algorithm network, and calculates and outputs the accumulated current of each column again in the second algorithm network, and sends it to the maximum value comparison output module;

[0011] The maximum value comparison output module determines the maximum value of the accumulated current in each column, and the column where the maximum value is located is the classification result.

[0012] Furthermore, the multiplication and accumulation module further includes: a popcount module and a multiplier;

[0013] The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier;

[0014] The multiplier multiplies the number of 1s by a fixed value β and sends the product to the adder-subtractor;

[0015] The adder-subtractor subtracts the product result from the digital signal to obtain a matrix multiplication and addition result, and sends the result to the shifter.

[0016] Furthermore, the circuit further comprises: a first column multiplexer MUX, a first analog-to-digital converter ADC;

[0017] The first column multiplexer MUX sequentially selects each column of the storage and calculation unit of the first algorithm network, and sends the accumulated current of the selected column of storage and calculation unit to the first analog-to-digital converter ADC;

[0018] The first analog-to-digital converter ADC converts the accumulated current output by the first algorithm network into a digital signal and sends it to the adder-subtractor.

[0019] Furthermore, the circuit further comprises: a second column multiplexer MUX, a second analog-to-digital converter ADC;

[0020] The second column multiplexer MUX sequentially selects each column of the storage and calculation unit of the second algorithm network, and sends the accumulated current of the selected column of storage and calculation unit to the second analog-to-digital converter ADC;

[0021] The second analog-to-digital converter ADC converts the accumulated current output by the second algorithm network into a digital signal and sends it to the maximum value comparison output module.

[0022] Furthermore, the circuit further comprises: a first data buffer module, a second data buffer module and a third data buffer module; all of which are used for temporary storage and integration of data;

[0023] The first data buffer module receives the digital signal output by the first analog-to-digital converter ADC, buffers the digital signal, and then outputs the digital signal to the adder-subtractor;

[0024] The second data buffer module receives the shift result output by the shifter, buffers it, and then outputs it to the adder-subtractor;

[0025] The third data buffer module receives the binarization result output by the comparator, buffers it, and then outputs it to the second algorithm network.

[0026] Furthermore, the adder-subtractor implements addition or subtraction operations through a control signal sent by the FPGA.

[0027] Furthermore, according to the bit positions of the input multiple rows of data, the multiplication and addition result is shifted left by the corresponding number of bits in the shifter; for the multiplication and accumulation result corresponding to the i-th multiple rows of data, the multiplication and accumulation result is shifted left by i bits in the shifter; wherein 0≤i≤7.

[0028] Furthermore, a threshold is preset in the comparator. When the sum calculation result is greater than the threshold, the comparator outputs 1, and when the sum calculation result is less than the threshold, the comparator outputs 0.

[0029] Furthermore, the flexible RRAM storage and computing array includes n×m storage and computing units;

[0030] The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence. The bit lines BL are used to output the calculation results of the storage and calculation units in this column.

[0031] Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

[0032] Furthermore, the transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the memristor is an RRAM;

[0033] The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage and calculation unit, the drain is connected to the bit line BL of the storage and calculation unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage and calculation unit.

[0034] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0035] 1. This application uses a flexible RRAM memory and computing array with a 1T1R unit structure. The indium gallium zinc oxide thin-film transistor (IGZO TFT) and memristor in the 1T1R unit structure are both flexible RRAM devices. Compared with the traditional 2T2R structure, this application halves the memory and computing array area without affecting the computing accuracy, further improving energy efficiency. Its flexible characteristics make it more suitable for use in creating electronic skin.

[0036] 2. Peripheral circuits such as the analog-to-digital converter (ADC), popcount module, multiplier, and subtractor can fully calculate the entire BNN algorithm and can input multiple bits, thereby improving the computational precision and accuracy of the hardware circuit implementation of the BNN algorithm.

[0037] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0039] Figure 1 The overall circuit architecture diagram provided by the present invention;

[0040] Figure 2 The data flow chart for implementing the BNN algorithm provided by the present invention;

[0041] Figure 3 This is a circuit diagram of the flexible RRAM storage and computing array;

[0042] Figure 4 The calculation coding table of the RRAM storage array based on the 1T1R structure. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0044] A specific embodiment of the present invention discloses an in-memory computing circuit based on BNN algorithm acceleration implementation, such as Figure 1 The circuit includes: a flexible RRAM storage and calculation array, a multiplication and accumulation module, a shifter, a comparator, and a maximum value comparison output module;

[0045] According to the BNN network structure and input data, two areas are selected in the flexible RRAM storage and computing array as the first algorithm network and the second algorithm network;

[0046] Input multiple rows of data of each bit into the first algorithm network and the multiplication-accumulation module. The first algorithm network outputs the accumulated current of each column of the storage and calculation unit to the multiplication-accumulation module. The multiplication-accumulation module obtains the multiplication-accumulation result of each column based on the multiple rows of data and the accumulated current of each column, and inputs the multiplication-accumulation result of each column into the shifter.

[0047] The shifter shifts the multiplication and accumulation results of each column by the corresponding number of bits according to the bits of each row of input data, and outputs the shifted results to the adder-subtractor in the multiplication and accumulation module. The adder-subtractor adds and calculates the shifted results of different bits of each column, and outputs the summed calculation results of each column to the comparator;

[0048] The comparator performs binarization processing on the sum calculation results of each column to obtain a binarized result, outputs the binarized result to the second algorithm network, and calculates and outputs the accumulated current of each column again in the second algorithm network, and sends it to the maximum value comparison output module;

[0049] The maximum value comparison output module determines the maximum value of the accumulated current in each column, and the column where the maximum value is located is the classification result.

[0050] Specifically, according to the network structure of the BNN algorithm and the amount of input data, two areas are selected in the flexible RRAM storage and computing array as the first algorithm network and the second algorithm network.

[0051] Specifically, the rows and columns of the first algorithm network are determined according to the number of rows of input data and the size of the hidden layer, and then the size of the first algorithm network is determined. The rows and columns of the second algorithm network are determined according to the size of the hidden layer and the number of output data of the output layer, and then the size of the second algorithm network is determined.

[0052] Furthermore, the flexible RRAM storage and computing array includes n×m storage and computing units;

[0053] The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence. The bit lines BL are used to output the calculation results of the storage and calculation units in this column.

[0054] Each of the storage and computing units has a 1T1R structure, including a transistor and a memristor.

[0055] Preferably, Figure 3 As shown, the flexible RRAM memory array has a size of 64*64 and a total capacity of 4Kb; it cooperates with peripheral circuits such as word line decoders, bit line decoders, and source line decoders to form a multiplication and addition calculation unit. The word line decoder, bit line decoder, and source line decoder decode the address signal given by the external FPGA to cooperate with it to complete read and write operations.

[0056] Specifically, the transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the memristor is an RRAM;

[0057] The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage and calculation unit, the drain is connected to the bit line BL of the storage and calculation unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage and calculation unit.

[0058] Specifically, the working modes of the flexible RRAM storage and computing array include a write weight mode and an inference working mode.

[0059] Specifically, when the bit line BL or the source line SL is connected to the write voltage Vw, the working mode of the flexible RRAM memory computing array is the write weight mode; when the bit line BL is connected to the read voltage Vr, the working mode of the flexible RRAM memory computing array is the inference working mode.

[0060] Specifically, the input voltages of the word lines, bit lines, and source lines connected to the array are controlled by the peripheral FPGA, that is, the word line WL is connected to a high level or a low level to control the on and off of the transistor, thereby selecting whether the current storage unit is selected; when the word line WL is connected to a high level, the transistor is turned on, that is, the storage unit is selected; when the word line WL is connected to a low level, the transistor is not turned on, that is, the storage unit is not selected.

[0061] Specifically, in the write weight working mode, the connection voltage of the word line WL, the bit line BL and the source line SL is controlled to change the resistance state of the memristor RRAM, thereby achieving weight writing.

[0062] Specifically, when the word line WL is connected to a high level, the bit line BL is connected to a write voltage Vw, and the source line SL is grounded, the conductance state of the memristor RRAM is a low resistance state LRS, and its weight is assigned to β+1;

[0063] When the word line WL is connected to a high level, the bit line BL is grounded, and the source line SL is connected to a write voltage Vw, the conductance state of the memristor RRAM is a high resistance state HRS, and its weight is assigned to β-1;

[0064] When the word line WL is connected to a low level, it indicates that the memristor RRAM is not selected, and the resistance state of the memristor RRAM remains unchanged.

[0065] In the write weight mode, the high and low resistance states of the RRAM are set by controlling the write voltage Vw of the storage and calculation unit and the on and off of the transistor, thereby completing the deployment of the weight in the RRAM array; the output of the source line SL and the bit line BL is grounded or connected to the write voltage, and the word line WL controls the on and off of the transistor to control the weight writing of the RRAM in the storage and calculation unit. For example, when the word line WL <0> When the source line SL is connected to the ground, and the bit line BL is connected to the write voltage, the RRAM is programmed to a low resistance state.

[0066] Specifically, in the write weight mode and inference working mode, because the memristor RRAM is a non-volatile device, after the write weight mode completes the resistance state setting of the RRAM, the resistance state of the memristor RRAM is fixed and will not change unless a new programming voltage is applied to the word line WL, the bit line BL and the source line SL.

[0067] Specifically, the write weight mode adopts a half voltage method, the write voltage Vw is greater than the threshold voltage of the memristor RRAM, and the half write voltage Vw is less than the threshold voltage of the memristor RRAM to ensure that the state of the unselected memristor RRAM remains unchanged.

[0068] Specifically, in the inference working mode, the bit line BL is connected to the read voltage Vr and the source line SL is grounded. The input of the storage unit is determined according to whether the bit line WL is connected to a high level or a low level. The current value output by the storage unit is used as the product of the storage unit input and the memristor RRAM weight. The current output by each storage unit in each column of storage units is merged in the bit line corresponding to the storage unit in the column, so that the bit line output is the sum of the products of each unit in the column of storage units.

[0069] Specifically, such as Figure 4 As shown, when the word line WL is connected to a high level and the resistance state of the memristor RRAM is a high resistance state HRS, the input of the memory computing unit is 1 and the output is a low current I L , low current I L The value of is β-1;

[0070] When the word line WL is connected to a high level and the resistance state of the memristor RRAM is a low resistance state LRS, the input of the memory computing unit is 1 and the output is a high current I H , high current I H The value of is β+1;

[0071] When the word line WL is connected to a low level, the indium gallium zinc oxide thin film transistor IGZO TFT is disconnected, the storage and calculation unit is not connected, the input of the storage and calculation unit is 0, and the output current of the storage and calculation unit is 0.

[0072] In the inference working mode, the entire RRAM array can realize the calculation function of multiplication and addition; the word line WL is used to control the on and off of the TFT transistor to realize the input: when the word line WL is connected to a high level, the TFT transistor is turned on, that is, the storage unit is selected, indicating that the input is 1; when the word line WL is connected to a low level, the transistor is turned off, that is, the unit is not connected, indicating that the input is 0. The source line SL is connected to the ground terminal, and the bit line BL is connected to the read voltage Vr to obtain the corresponding accumulated current, which is the multiplication and addition result. The high and low resistance states of RRAM after programming represent the weight distribution. When a bit line BL of the RRAM array is selected, a current I will be generated according to different high resistance or low resistance states. H or I L For example, when the word line WL <0> When the RRAM is in a high-resistance state, the memory unit generates a reference current I L , indicating that the calculation result of this cell is β-1 (β>1). This is repeated for an entire column of memory-calculation cells. The accumulated current obtained at the output bit line BL is the multiplication and addition result of the entire column of memory-calculation cells. This allows the use of only one TFT transistor and one RRAM as a memory-calculation cell, thus forming a memory-calculation array.

[0073] Specifically, the β>1, the present application is equivalent to a deformed binary calculation, the input of the word line WL is to control whether the transistor is turned on or not, and the high resistance state and low resistance state of the memristor RRAM are determined by controlling the voltage connected to the bit line BL and the source line SL in the write weight mode. Since the high resistance state and the low resistance state are actually positive values, the low resistance state and the high resistance state are encoded as β+1 and β-1 respectively. In the inference working mode, the output also changes accordingly, and the output is also a binary high current and low current.

[0074] Furthermore, the multiplication and accumulation module further includes: a popcount module and a multiplier;

[0075] The popcount module receives multiple lines of input and obtains the number of 1s in the multiple lines of input, and outputs the number of 1s to the multiplier;

[0076] The multiplier multiplies the number of 1s by a fixed value β and sends the product to the adder-subtractor;

[0077] The adder-subtractor subtracts the product result from the digital signal to obtain a matrix multiplication and addition result, and sends the result to the shifter;

[0078] Specifically, the function of the multiplier is to multiply the input by a fixed β value to solve the weight setting problem, where the β value is determined by the performance of the RRAM storage array.

[0079] For example, when the matrix multiplication is [1,0,1,0,1]*[+1,+1,-1,-1,-1], that is, the multiple rows of input are [1,0,1,0,1], the weight of a column of the RRAM storage array is [+1,+1,-1,-1,-1], the multiplication and addition result is -1, the corresponding multiple rows of input of the RRAM storage array are 10101, and the resistance states of the input corresponding RRAM units are β+1, β+1, β-1, β-1, β-1, respectively. Then, the accumulated current output by the RRAM storage array in this column is input to the multiplexer, and the multiplexer selects the accumulated current of the column of the storage array and outputs it to the analog-to-digital converter ADC. After analog-to-digital conversion, it outputs a current digital signal of 3β-1 to the adder-subtractor. The popcount module output is 3, and the multiplier output is 3β. Then the adder-subtractor performs a subtraction operation and outputs -1. It can be seen that this scheme is completely consistent with the original multiplication and addition result.

[0080] Furthermore, the circuit further comprises: a first column multiplexer MUX, a first analog-to-digital converter ADC;

[0081] The first column multiplexer MUX sequentially selects each column of the storage and calculation unit of the first algorithm network, and sends the accumulated current of the selected column of storage and calculation unit to the first analog-to-digital converter ADC;

[0082] The first analog-to-digital converter ADC converts the accumulated current output by the first algorithm network into a digital signal and sends it to the adder-subtractor.

[0083] Furthermore, the adder-subtractor implements addition or subtraction operations through a control signal sent by the FPGA.

[0084] Specifically, the adder-subtractor module uses a carry-lookahead adder structure and can perform addition and subtraction of two signed numbers. The addition or subtraction is controlled by the control signal provided by the FPGA. Because the RRAM storage array weight encoding uses all-positive number encoding during hardware implementation, it is actually greater than the weight value in the actual algorithm. Therefore, the multiplication and addition result from the RRAM array needs to be subtracted from the output result of the popcount module to make a correction, and subtraction is performed at this time; this implementation method splits the input into each bit input, so the results of each bit need to be added to obtain the calculation result of the complete input, and addition is performed at this time.

[0085] Furthermore, the circuit further comprises: a first data buffer module, a second data buffer module and a third data buffer module; all of which are used for temporary storage and integration of data;

[0086] The first data buffer module receives the digital signal output by the first analog-to-digital converter ADC, buffers the digital signal, and then outputs the digital signal to the adder-subtractor;

[0087] The second data buffer module receives the shift result output by the shifter, buffers it, and then outputs it to the adder-subtractor;

[0088] The third data buffer module receives the binarization result output by the comparator, buffers it, and then outputs it to the second algorithm network.

[0089] Furthermore, the circuit further comprises: a second column multiplexer MUX, a second analog-to-digital converter ADC;

[0090] The second column multiplexer MUX sequentially selects each column of the storage and calculation unit of the second algorithm network, and sends the accumulated current of the selected column of storage and calculation unit to the second analog-to-digital converter ADC;

[0091] The second analog-to-digital converter ADC converts the accumulated current output by the second algorithm network into a digital signal and sends it to the maximum value comparison output module.

[0092] Furthermore, according to the bit positions of the input multiple rows of data, the multiplication and addition result is shifted to the left by the corresponding number of bits in the shifter; for the multiplication and accumulation result corresponding to the i-th position of the multiple rows of data, the multiplication and accumulation result is shifted to the left by i bits in the shifter;

[0093] Among them, 0≤i≤7.

[0094] Specifically, the shifter is used to perform data shift of signed numbers instead of multiplication operations.

[0095] Furthermore, a threshold is preset in the comparator. When the sum calculation result is greater than the threshold, the comparator outputs 1, and when the sum calculation result is less than the threshold, the comparator outputs 0.

[0096] Specifically, the comparator implements normalization and binarization of the data for use by the next layer of the network.

[0097] The maximum comparison output module can compare the maximum values ​​of the four output data of the last layer of the network and use them as the output of the classification results.

[0098] For example, if the hidden layer size in the BNN network is 14, the input data is 35 rows of 8-bit data, and the BNN network output is 4 data, the required algorithm network is two fully connected layers of 35*14 and 14*4, which are mapped to the circuit implementation as two RRAM arrays of 35*14 and 14*4. Therefore, according to the above BNN network structure and input data, a 35*14 area is selected in the flexible RRAM storage array as the first algorithm network, and a 14*4 area is selected as the second algorithm network; the first input of the flexible RRAM storage array is 35 rows * 8-bit input, and the weights are reused. Each of the 35 bits is written into the first algorithm network through the word line decoder eight times, that is, the input data is each bit of multiple rows (35 rows). After calculation through the first algorithm network, the multiplication and addition result is obtained, and the first column multiplexer MUX is connected to the first analog-to-digital converter ADC to obtain the digital-to-analog conversion result of the accumulated current of each column, and the analog-to-digital conversion result is stored in the data cache module 1. The output of the data buffer module 1 is connected to the adder-subtractor. At the same time, each bit input in the 35 rows is connected to the popcount module, which obtains the number of 1s in each bit in the multiple rows of input. The popcount module output is connected to the multiplier, where the number of 1s is multiplied by a fixed β value. The multiplier output is then connected to the adder-subtractor. The FPGA first sets the adder-subtractor to subtraction mode. The output of the multiplier is subtracted from the output of data buffer module 1 to obtain the multiplication and accumulation results for each bit in the 35 rows. The multiplication and accumulation results for each column corresponding to each bit are input into the shifter, which performs the corresponding shift for each bit. For example, the 0th bit is shifted left by 0 bits, and the 7th bit is shifted left by 7 bits. The shift results for each bit in each column are stored in data buffer module 2. For example, if it is the 0th bit, the shifter input data is 00000010, which is shifted by 0 bits and becomes 00000010 after shifting; if it is the 3rd bit, the shifter input data is 00000010, which is shifted by 3 bits and becomes 00010000. After the above operations are performed on all 8 bits, the shift results are stored in data buffer module 2. The shift results in data buffer module 2 are input to the adder-subtractor. The FPGA sets the adder-subtractor to addition, adds all the bit shift results of each column stored in data buffer module 2 to obtain the sum of each column, and outputs the sum to the comparator.A normalization operation is performed in the comparator, that is, the sum of the addition results is compared with the set threshold value. When the addition result is greater than the threshold value, 1 is output, and when the addition result is less than the threshold value, 0 is output; that is, when the addition result of the input is 3 and the threshold value is 1, the output is 1; when the addition result of the input is 0 and the threshold value is 1, the output is 0; in this way, the binary input of the next layer is obtained, that is, the input data of the second algorithm network; the last layer is not binarized, and the classification result is directly output through the maximum value comparison output module. Specifically, if the cumulative current value of the first column is the largest, 0 is output, and so on, if the data in the fourth column is the largest, 3 is output.

[0099] Compared to the prior art, this embodiment provides an in-memory computing circuit based on accelerated implementation of a BNN algorithm. This application utilizes a flexible RRAM memory-computing array with a 1T1R unit structure. The indium gallium zinc oxide thin-film transistor (IGZO) and memristor in the 1T1R unit structure are both flexible RRAM structures. Compared to the traditional 2T2R structure, this application halves the memory-computing array area without compromising computational accuracy, further improving energy efficiency. Its flexibility makes it particularly suitable for electronic skin applications. The design of peripheral circuits such as the analog-to-digital converter (ADC), popcount module, multiplier, and subtractor implements a complete BNN algorithm and supports multi-bit input, further improving the precision and accuracy of the algorithm's hardware circuit implementation.

[0100] Those skilled in the art will appreciate that all or part of the process steps of the above-described embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0101] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. An in-memory computing circuit based on the accelerated implementation of a binary neural network (BNN) algorithm, characterized in that: The circuit includes: a flexible RRAM storage and calculation array, a multiplication and accumulation module, a shifter, a comparator and a maximum value comparison output module; According to the BNN network structure and input data, two areas are selected in the flexible RRAM storage and computing array as the first algorithm network and the second algorithm network; Input multiple rows of data of each bit into the first algorithm network and the multiplication-accumulation module. The first algorithm network outputs the accumulated current of each column storage and calculation unit to the multiplication-accumulation module. The multiplication-accumulation module obtains the multiplication-accumulation result of each column based on the multiple rows of data and the accumulated current of each column storage and calculation unit, and inputs the multiplication-accumulation result of each column into the shifter. The shifter shifts the multiplication and accumulation results of each column by the corresponding number of bits according to the bits of each row of input data, and outputs the shifted results to the adder-subtractor in the multiplication and accumulation module. The adder-subtractor adds and calculates the shifted results of different bits of each column, and outputs the summed calculation results of each column to the comparator; The comparator performs binarization processing on the sum calculation results of each column to obtain a binarized result, outputs the binarized result to the second algorithm network, and calculates and outputs the accumulated current of each column again in the second algorithm network, and sends it to the maximum value comparison output module; The maximum value comparison output module determines the maximum value of the accumulated current in each column, and the column where the maximum value is located is the classification result.

2. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 1, characterized in that: The multiplication and accumulation module also includes: a popcount module and a multiplier; The popcount module receives multiple lines of data input and obtains the number of 1s in the multiple lines of data input, and outputs the number of 1s to the multiplier; The multiplier multiplies the number of 1s by a fixed value β and sends the product to the adder-subtractor; The adder-subtractor subtracts the product result from the digital signal to obtain a matrix multiplication and addition result, and sends the result to the shifter.

3. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 2, characterized in that: The circuit further comprises: a first column multiplexer MUX, a first analog-to-digital converter ADC; The first column multiplexer MUX sequentially selects each column of the storage and calculation unit of the first algorithm network, and sends the accumulated current of the selected column of storage and calculation unit to the first analog-to-digital converter ADC; The first analog-to-digital converter ADC converts the accumulated current output by the first algorithm network into a digital signal and sends it to the adder-subtractor.

4. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 3, characterized in that: The circuit further comprises: a second column multiplexer MUX, a second analog-to-digital converter ADC; The second column multiplexer MUX sequentially selects each column of the storage and calculation unit of the second algorithm network, and sends the accumulated current of the selected column of storage and calculation unit to the second analog-to-digital converter ADC; The second analog-to-digital converter ADC converts the accumulated current output by the second algorithm network into a digital signal and sends it to the maximum value comparison output module.

5. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 4, characterized in that: The circuit further comprises: a first data buffer module, a second data buffer module and a third data buffer module; all of which are used for temporary storage and integration of data; The first data buffer module receives the digital signal output by the first analog-to-digital converter ADC, buffers the digital signal, and then outputs the digital signal to the adder-subtractor; The second data buffer module receives the shift result output by the shifter, buffers it, and then outputs it to the adder-subtractor; The third data buffer module receives the binarization result output by the comparator, buffers it, and then outputs it to the second algorithm network.

6. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 5, characterized in that: The adder-subtractor implements addition or subtraction operations through control signals sent by the FPGA.

7. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 6, characterized in that: According to the bit positions of the input multiple rows of data, the multiplication and addition result is shifted left by the corresponding number of bits in the shifter; for the multiplication and accumulation result corresponding to the i-th multiple rows of data, the multiplication and accumulation result is shifted left by i bits in the shifter; wherein 0≤i≤7.

8. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 7, characterized in that: A threshold is pre-set in the comparator. When the sum calculation result is greater than the threshold, the comparator outputs 1, and when the sum calculation result is less than the threshold, the comparator outputs 0.

9. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 1, characterized in that: The flexible RRAM storage and computing array includes n×m storage and computing units; The word lines WL of each row of storage and calculation units are connected in sequence, the source lines SL of each column of storage and calculation units are connected in sequence, and the bit lines BL of each column of storage and calculation units are connected in sequence. The bit lines BL are used to output the calculation results of the storage and calculation units in this column. Each storage and computing unit has a 1T1R structure, including a transistor and a memristor.

10. The in-memory computing circuit based on the accelerated implementation of the binary neural network (BNN) algorithm according to claim 9, characterized in that: The transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the memristor is an RRAM; The gate of the indium gallium zinc oxide thin film transistor IGZO TFT is connected to the word line WL of the storage and calculation unit, the drain is connected to the bit line BL of the storage and calculation unit, the source is connected to one end of the memristor RRAM, and the other end of the RRAM is connected to the source line SL of the storage and calculation unit.

Images