Operation method of memory, memory and memory system

Abstract

The invention provides an operation method of a memory, the memory and a storage system, relates to the technical field of memories, and aims to solve the problem of programming interference. The method comprises the step of applying a first power supply voltage to the common source electrode in a programming pre-charging process. Starting from the first moment of the programming pre-charging process, first voltage is applied to the first bottom grid line, second voltage is applied to the voltage of the second bottom grid line, the first voltage is smaller than the first threshold voltage of a bottom selection tube connected with the first bottom grid line, and the second voltage is smaller than the second threshold voltage of a bottom selection tube connected with the second bottom grid line; and the second voltage is greater than a second threshold voltage of the bottom selection tube connected with the first bottom grid line. And after the first moment of the programming pre-charging process, a second power supply voltage is applied to the first bottom grid line, a third voltage is applied to the second bottom grid line, and the third voltage is smaller than a third threshold voltage of a bottom selection tube connected with the second bottom grid line. The operation method of the memory is applied to a programming pre-charging process of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory operation method, a memory, and a storage system. Background Art

[0002] NAND flash memory is a non-volatile storage technology, which means that data can be stored even after power failure, and has the advantages of low storage cost and high storage capacity. With the development of NAND flash memory technology, the circuit area of ​​NAND is gradually reduced, and the size of complementary metal oxide semiconductor (CMOS) circuit in NAND is also reduced. When the area of ​​peripheral circuit is reduced, the ramp capability of storage array voltage is affected, which will increase programming time.

[0003] In order to reduce the programming time, the method of reducing the load that the peripheral circuit needs to drive is usually adopted, thereby reducing the ramp up / ramp down time of the word line (WL) and the like. However, when reducing the load that the peripheral circuit needs to drive, programming disturbance is often caused. Therefore, how to reduce programming disturbance is a problem that needs to be solved urgently. Summary of the invention

[0004] Embodiments of the present disclosure provide a memory operation method, a memory, and a storage system, aiming to solve the problem of how to solve program disturbance.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, a method for operating a memory is provided, the method comprising: applying a first power supply voltage to a common source during a programming precharge process. Starting at the first moment of the programming precharge process, applying a first voltage to a first bottom gate line, and applying a second voltage to a voltage of a second bottom gate line, the first voltage being less than a first threshold voltage of a bottom selection tube connected to the first bottom gate line, and the second voltage being greater than a second threshold voltage of a bottom selection tube connected to the first bottom gate line. After the first moment of the programming precharge process, applying a second power supply voltage to the first bottom gate line, and applying a third voltage to the second bottom gate line, the third voltage being less than a third threshold voltage of a bottom selection tube connected to the second bottom gate line.

[0007] The operating method of the memory provided by the above-mentioned embodiment of the present disclosure applies the first power supply voltage to the common source, that is, the common source is at a high potential. At the first moment of the programming precharge process, the bottom selection tube connected with the first bottom gate line is turned off, and the bottom selection tube connected with the second bottom gate line is still in a conducting state at this moment, and the residual electrons when the bottom selection tube connected with the first bottom gate line is turned off can flow to the common source. In addition, after the first moment of the programming precharge process, the bottom selection tube connected with the second bottom gate line is turned off, and the residual electrons when the bottom selection tube connected with the second bottom gate line is turned off can flow to the common source. Thus, by carrying out sequential turning off of the first bottom gate line and the second bottom gate line, programming interference can be reduced.

[0008] In some embodiments, after a first moment of a programming precharge process, applying a second power supply voltage to the first bottom gate line, and applying a third voltage to the second bottom gate line, comprises: starting at a second moment after the first moment of the programming precharge process, applying the second power supply voltage to the first bottom gate line, and applying the third voltage to the top bottom gate line of the second bottom gate line. Applying the second power supply voltage to the top bottom gate lines of the first bottom gate line and the second bottom gate line, and starting at a third moment after the second moment of the programming precharge process, applying the third voltage to the bottom bottom gate line of the second bottom gate line.

[0009] In these embodiments, the top bottom gate line and the bottom bottom gate line in the first bottom gate line and the second bottom gate line are sequentially turned off, and the first power supply voltage is applied to the common source, that is, the common source is at a high potential. At this time, when the bottom selection tube is turned off, the electrons remaining in the channel will flow to the common source, thereby reducing programming interference.

[0010] In some embodiments, the method further includes: before the first moment of the programming precharge process, applying a fourth voltage to the first bottom gate line, the fourth voltage is less than the second voltage, and the fourth voltage is greater than a fourth threshold voltage of a bottom selection tube connected to the first bottom gate line.

[0011] In these embodiments, by applying a step-by-step conduction voltage to the first bottom gate line and the second bottom gate line, the bottom selection tube can be fully turned on to achieve a better programming pre-charging effect.

[0012] In some embodiments, the method further comprises: applying a bias voltage to the selected word line and applying a second power supply voltage to the unselected word lines during the program precharge process.

[0013] In some embodiments, the method further includes: applying a turn-on voltage to the selected top selection tubes, and applying a second power supply voltage to the unselected top selection tubes during the programming precharge process.

[0014] In some embodiments, the method further includes: before the programming precharge process, applying a first programming voltage and a second programming voltage to the first bottom gate line, wherein when the first programming voltage is applied, the first bottom selection tube of the first storage cell string connected to the first bottom gate line and the first bottom selection tube of the second storage cell string are programmed to the first threshold voltage, and when the second programming voltage is applied, the first bottom selection tube of the second storage cell string is programmed to the fourth threshold voltage, and the first threshold voltage is less than the fourth threshold voltage. Applying the first programming voltage and the second programming voltage to the second bottom gate line, wherein when the first programming voltage is applied, the second bottom selection tube of the first storage cell string connected to the second bottom gate line and the second bottom selection tube of the second storage cell string are programmed to the third threshold voltage, and when the second programming voltage is applied, the second bottom selection tube of the first storage cell string is programmed to the second threshold voltage, and the third threshold voltage is less than the second threshold voltage.

[0015] In these embodiments, before the programming precharge process, the first programming voltage and the second programming voltage are applied to the bottom selection tubes connected to the first bottom gate line and the second bottom gate line to control the threshold voltages of the bottom selection tubes to be different, thereby achieving electrical isolation. Compared with physical isolation, electrical isolation can save production costs and reduce process difficulty.

[0016] In some embodiments, the first storage string and the second storage string are located in different finger storage areas.

[0017] In these embodiments, electrical isolation can be set for different finger storage areas. Compared with physical isolation, electrical isolation can save production costs and reduce process difficulty.

[0018] In a second aspect, a memory is provided, the memory includes a plurality of memory cell strings, the memory cell strings include a plurality of bottom selection tubes connected in series in sequence; wherein the first bottom selection tube of the first memory cell string and the first bottom selection tube of the second memory cell string are connected to the first bottom gate line; the second bottom selection tube of the first memory cell string and the second bottom selection tube of the second memory cell string are connected to the second bottom gate line, and the second bottom selection tube is located between the first bottom selection tube and the common source; the memory also includes a peripheral circuit, the peripheral circuit is configured to: in the programming pre-charging process, apply a first power supply voltage to the common source. Starting from the first moment of the programming pre-charging process, apply a first voltage to the first bottom gate line, and apply a second voltage to the voltage of the second bottom gate line, the first voltage is less than the first threshold voltage of the bottom selection tube connected to the first bottom gate line, and the second voltage is greater than the second threshold voltage of the bottom selection tube connected to the first bottom gate line. After the first moment of the programming pre-charging process, apply a second power supply voltage to the first bottom gate line, and apply a third voltage to the second bottom gate line, the third voltage is less than the third threshold voltage of the bottom selection tube connected to the second bottom gate line.

[0019] The beneficial effects of the second aspect can refer to the description of the first aspect.

[0020] In some embodiments, the second bottom gate line includes a top bottom gate line and a bottom bottom gate line; the peripheral circuit is further configured to: starting from a second moment after the first moment of the programming precharge process, apply a second power supply voltage to the first bottom gate line, and apply a third voltage to the top bottom gate line of the second bottom gate line. Starting from a third moment after the second moment of the programming precharge process, apply a second power supply voltage to the top bottom gate line of the first bottom gate line and the second bottom gate line, and apply a third voltage to the bottom bottom gate line of the second bottom gate line.

[0021] In some embodiments, the peripheral circuit is further configured to: apply a fourth voltage to the first bottom gate line before the first moment of the programming precharge process, the fourth voltage is less than the second voltage, and the fourth voltage is greater than the fourth threshold voltage of the bottom selection tube connected to the first bottom gate line.

[0022] In some embodiments, the peripheral circuit is further configured to: apply a bias voltage to a selected word line and apply a second power supply voltage to unselected word lines during a program precharge process.

[0023] In some embodiments, the peripheral circuit is further configured to: apply a turn-on voltage to the selected top selection tubes, and apply a second power supply voltage to the unselected top selection tubes during the programming precharge process.

[0024] In some embodiments, the peripheral circuit is further configured to: apply a first programming voltage and a second programming voltage to the first bottom gate line before the programming precharge process, wherein when the first programming voltage is applied, the first bottom selection tube of the first storage cell string connected to the first bottom gate line and the first bottom selection tube of the second storage cell string are programmed to the first threshold voltage, and when the second programming voltage is applied, the first bottom selection tube of the second storage cell string is programmed to the fourth threshold voltage, and the first threshold voltage is less than the fourth threshold voltage. Apply the first programming voltage and the second programming voltage to the second bottom gate line, wherein when the first programming voltage is applied, the second bottom selection tube of the first storage cell string connected to the second bottom gate line and the second bottom selection tube of the second storage cell string are programmed to the third threshold voltage, and when the second programming voltage is applied, the second bottom selection tube of the first storage cell string is programmed to the second threshold voltage, and the third threshold voltage is less than the second threshold voltage.

[0025] In some embodiments, the first storage string and the second storage string are located in different finger storage areas.

[0026] According to a third aspect, a memory system is provided, the memory system comprising one or more memories according to the second aspect, and a memory controller coupled to the memory and configured to control the memory.

[0027] According to a fourth aspect, an electronic device is provided, the electronic device comprising the above storage system.

[0028] It can be understood that the beneficial effects that can be achieved by the memory operation method, memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the memory described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 A schematic diagram of a physical partition provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of an electrical isolation provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of a memory cell array for achieving electrical isolation provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of another memory cell array for achieving electrical isolation provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the structure of an exemplary system S1 having a storage system 10 provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of a memory card provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of another memory card provided in an embodiment of the present application;

[0037] Figure 8 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0038] Fig. 9 A flowchart of a method for operating a memory provided by an embodiment of the present application;

[0039] Fig.10A timing diagram of a programming operation of a memory provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of channel potential differences at different memory cells provided in an embodiment of the present application;

[0041] Fig.12 A timing diagram of a programming operation of another memory provided in an embodiment of the present application;

[0042] Fig.13 A schematic diagram of another channel potential difference at different memory cells provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0044] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and both include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0047] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0048] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0049] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0050] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0051] In order to effectively improve the program interference during the memory programming process, before performing a programming operation on the memory (such as NAND flash memory), a programming precharge process is performed on the memory to increase the coupling potential of the channel corresponding to the program inhibit memory cell string (inhibit string) in the memory when performing a programming operation on the selected memory cell string in the memory. Among them, the program inhibit memory cell string can also be understood as an unselected memory cell string or a non-programmed string. By increasing the coupling potential of the channel corresponding to the unselected memory cell string, the programming of the unselected memory cell string can be inhibited, thereby reducing program interference.

[0052] In order to turn off the unselected memory cell strings, a physical cut method can be used. Figure 1 As shown, Figure 1 A schematic diagram of a physical partition provided in an embodiment of the present application. Figure 1 A finger storage area (finger) is shown in the figure, and a finger storage area includes a top select gate (TSG), multiple storage units and a bottom select gate (BSG), and the top select gate and the bottom select gate are both provided with a physical partition structure. In one example, after the bottom select gate is physically partitioned, the bottom select gate is connected to a complementary metal oxide semiconductor (CMOS). At this time, the CMOS driver 1 (drive) can control the conduction and shutdown of a part of the bottom select gates, and the CMOS driver 2 can control the conduction and shutdown of another part of the bottom select gates.

[0053] However, the physical cut method will increase the manufacturing cost of the memory. Therefore, an electrical cut method is proposed, such as Figure 2 As shown, Figure 2 A schematic diagram of an electrical isolation provided in an embodiment of the present application. Figure 2 The storage area shown in the figure includes a top selection tube, a plurality of storage units and a bottom selection tube. The top selection tube is physically isolated, and the bottom selection tube is electrically isolated. Specifically, the bottom selection tube includes BSG1 and BSG2, wherein BSG1 is connected to CMOS driver 1, and BSG2 is connected to CMOS driver 2. At this time, the threshold voltages of the multiple bottom selection tubes in BSG1 and BSG2 are different, so different voltages can be applied to CMOS driver 1 and CMOS driver 2 to control the multiple bottom selection tubes in BSG1 and BSG2 to turn on or off, thereby realizing the turning on or off of the bottom selection tubes of the same page.

[0054] Specifically, Figure 3 As shown, Figure 3 , a first finger storage area (finger1) and a second finger storage area (finger2) are shown. Finger1 includes two storage strings (str0 and str1), and finger2 includes two storage strings (str2 and str3). Figure 3Only some storage units, bottom selection tubes and common source connected in series are shown in the figure, wherein some bottom selection tubes are connected to the first bottom gate line, some bottom selection tubes are connected to the second bottom gate line, and the bottom selection tube connected to the second bottom gate line is closer to the common source. In order to avoid the situation where the storage string fails due to damage of a single bottom selection tube, the first bottom gate line can be connected to the multi-layer bottom selection tube, that is, the first bottom gate line can include multiple word lines (word line, WL), and applying a turn-off voltage to the first bottom gate line can be understood as applying the same turn-off voltage to multiple word lines. The second bottom gate line can also be connected to the multi-layer bottom selection tube, that is, the second bottom gate line also includes multiple word lines, and applying a turn-off voltage to the second bottom gate line can be understood as applying the same turn-off voltage to multiple word lines. Before programming between storage units, multiple bottom selection tubes can be programmed so that the threshold voltages of multiple bottom selection tubes are different to achieve electrical isolation. In one example, the bottom selection tube of finger1 connected to the first bottom gate line is a high threshold voltage (high threshold voltage, HV), and the bottom selection tube of finger2 connected to the first bottom gate line is a low threshold voltage (low threshold voltage). In addition, the bottom selection tube of finger1 connected to the second bottom gate line is a low threshold voltage, and the bottom selection tube of finger2 connected to the second bottom gate line is a high threshold voltage. In addition, the bottom selection tubes of finger1 and finger2 connected to the second bottom gate line also include a bottom selection tube with a middle threshold voltage (middle threshold voltage), and the bottom selection tube with the middle threshold voltage is used to isolate the bottom selection tube with a high threshold voltage and the bottom selection tube with a low threshold voltage.

[0055] Wherein, the principle of realizing electrical isolation is: applying a first conduction voltage to the first bottom gate line, the first conduction voltage is greater than the high threshold voltage, and the bottom selection tubes connected to the first bottom gate line are all turned on, applying a second conduction voltage to the second bottom gate line, the second conduction voltage is greater than the low threshold voltage and less than the high threshold voltage, at this time, the bottom selection tube in finger1 connected to the second bottom gate line is turned on, and the bottom selection tube in finger2 connected to the second bottom gate line is turned off. Thus, the bottom selection tubes of finger1 are all turned on, and the bottom selection tubes of finger2 are partially turned off, and the storage cell string of finger2 is a non-selected storage cell string. In another implementation, the second conduction voltage is applied to the first bottom gate line, at this time, finger1 connected to the first bottom gate line is turned off, and finger2 connected to the first bottom gate line is turned on. Applying a first conduction voltage to the second bottom gate line, at this time, finger1 and finger2 connected to the first bottom gate line are both turned on. Thus, the bottom selection tubes of finger1 are partially turned off, and the bottom selection tubes of finger2 are all turned off. At this time, the memory cell string of finger1 is a non-selected memory cell string.

[0056] In another implementation, Figure 4 As shown, Figure 4 , a first finger storage area (finger1) and a second finger storage area (finger2) are shown. Finger1 includes two storage strings (str0 and str1), and finger2 includes two storage strings (str2 and str3). Figure 4 Only some storage units, bottom selection tubes and common sources connected in series are shown in FIG. Wherein, a part of the bottom selection tubes is connected to the first bottom gate line, another part of the bottom selection tubes is connected to the top bottom gate line of the second bottom gate line, and another part of the bottom selection tubes is connected to the bottom bottom gate line of the second bottom gate line. Wherein, the first bottom gate line, the top bottom gate line of the second bottom gate line, the bottom bottom gate line of the second bottom gate line are arranged in sequence, and the bottom bottom gate line of the second bottom gate line is closer to the common source. In one example, the bottom selection tube of finger1 connected to the first bottom gate line is a high threshold voltage, and the bottom selection tube of finger2 connected to the first bottom gate line is a low threshold voltage. In addition, the bottom selection tube of finger1 connected to the top bottom gate line of the second bottom gate line is a low threshold voltage, the bottom selection tube of finger2 connected to the top bottom gate line of the second bottom gate line is a high threshold voltage, and the bottom selection tube of the top bottom gate line of the second bottom gate line can also be a medium threshold voltage. In addition, the bottom selection tube connected to the bottom bottom gate line of the second bottom gate line is a medium threshold voltage.

[0057] However, in order to reduce programming time, the unselected memory cell strings are usually selectively turned off to reduce the load that the peripheral circuit needs to drive and to reduce the rise / fall time of the word line, etc. When the unselected memory cell strings are selectively turned off, due to the different threshold voltages of the bottom selection tubes, there will be residual electrons in the channel of the unselected memory cell strings, and the residual electrons will cause programming interference.

[0058] Therefore, an embodiment of the present application provides a method for operating a memory, by sequentially shutting down the first bottom gate line and the second bottom gate line, and applying a first power supply voltage to the common source, that is, the common source is at a high potential. At this time, when the bottom selection tube is turned off, the electrons remaining in the channel will flow to the common source, thereby reducing programming interference.

[0059] For ease of understanding, the storage system to which the memory operation method provided in the embodiment of the present application is applied is first introduced below.

[0060] like Figure 5 As shown, Figure 5 A schematic diagram of the structure of an exemplary system S1 having a storage system 10 provided in an embodiment of the present disclosure. The system S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The storage system 10 (also referred to as a NAND memory system) includes a memory 101 and a controller 102. The storage system 10 may communicate with a host computer 20 through the controller 102, wherein the controller 102 may be coupled to the memory 101 via a memory channel 30. In some embodiments, the memory 101 in the present disclosure may be a three-dimensional non-volatile memory, such as a NAND flash memory, which may also be referred to as a flash memory or NAND. Of course, the memory 101 in the present disclosure may also be other memories. The storage system 10 may have more than one memory 101, and each memory 101 may be managed by a controller 102.

[0061] In some embodiments, the host computer 20 may be a processor of an electronic device, such as a central processing unit (CPU), a system-on-chip (SoC), or an application processor (AP). The host computer 20 may send data to be stored in the storage system 10 or read data stored in the storage system 10.

[0062] Controller 102 may process input / output (I / O) requests received from host computer 20, ensure data integrity and efficient storage, and may also manage memory 101. Memory channel 30 may provide data and control communications between controller 102 and memory 101 via a data bus.

[0063] Continue to refer Figure 5 , the memory 101 may be a memory chip (package), a memory die, or any portion of a memory die, and may include one or more storage planes 1011, each of which may include multiple storage blocks 10111. The same and concurrent operations may occur at each storage plane 1011. The size of the storage block 10111 may be megabytes (MB), and the storage block 10111 is the smallest unit for performing an erase operation. Figure 5 The memory 101 illustrated in the example includes four storage planes 1011, and each storage plane 1011 includes six storage blocks 10111. Each storage block 10111 may include a plurality of storage cells, wherein each storage cell may be addressed by, for example, a bit line (BL) and a word line (WL). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The directions of the bit lines and word lines are Figure 5 In the present disclosure, one or more storage blocks 10111 may also be referred to as a "storage array" or "array". The storage array is a core area in a memory device that performs storage functions.

[0064] The memory 101 also includes a peripheral circuit area 1012, which is a peripheral area of ​​the storage surface 1011. The peripheral circuit area 1012 (also referred to as a peripheral circuit) contains many digital, analog and / or mixed signal circuits (e.g., page buffer / sense amplifier 10121, row decoder / word line driver 10122, column decoder / bit line driver 10123 and peripheral control circuit 10124) to support the functions of the memory 101. Among them, the peripheral control circuit 10124 may include registers, active and / or passive semiconductor devices, such as transistors, diodes, capacitors or resistors, etc., which is obvious to those of ordinary skill in the art. The peripheral control circuit 10124 of the peripheral circuit area 1012 can be configured to initiate a programming operation on a selected memory cell of a NAND memory string in the memory block 10111. In some embodiments, the peripheral control circuit 10124 receives a programming command from the controller 102 through an interface, and in response, sends control signals to the row decoder / word line driver 10122, column decoder / bit line driver 10123, and voltage generator ( Figure 5 ), to initiate a programming operation on the selected memory cell.

[0065] Notice, Figure 5 The layout of the electronic devices in the storage system 10 and the memory 101 in FIG. 1 is shown as an example. The storage system 10 and the memory 101 may have other layouts and may include additional devices. For example, the memory 101 may also include a high voltage charge pump, input-output circuits, etc. The storage system 10 may also include firmware and a data scrambler, etc. In some embodiments, the peripheral circuit area 1012 and the storage array may be independently formed on separate wafers and connected to each other by wafer bonding.

[0066] The controller 102 and one or more memories 101 may be integrated into various types of storage devices, for example, in the same package, such as a universal flash storage (UFS) package or an embedded multi-media card (eMMC) package. That is, the storage system 10 may be implemented and packaged into different types of terminal electronic products. Figure 6In one example shown in FIG. 1 , the controller 102 and the single memory 101 may be integrated into a memory card 40. The memory card 40 may include a personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD card), or a UFS, etc. The memory card 40 may also include a memory card connector 41 that couples the memory card 40 to the host computer 20. In the example shown in FIG. 1 , the controller 102 and the single memory 101 may be integrated into a memory card 40. In the example shown in FIG. 1 , the memory card 40 may include a personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD card), or a UFS, etc. The memory card 40 may also include a memory card connector 41 that couples the memory card 40 to the host computer 20. Figure 7 In another example shown in FIG. 1 , the controller 102 and the plurality of memories 101 may be integrated into a solid state drive (SSD) 50. The SSD 50 may further include an SSD connector 51 that couples the SSD 50 with the host computer 20.

[0067] like Figure 8 As shown, Figure 8 A schematic diagram of the structure of a memory 101 provided in an embodiment of the present disclosure. The memory 101 includes one or more memory blocks 10111. Each memory block 10111 includes a memory string 60. Each memory string 60 includes a memory cell 601. The memory cells 601 sharing the same bit line form a memory string 60. The memory string 60 may also include at least one field effect transistor (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) at each end, which is controlled by a top selection tube 71 and a bottom selection tube 72, respectively. The drain terminal of the top selection tube 71 may be connected to a bit line 80, and the source terminal of the bottom selection tube 72 may be connected to an array common source (ACS) 82. The ACS 82 may be shared by the memory strings 60 in the entire memory block 10111, and is also referred to as a common source line (SL).

[0068] In some embodiments, the peripheral circuit area 1012 of the memory 101 may support the erase operation of the GIDL assisted technology. The memory block 10111 may be coupled to the row decoder / word line driver 10122 via the word line 81, the top selection tube 71, and the bottom selection tube 72. The memory block 10111 may be coupled to the page buffer / sense amplifier 10121 via the bit line 80. The row decoder / word line driver 10122 may select one of the memory blocks 10111 on the memory 101 in response to the X path control signal provided by the peripheral control circuit 10124. The row decoder / word line driver 10122 may pass the voltage provided from the voltage generator 90 to the word line 81 according to the X path control signal. During the read and program operations, the row decoder / word line driver 10122 may pass the read voltage Vread and the program voltage Vpgm to the selected word line 81 according to the X path control signal received from the peripheral control circuit 10124, and pass the pass voltage Vpass to the non-selected word line.

[0069] The column decoder / bit line driver 10123 can pass the inhibit voltage Vinhibit to the non-selected bit line according to the Y path control signal received from the peripheral control circuit 10124, and connect the selected bit line 80 to the ground. That is, the column decoder / bit line driver 10123 can be configured to select or deselect one or more storage strings 60 according to the Y path control signal from the peripheral control circuit 10124. The page buffer / sense amplifier 10121 can be configured to read data from the storage block 10111 and program (write) data to the storage block 10111 according to the Y path control signal from the peripheral control circuit 10124. For example, the page buffer / sense amplifier 10121 can store a page of data to be programmed into a memory page. In another example, the page buffer / sense amplifier 10121 can perform a verification operation to ensure that the data has been correctly programmed into each memory cell 601. In yet another example, during a read operation, the page buffer / sense amplifier 10121 can sense the current flowing through the bit line 80 reflecting the logic state (ie, data) of the memory cell 601 , as well as the amplification rate of amplifying a small signal to a measurable signal.

[0070] The input / output buffer 91 may transfer I / O data from / to the page buffer / sense amplifier 10121, and transfer an address ADDR signal or a command CMD signal to the peripheral control circuit 10124. In some embodiments, the input / output buffer 91 may be used as an interface between the controller 102 and the memory 101.

[0071] The peripheral control circuit 10124 may control the page buffer / sense amplifier 10121 and the row decoder / word line driver 10122 in response to the command CMD delivered by the input / output buffer 91. During a programming operation, the peripheral control circuit 10124 may control the row decoder / word line driver 10122 and the page buffer / sense amplifier 10121 to program the selected memory cell 601. During a read operation, the peripheral control circuit 10124 may control the row decoder / word line driver 10122 and the page buffer / sense amplifier 10121 to read the selected memory cell 601. The X-path control signal includes a row address X-ADDR, and the Y-path control signal includes a column address Y-ADDR, which may be used to locate the selected memory cell 601 in the memory block 10111. The row address X-ADDR may include a page index, a block index, and a plane index to identify a memory page, a memory block 10111, and a memory plane 1011, respectively. The column address Y-ADDR may identify a byte or word in the data of the memory page.

[0072] In some embodiments, the peripheral control circuit 10124 may include one or more control logic units. Each control logic unit described herein may be a software module and / or a firmware module running on a processor, such as a microcontroller unit (MCU) as part of the peripheral control circuit 10124, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC), such as an application-specific IC (ASIC), a field-programmable gate array (FPGA), etc., or a combination of software modules, firmware modules, and hardware modules.

[0073] The voltage generator 90 may generate voltages provided to the word lines 81 and the bit lines 80 under the control of the peripheral control circuit 10124. The voltages generated by the voltage generator 90 include a read voltage Vread, a program voltage Vpgm, a pass voltage Vpass, an inhibit voltage Vinhibit, and the like.

[0074] In some embodiments, the memory 101 may be formed based on floating gate technology. In some embodiments, the memory 101 may be formed based on charge trapping technology. The memory 101 based on charge trapping may provide high storage density and high intrinsic reliability. The stored data or logic state (e.g., the threshold voltage Vth of the memory cell 601) depends on the amount of charge trapped in the storage layer. In some embodiments, the memory 101 may be a three-dimensional (3D) memory device in which the memory cells 601 may be stacked vertically on top of each other.

[0075] In some embodiments, when performing an erase operation, by implementing a negative voltage difference between the gate and source terminals (e.g., ACS82) of 601, all trapped electron charges in the storage layer of the memory cell 601 can be removed, and all memory cells 601 in the same memory block 10111 can be reset to the erase state ER as logic "1". For example, the voltage difference can be induced by setting the control gate in the memory cell 601 to ground and applying a positive voltage to the source line 82. In this example, a voltage pulse can be applied to the memory cell 601 in the erase operation.

[0076] Applied to the above memory, the embodiment of the present application provides a method for operating the memory, such as Fig. 9 As shown, Fig. 9 A flowchart of a memory operation method provided in an embodiment of the present application. The memory operation method includes the following steps.

[0077] S901. During programming pre-charging, the memory applies a first power supply voltage to a common source.

[0078] Exemplarily, the memory may include a memory array composed of a plurality of memory cells, and the memory cells may include single-level cells, multi-level cells, triple-level cells, quad-level cells, or cells with a higher number of levels, etc. The programming operation of the memory cell may include a program precharge process (program precharge) and a programming process (program).

[0079] Exemplarily, the first power supply voltage may be a system voltage (Vdd) of the memory. During the programming precharge process, the voltage at the common source is the first power supply voltage, that is, the common source is at a high potential, which can attract the electrons remaining in the channel when the bottom selection tube is turned off to flow to the common source to reduce programming interference.

[0080] S902, starting from the first moment of the programming precharge process, the memory applies a first voltage to the first bottom gate line, and applies a second voltage to the voltage of the second bottom gate line, the first voltage is less than the first threshold voltage of the bottom selection tube connected to the first bottom gate line, and the second voltage is greater than the second threshold voltage of the bottom selection tube connected to the first bottom gate line.

[0081] Exemplarily, the first threshold voltage may be the minimum threshold voltage of the bottom selection tube connected to the first bottom gate line, that is, the first voltage is less than the low threshold voltage of the bottom selection tube connected to the first bottom gate line. The second threshold voltage may be the maximum threshold voltage of the bottom selection tube connected to the second bottom gate line, that is, the second voltage is greater than the high threshold voltage of the bottom selection tube connected to the second bottom gate line.

[0082] S903, after the first moment of the programming precharge process, the memory applies a second power supply voltage to the first bottom gate line, and applies a third voltage to the second bottom gate line, wherein the third voltage is less than a third threshold voltage of the bottom selection tube connected to the second bottom gate line.

[0083] Exemplarily, the third threshold voltage can be the minimum threshold voltage of the bottom selection tube connected to the second bottom gate line, that is, the third voltage is less than the low threshold voltage of the bottom selection tube connected to the second bottom gate line. In addition, the second power supply voltage is the ground voltage (VSS) of the memory.

[0084] like Fig.10 As shown, Fig.10 A timing diagram of a programming operation of a memory is shown in FIG. Wherein, the voltage at the common source is the first power supply voltage in the programming precharge process and the programming process. At the first moment, a first voltage is applied to the first bottom gate line, and the first voltage is less than the first threshold voltage, whereby the bottom selection tube connected to the first bottom gate line begins to turn off. At this time, a second voltage is applied to the second bottom gate line, and the second voltage is greater than the second threshold voltage, whereby the bottom selection tube connected to the second bottom gate line is still in the on state, and the residual electrons in the channel caused by the bottom selection tube connected to the first bottom gate line being turned off can be attracted to the common source through the bottom selection tube connected to the second bottom gate line.

[0085] After the first moment, a third voltage is applied to the second bottom gate line, and the third voltage is less than a third threshold voltage, so that the bottom selection tube connected to the second bottom gate line begins to turn off, and the electrons remaining in the channel caused by the bottom selection tube connected to the second bottom gate line turning off are attracted to the common source. Thus, the electrons remaining in the channel can be reduced, and program disturbance can be reduced.

[0086] Optionally, the method further includes: during the programming pre-charging process, applying a turn-on voltage to the selected top selection tube, and applying a second power supply voltage to the unselected top selection tube.

[0087] Continue to refer Fig.10For the top selection tube, the unselected top selection tube can apply the second power supply voltage in both the programming pre-charging process and the programming process, and the selected top selection tube can apply the second power supply voltage in the programming pre-charging process and can apply a turn-on voltage in the programming process, and the turn-on voltage can be applied, which is greater than the threshold voltage of the top selection tube.

[0088] Optionally, the method further includes: applying a bias voltage to a selected word line and applying a second power supply voltage to an unselected word line during a programming precharge process.

[0089] Continue to refer Fig.10 , a bias voltage may be applied to the selected word line during the programming precharge process, and a second power supply voltage may also be applied to the selected word line during the programming precharge process. A program voltage (Vpgrm) may be applied to the selected word line during the programming process. A second power supply voltage may be applied to the unselected word line during the programming precharge process. In order to reduce the programming interference of the unselected word line on the selected word line, a pass voltage (Vpass) may be applied to the unselected word line during the programming process.

[0090] In addition, for the top dummy layer, a second power supply voltage may be applied during the programming precharge process, and a bias voltage (bias voltage, Vbias) may be applied during the programming process. For the bottom dummy layer, a high threshold voltage may be applied at the beginning of the programming precharge process, a second power supply voltage may be applied at the end of the programming precharge process, and a bias voltage may be applied during the programming process.

[0091] like Fig.11 As shown, Fig.11 Schematic diagram showing the channel potential difference at different memory cells. Fig.11 Schematic diagrams of channel potential differences at different memory cells in a baseline without sequentially shutting down the bottom selection tube, schematic diagrams of channel potential differences at different memory cells in a first finger storage area, and schematic diagrams of channel potential differences at different memory cells in a second finger storage area are shown in FIG. Fig.11 It can be seen that compared with the bottom selection tube in the baseline, the channel potential difference between the bottom selection tube in the first finger storage area and the second finger storage area is lower, thereby reducing the residual electrons in the channel and reducing programming interference.

[0092] Optionally, step S903 may include: starting at a second moment after the first moment of the programming precharge process, applying a second power supply voltage to the first bottom gate line, and applying a third voltage to the top bottom gate line of the second bottom gate line. Starting at a third moment after the second moment of the programming precharge process, applying a second power supply voltage to the top bottom gate line of the first bottom gate line and the second bottom gate line, and applying a third voltage to the bottom bottom gate line of the second bottom gate line.

[0093] For example, Fig.12 As shown, Fig.12 A timing diagram of the programming operation of another memory is shown. Wherein, the voltage at the common source can apply the first power supply voltage in the programming precharge process and the programming process. At the first moment, the first bottom gate line is applied with a first voltage, and the first voltage is less than the first threshold voltage, and the bottom selection tube connected with the first bottom gate line begins to turn off. At this moment, the second bottom gate line is applied with a second voltage, and the second voltage is greater than the second threshold voltage, thus, the bottom selection tube connected with the top bottom gate line and the bottom bottom gate line of the second bottom gate line is still in the conducting state, thus, the residual electrons in the channel caused by the bottom selection tube connected with the first bottom gate line turning off can be attracted to the common source through the bottom selection tube connected with the top bottom gate line and the bottom bottom gate line of the second bottom gate line.

[0094] At the second moment, a third voltage is applied to the top bottom gate line, and the third voltage is less than the third threshold voltage, and the bottom selection tube connected to the top bottom gate line begins to turn off. At this time, the bottom selection tube connected to the bottom bottom gate line is still in the on state, so that the electrons remaining in the channel caused by the bottom selection tube connected to the top bottom gate line turning off can be attracted to the common source through the bottom selection tube connected to the bottom bottom gate line. At the third moment, a third voltage is applied to the bottom bottom gate line, and the bottom selection tube connected to the bottom bottom gate line begins to turn off, so that the electrons remaining in the channel caused by the bottom selection tube connected to the bottom bottom gate line turning off are attracted to the common source. Thus, the electrons remaining in the channel can be reduced, and the programming interference can be reduced.

[0095] In addition, for the unselected top gate line, the selected top gate line, the selected word line, the unselected word line, the top redundant layer and the bottom redundant layer and Fig.10 The timing diagram is the same as that shown in , and will not be repeated here.

[0096] like Fig.13 As shown, Fig.13 A schematic diagram showing the channel potential difference at different memory cells. Fig.13, a schematic diagram of the channel potential difference at different memory cells in the baseline without the bottom selection tube being turned off sequentially, a schematic diagram of the channel potential difference at different memory cells in the first finger storage area, and a schematic diagram of the channel potential difference at different memory cells in the second finger storage area. Fig.13 It can be seen that compared with the bottom selection tube in the baseline, the channel potential difference between the bottom selection tube in the first finger storage area and the second finger storage area is lower, thereby reducing the residual electrons in the channel and reducing programming interference.

[0097] Optionally, the method may further include: before the first moment of programming pre-charging, applying a fourth voltage to the first bottom gate line, the fourth voltage being less than the second voltage and greater than a fourth threshold voltage of a bottom selection tube connected to the first bottom gate line.

[0098] Continue to refer Fig.10 In order to make the bottom selection tube fully conductive and achieve a better programming pre-charging effect, a step voltage can be applied to the first bottom gate line and the second bottom gate line. Among them, the fourth threshold voltage can be the maximum threshold voltage of the bottom selection tube connected to the first bottom gate line. The fourth voltage is greater than the maximum threshold voltage of the bottom selection tube connected to the first bottom gate line, and the second voltage is also greater than the maximum threshold voltage of the bottom selection tube connected to the second bottom gate line. That is, in the programming pre-charging process, the bottom selection tubes are all in the conductive state.

[0099] In another implementation, see Fig.12 In order to make the bottom selection tube fully conductive and achieve a better programming pre-charging effect, a step voltage can be applied to the first bottom gate line, the top bottom gate line and the bottom bottom gate line. That is, before the first moment of programming pre-charging, the fourth voltage is applied to the first bottom gate line, the second voltage is applied to the top bottom gate line, and the fifth voltage is applied to the bottom bottom gate line, wherein the fifth voltage is greater than the second voltage. Thus, during the programming pre-charging process, the bottom selection tubes are all in a conductive state.

[0100] Optionally, the method further includes: before the programming precharge process, applying a first programming voltage and a second programming voltage to the first bottom gate line, wherein when the first programming voltage is applied, the first bottom selection tube of the first storage cell string and the first bottom selection tube of the second storage cell string connected to the first bottom gate line are programmed to the first threshold voltage, and when the second programming voltage is applied, the first bottom selection tube of the second storage cell string is programmed to the fourth threshold voltage, and the first threshold voltage is less than the fourth threshold voltage. Applying the first programming voltage and the second programming voltage to the second bottom gate line, wherein when the first programming voltage is applied, the second bottom selection tube of the first storage cell string and the second bottom selection tube of the second storage cell string connected to the second bottom gate line are programmed to the third threshold voltage, and when the second programming voltage is applied, the second bottom selection tube of the first storage cell string is programmed to the second threshold voltage, and the third threshold voltage is less than the second threshold voltage.

[0101] Exemplarily, the first storage string may include a storage cell string connected to BL0-BLn, and the second storage string may include a storage cell string connected to BLn+1-BL2n. The finger storage area may include two storage strings, the first storage string and the second storage string are located in different finger storage areas, and the finger storage area may include a first finger storage area and a second finger storage area.

[0102] The first threshold voltage may be a high threshold voltage, and the fourth threshold voltage may be a low threshold voltage. Figure 3 The storage string shown is taken as an example. When the first programming voltage is applied to the first bottom gate line, the bottom selection tubes of str0, str1, str2 and str3 connected to the first bottom gate line are all programmed to a low threshold voltage. When the second programming voltage is applied to the first bottom gate line, the bottom selection tubes of str0 and str1 connected to the first bottom gate line are programmed to a high threshold voltage, wherein an inhibit voltage can be applied to the bit line connecting str2 and str3. When the first programming voltage is applied to the second bottom gate line, the bottom selection tubes of str0, str1, str2 and str3 connected to the first bottom gate line are all programmed to a low threshold voltage. When the second programming voltage is applied to the second bottom gate line, the bottom selection tubes of str2 and str3 connected to the second bottom gate line are programmed to a high threshold voltage, wherein an inhibit voltage can be applied to the bit line connecting str0 and str1. Thus, the selection of different storage strings or finger storage areas can be turned off by the combination of the threshold voltages of the bottom selection tubes of different layers, reducing the load driven by the peripheral circuit and reducing the programming time.

[0103] In addition, a third programming voltage may be applied to the bottom selection transistor connected to the second bottom gate line. When the third programming voltage is applied, the bottom selection transistors of the first storage cell string and the second storage cell string connected to the second bottom gate line are programmed to a fifth threshold voltage, which may be a middle threshold voltage.

[0104] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0105] The electronic device may include the memory system described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0106] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that: The method comprises: In the programming precharge process, applying a first power supply voltage to the common source; Starting from the first moment of the programming precharge process, a first voltage is applied to the first bottom gate line, and a second voltage is applied to the voltage of the second bottom gate line, wherein the first voltage is less than a first threshold voltage of a bottom selection tube connected to the first bottom gate line, and the second voltage is greater than a second threshold voltage of a bottom selection tube connected to the second bottom gate line; After the first moment of the programming precharge process, a second power supply voltage is applied to the first bottom gate line, and a third voltage is applied to the second bottom gate line, wherein the third voltage is less than a third threshold voltage of a bottom selection tube connected to the second bottom gate line.

2. The operating method according to claim 1, characterized in that: After the first moment of the programming precharge process, applying the second power supply voltage to the first bottom gate line, and applying the third voltage to the second bottom gate line, comprises: Starting from a second moment after the first moment of the programming precharge process, applying the second power supply voltage to the first bottom gate line, and applying the third voltage to the top bottom gate line of the second bottom gate line; Starting at a third time after the second time of the programming precharge process, the second power supply voltage is applied to the top bottom gate line of the first bottom gate line and the second bottom gate line, and the third voltage is applied to the bottom bottom gate line of the second bottom gate line.

3. The operating method according to claim 1, characterized in that: The method further comprises: Before the first moment of the programming precharge process, a fourth voltage is applied to the first bottom gate line, the fourth voltage is less than the second voltage, and the fourth voltage is greater than a fourth threshold voltage of a bottom selection transistor connected to the first bottom gate line.

4. The operating method according to claim 1, characterized in that: The method further comprises: In the program precharge process, a bias voltage is applied to the selected word line, and a second power supply voltage is applied to the unselected word lines.

5. The operating method according to claim 1, characterized in that: The method further comprises: In the programming precharge process, a turn-on voltage is applied to the selected top selection tube, and a second power supply voltage is applied to the unselected top selection tube.

6. The operating method according to claim 1, characterized in that: The method further comprises: Before the programming precharge process, a first programming voltage and a second programming voltage are applied to the first bottom gate line, wherein when the first programming voltage is applied, the first bottom selection tube of the first storage cell string and the first bottom selection tube of the second storage cell string connected to the first bottom gate line are programmed to the first threshold voltage, and when the second programming voltage is applied, the first bottom selection tube of the second storage cell string is programmed to a fourth threshold voltage, and the first threshold voltage is less than the fourth threshold voltage.

7. The operating method according to claim 6, characterized in that: The method further comprises: The first programming voltage and the second programming voltage are applied to the second bottom gate line, wherein when the first programming voltage is applied, the second bottom selection tube of the first storage cell string and the second bottom selection tube of the second storage cell string connected to the second bottom gate line are programmed to the third threshold voltage, and when the second programming voltage is applied, the second bottom selection tube of the first storage cell string is programmed to the second threshold voltage, and the third threshold voltage is less than the second threshold voltage.

8. The operating method according to claim 7, characterized in that: The first storage string and the second storage string are located in different finger storage areas.

9. A memory, characterized in that: The memory comprises a plurality of storage cell strings, wherein the storage cell strings comprise a plurality of bottom selection tubes connected in series in sequence; wherein a first bottom selection tube of a first storage cell string and a first bottom selection tube of a second storage cell string are connected to a first bottom gate line; a second bottom selection tube of the first storage cell string and a second bottom selection tube of the second storage cell string are connected to a second bottom gate line, and the second bottom selection tube is located between the first bottom selection tube and a common source; The memory further includes a peripheral circuit, wherein the peripheral circuit is configured to: In a programming precharge process, applying a first power supply voltage to the common source; Starting at the first moment of the programming precharge process, applying a first voltage to the first bottom gate line, and applying a second voltage to the voltage of the second bottom gate line, the first voltage is less than a first threshold voltage of a bottom selection tube connected to the first bottom gate line, and the second voltage is greater than a second threshold voltage of a bottom selection tube connected to the first bottom gate line; After the first moment of the programming precharge process, a second power supply voltage is applied to the first bottom gate line, and a third voltage is applied to the second bottom gate line, wherein the third voltage is less than a third threshold voltage of a bottom selection tube connected to the second bottom gate line.

10. The memory according to claim 9, characterized in that: The second bottom gate line includes a top bottom gate line and a bottom bottom gate line; and the peripheral circuit is further configured as follows: Starting from a second moment after the first moment of the programming precharge process, applying the second power supply voltage to the first bottom gate line, and applying the third voltage to the top bottom gate line of the second bottom gate line; The programming precharge process starts at a third time after the second time, and the second power supply voltage is applied to the top bottom gate line of the first bottom gate line and the second bottom gate line, and the third voltage is applied to the bottom bottom gate line of the second bottom gate line.

11. The memory according to claim 9, characterized in that: The peripheral circuit is further configured as: Before the first moment of the programming precharge, a fourth voltage is applied to the first bottom gate line, the fourth voltage is less than the second voltage, and the fourth voltage is greater than a fourth threshold voltage of a bottom selection transistor connected to the first bottom gate line.

12. The memory according to claim 9, characterized in that: The peripheral circuit is further configured as: In the program precharge process, a bias voltage is applied to the selected word line, and a second power supply voltage is applied to the unselected word lines.

13. The memory according to claim 9, characterized in that: The peripheral circuit is further configured as: In the programming precharge process, a turn-on voltage is applied to the selected top selection tube, and a second power supply voltage is applied to the unselected top selection tube.

14. The memory according to claim 9, characterized in that: The peripheral circuit is further configured as: Before the programming precharge process, a first programming voltage and a second programming voltage are applied to the first bottom gate line, wherein when the first programming voltage is applied, the first bottom selection tube of the first storage cell string and the first bottom selection tube of the second storage cell string connected to the first bottom gate line are programmed to the first threshold voltage, and when the second programming voltage is applied, the first bottom selection tube of the second storage cell string is programmed to a fourth threshold voltage, and the first threshold voltage is less than the fourth threshold voltage.

15. The memory according to claim 14, characterized in that: The peripheral circuit is further configured as: The first programming voltage and the second programming voltage are applied to the second bottom gate line, wherein when the first programming voltage is applied, the second bottom selection tube of the first storage cell string and the second bottom selection tube of the second storage cell string connected to the second bottom gate line are programmed to the third threshold voltage, and when the second programming voltage is applied, the second bottom selection tube of the first storage cell string is programmed to the second threshold voltage, and the third threshold voltage is less than the second threshold voltage.

16. The memory according to claim 15, characterized in that: The first storage string and the second storage string are located in different finger storage areas.

17. A memory system, characterized in that: The memory system comprises: One or more memories as claimed in any one of claims 9 to 16; A memory controller is coupled to the memory and configured to control the memory.

Images