Substrate and method for producing a substrate
By forming a passivation layer on the conductive layer of the substrate, the problem of difficulty in completely removing pollutants in the structured conductive layer in the prior art is solved, the vulnerability of the substrate is reduced, and the stability of semiconductor structural elements is ensured. welding.
Patent Information
- Application Number
- CN202411097390.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-14
- Filing Date
- 2024-08-12
- Publication Date
- 2025-02-21
AI Technical Summary
Prior Art When manufacturing substrates of power semiconductor modules, it is difficult to completely remove contaminants in the structured conductive layer, resulting in the problem of accidental damage when welding semiconductor structural elements.
In the method of manufacturing the substrate, the first conductive layer is first formed on the first side of the dielectric insulating layer, and structured it by creating a coherent cutout in the first conductive layer. Then, the passivation layer is formed to cover the entire structured first conductive layer surface to prevent the contaminants from being activated.
By forming a passivation layer on the conductive layer of the substrate, the pollutants are effectively prevented from being activated, the vulnerability of the substrate is reduced, the stable welding of semiconductor structural elements is ensured, and the reliability of the substrate is improved.
Smart Images
Figure CN119495568A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a substrate and a method for producing a substrate, in particular a method for producing a substrate for a power semiconductor module. Background Art
[0002] Typically, a power semiconductor module has one or more substrates, which can be arranged on a base plate or on a cooling body. A semiconductor component having a plurality of controllable semiconductor components (e.g., IGBTs) is arranged on at least one of the substrates. Typically, the substrate has an electrically insulating substrate layer (e.g., a ceramic layer), a first conductive layer (e.g., a first metal layer), and a second conductive layer (e.g., a second metal layer), the first conductive layer being arranged on a first side of the substrate layer, and the second conductive layer being arranged on a second side of the substrate layer opposite to the first side. The controllable semiconductor components are arranged, for example, on the first conductive layer. The second conductive layer is typically connected to the base plate or the cooling body, that is, it is arranged between the base plate / cooling body and the electrically insulating substrate layer.
[0003] Typically, at least the first conductive layer is a structured layer. That is to say, the layer has a plurality of sections spaced apart from one another, which are separated from one another by continuous cuts in the first conductive layer. In order to produce different sections, the initially continuous conductive layer can be structured accordingly, for example etched. Before structuring, the continuous conductive layer has been contaminated. In addition, contaminants may also be generated during structuring, which may accidentally remain on the first conductive layer after the structuring process. However, it is not always possible to reliably and completely remove all contaminants in a specific cleaning step that usually follows structuring. If structural elements are subsequently welded to the contaminated first conductive layer, even a single minimal contaminant may cause accidental damage. Summary of the invention
[0004] There is therefore a need for a substrate and a method for producing a substrate which, despite the presence of possible contaminants, has the lowest possible susceptibility to damage.
[0005] The method for manufacturing a substrate for a semiconductor module comprises: forming a first conductive layer on a first side of a dielectric insulating layer; structuring the first conductive layer by producing one or more continuous cuts in the first conductive layer, the cuts extending from the upper surface of the first conductive layer to the dielectric insulating layer so as to completely separate different sections of the first conductive layer from each other; and forming a passivation layer, wherein the passivation layer covers the entire surface of the structured first conductive layer.
[0006] A substrate for a semiconductor module comprises a dielectric insulation layer, a first conductive layer arranged on a first side of the dielectric insulation layer, and a passivation layer, wherein the first conductive layer is a structured layer having one or more cutouts between different completely mutually separated sections of the first conductive layer, and the passivation layer covers the entire surface of the structured first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The invention is explained in more detail below based on examples and with reference to the accompanying drawings. Here, the same reference numerals represent the same elements. The schematic diagrams in the drawings are not necessarily to scale.
[0008] Figure 1 A cross section of a substrate is shown by way of example, the substrate having a semiconductor body arranged thereon;
[0009] Figure 2, including Figures 2A to 2D , showing a conventional method for manufacturing a substrate;
[0010] Figure 3, including Figure 3A and 3B , schematically illustrating steps of a method for manufacturing a substrate according to an example. DETAILED DESCRIPTION
[0011] In the detailed description below, how the present invention can be implemented is shown according to specific examples. It should be understood that, unless otherwise stated, the features of the different examples described herein can be combined with each other. If a certain element is referred to as a "first element", "second element", ... or the like, the expressions "first", "second", ... are only used to distinguish different elements from each other. The order or count is irrelevant to the expression. This means that, for example, even if there is no "first element", there can be a "second element".
[0012] Reference Figure 1 , a substrate 10 is shown. The substrate 10 has a dielectric insulation layer 11, a structured first conductive layer 111 and a (structured) second conductive layer 112. The first conductive layer 111 is arranged on a first side of the dielectric insulation layer 11, and the second conductive layer 112 is arranged on a second side of the dielectric insulation layer 11 opposite to the first side. Therefore, the dielectric insulation layer 11 is arranged between the first conductive layer 111 and the second conductive layer 112. However, here, the second conductive layer 112 is only optional. It is also possible to arrange only the first conductive layer 111 on the dielectric insulation layer 11 and completely omit the second conductive layer 112.
[0013] Each of the first conductive layer 111 and the second conductive layer 112 may consist of or have one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or any other metal alloy that remains in a solid state during operation of the power semiconductor module. The substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 consists of ceramic. Thus, for example, the dielectric insulating layer 11 may be a thin ceramic layer. For example, the ceramic of the dielectric insulating layer 11 may consist of or have one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other ceramic. For example, the dielectric insulating layer 11 may be made of or have one of the following materials: Al2O3, AlN or Si3N4. For example, the substrate 10 may be a so-called direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, an insulated metal substrate (IMS) or an active metal brazing (AMB) substrate. For example, the substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 may be made of or have a hardened resin.
[0014] In addition, refer to Figure 1 , one or more semiconductor bodies 20 can be arranged on the substrate 10. Each of the semiconductor bodies 20 on the substrate 10 can have a diode, an IGBT (Bipolar transistor mitisolierter Gate-Elektrode, a bipolar transistor with an insulated gate electrode), a MOSFET (Metall-Oxid-Halbleiter-Feldeffekttransistor, a metal oxide semiconductor field effect transistor), a JFET (Sperrschicht-Feldeffekttransistor, a junction field effect transistor), a HEMT (Transistor mithoher Elektronenbeweglichkeit, a high electron mobility transistor) or any other suitable controllable or non-controllable semiconductor structural element. The one or more semiconductor bodies 20 can form a semiconductor component (for example, one or more half bridges) on the substrate 10. Figure 1 Only two semiconductor bodies 20 are shown by way of example.
[0015] exist Figure 1 The first conductive layer 111 shown in is a structured layer. In this context, "structured layer" means that the first conductive layer 111 is not a continuous layer, but has interruptions between different sections of the layer. Different semiconductor bodies 20 can be arranged on the same section or on different sections of the first conductive layer 111. The different sections of the first conductive layer 111 may not have an electrical connection with each other, or may be electrically connected to each other, for example, by means of bonding wires or other connecting elements. Each of the semiconductor bodies 20 can be electrically and mechanically connected to the substrate 10 by means of a conductive connecting layer 22. By way of example, Figure 1 A substrate 10 is shown, which has a semiconductor body 20 arranged thereon and a connection layer 22. Such an electrically conductive connection layer 22 may be a solder layer, for example. The second electrically conductive layer 112, if present, may be a continuous layer or may also be a structured layer.
[0016] In order to connect the semiconductor body 20 to the substrate 10, the semiconductor body 20 is arranged on a surface (upper surface) of the substrate 10, wherein a connecting layer 22 is arranged between the substrate 10 and the semiconductor body 20. The upper surface of the substrate 10 is the surface of the first electrically conductive layer 111 facing away from the dielectric insulation layer 11. Alternatively or additionally, for example, one or more semiconductor bodies 20 can also be connected to the substrate 10 by means of bonding wires 24. For example, the substrate 10 with at least one semiconductor body 20 arranged thereon can be part of a power semiconductor module and arranged in a housing (not shown).
[0017] Referring now to FIG. 2 , a method for manufacturing substrate 10 is schematically illustrated. Figure 2A As shown, a first continuous conductive layer 111 is usually first applied to the dielectric insulating layer 11 (for example by a suitable deposition method). In the next method step, the first continuous conductive layer 111 is structured. Figure 2B . When the first conductive layer 111 is structured, a continuous cut is produced in the first conductive layer 111, which extends from the upper surface of the first conductive layer 111 to the dielectric insulating layer 11, so that different sections of the first conductive layer 111 are completely separated from each other. For example, the cut can be produced by means of a corresponding etching method (for example, a wet etching method or a dry etching method). However, after the etching process for structuring the first conductive layer 111, contaminants 30 that have reached the first conductive layer 111 before or during the structuring may remain on the first conductive layer 111, such as Figure 2BFor example, when etching the first conductive layer 111, chemicals such as copper chloride (CuCl), sodium hydroxide (NaOH) or sodium carbonate (Na2CO3) are used, and the chemicals may contaminate the surface of the first conductive layer 111 after the etching process.
[0018] To remove such contaminants 30, a subsequent cleaning process is usually performed, such as Figure 2C In principle, such a cleaning process can have one or more steps in which one or more of a plurality of chemical agents 34 (e.g. sulfuric acid H2SO4 or hydrogen peroxide H2O2) are sprayed onto the surface of the first conductive layer 111 and removed again in a subsequent swabbing step (not explicitly shown). Finally, a drying step can be performed. By means of this type of cleaning process, at least a large part of the contaminants 30 can be removed from the surface of the first conductive layer 111. However, as Figure 2C As schematically shown, individual contaminants 30 may also still remain on the surface after a thorough cleaning process.
[0019] Now refer to Figure 2D In a subsequent step, the semiconductor component 20 is connected to the possibly still contaminated surface of the first electrically conductive layer 111. For example, the semiconductor component 20 can be soldered to the first electrically conductive layer 111. For this purpose, for example, solder paste can be used, or also preformed solder pressings or solder preforms (so-called solder preforms). When using solder preforms, they are usually made in an environment containing formic acid. The soldering process is performed during the soldering process. Formic acid 38 can react with contaminants 30 remaining on the surface of the first electrically conductive layer 111, or formic acid 38 can "activate" the contaminants 30. This activation by formic acid 38 cannot usually be determined directly during the soldering step or directly after the soldering step. Usually, the activation can only be determined at a significantly later point in time (for example, after 12 hours at the earliest or after 24 hours at the earliest). Usually, the activation of contaminants 30 by formic acid 38 leads to clearly visible discoloration on the surface of the first electrically conductive layer 111. The activation of contaminants 30 by formic acid 38 may also lead to damage to the substrate 10 and therefore to faulty functioning of the semiconductor components arranged on the substrate 10.
[0020] For this reason, according to one example, before the component is applied to the substrate 10, a passivation layer 40 is also applied at least to the first electrically conductive layer 111. Figure 3A For example, Figure 3A The steps shown can be followed in the cleaning step (see Figure 2C ) and after applying the component to the substrate (see Figure 2D). That is, the passivation layer 40 is applied to the structured, but not yet completely equipped, first conductive layer 111. Since no components have yet been arranged on the first conductive layer 111, the entire first conductive layer 111 is covered by the passivation layer 40. The passivation layer 40 also completely covers the contaminants 30 that may remain on the surface of the first conductive layer 111. If the semiconductor component 20 is subsequently soldered in an environment containing formic acid, the passivation layer 40 is a barrier between the formic acid 38 and the contaminants 30, so that the contaminants 30 cannot be activated by the formic acid.
[0021] The thickness of the passivation layer 40 in the vertical direction y (perpendicular to the upper surface of the substrate 10) can be less than 5 μm or less than 1 μm. For example, the passivation layer 40 can be a so-called monolayer (monolage or monoschit). A monolayer (English: Monolayer) is a thin single layer composed of atoms, molecules or cells. The thickness of the monolayer corresponds to the thickness of a single atom, molecule or cell. For example, the passivation layer 40 can be a (mono) layer of organic molecules. Organic molecules can have functional groups, which are used to attach organic molecules to the surface of the first conductive layer 111. Functional groups are the following atomic groups in organic molecules: the atomic groups decisively affect their properties and reaction characteristics. This type of passivation layer 40 composed of organic molecules is in principle heat-resistant and is therefore not damaged during the subsequent welding process. However, at the same time, such a (thin) passivation layer 40 does not affect the subsequent welding process. This means that the semiconductor body 20 or any other element can be soldered to the substrate 10 in the same way as in the case of a substrate without the passivation layer 40. The passivation layer 40 has no influence on either the mechanical stability or the electrical conductivity of the connection produced.
[0022] For example, the passivation layer 40 can be produced by treating the substrate 10 with an HFE (Hydrofluorether) cleaning method. In principle, different HFE solutions are known as solvents for cleaning. The HFE cleaning method is usually a multi-stage (e.g., two-stage) cleaning method. For example, in a first step, the entire substrate 10 can be immersed in a first washing tank. For example, the first washing tank can contain a cleaning agent for removing flux residues (e.g., so-called "Topklean", which has a small proportion of HFE, such as <50% or <25%). In one or more further steps, the substrate 10 can be immersed in another solution of the HFE cleaning method, which can, for example, have a dominant proportion of HFE (e.g., >50%, or >70%). During such a multi-stage HFE cleaning method, for example, (during one or more of the individual cleaning steps), a thin layer containing phosphoric acid can be deposited on the first conductive layer 111, and the thin layer containing phosphoric acid forms the passivation layer 40. However, processing by means of the HFE cleaning method to deposit the passivation layer 40 composed of phosphate is only an example. For example, the organic molecule functional groups suitable for forming the passivation layer 40 may have one or more of the following substances: phosphate, thiol, silicone, carbonic acid, ester and nitride. Different functional groups can be applied to the surface of the first conductive layer 111 simultaneously in the same step or sequentially in consecutive steps.
[0023] As described above, for example, the passivation layer 40 can be produced by immersing the substrate 10 in a corresponding solution (dip coating method). However, this is only an example. Alternatively, the passivation layer 40 can also be manufactured, for example, by spraying (spray coating method), by a plasma-based deposition method (plasma coating method, English: plasma enhanced deposition, plasma enhanced deposition) or by vapor deposition (vapor deposition method).
[0024] For example, in Figure 3A 1 shows a substrate 10 for a semiconductor module. The substrate 10 comprises a dielectric insulation layer 11, a first conductive layer 111 arranged on a first side of the dielectric insulation layer 11, and a passivation layer 40, wherein the first conductive layer 111 is a structured layer having one or more cutouts between different completely mutually separated sections of the first conductive layer 111, and the passivation layer 40 covers the entire surface of the structured first conductive layer 111.
Claims
1. A method for producing a substrate (10) for a semiconductor module, wherein: The method has: forming a first conductive layer (111) on a first side of the dielectric insulating layer (11); The first conductive layer (111) is structured by producing one or more continuous cuts in the first conductive layer (111), the cuts extending from the upper surface of the first conductive layer (111) to the dielectric insulating layer (11), so as to completely separate different sections of the first conductive layer (111) from one another; A passivation layer (40) is formed, wherein the passivation layer (40) covers the entire surface of the structured first conductive layer (111).
2. The method according to claim 1, wherein: The passivation layer (40) is formed by: Applying the material by means of a spray coating method, or Apply the material by dipping, or Applying the material by means of a plasma coating method, or The material is applied by means of a vapor deposition method.
3. The method according to claim 1 or 2, wherein: The thickness of the passivation layer (40) is less than 5 μm or less than 1 μm.
4. The method according to any one of claims 1 to 3, wherein: The passivation layer (40) is a single layer.
5. A method according to any one of the preceding claims, wherein: The passivation layer (40) comprises organic molecules, and the organic molecules comprise at least one functional group.
6. The method according to claim 5, wherein: The at least one functional group has one or more of phosphate, thiol, silicone, carbonate, ester, and nitride.
7. A method according to any one of the preceding claims, wherein: The formation of the passivation layer (40) comprises treating the first conductive layer (111) by means of a hydrofluoroether (HFE) cleaning method.
8. A method according to any one of the preceding claims, wherein: The structuring of the first electrically conductive layer (111) comprises etching of the one or more cutouts by means of a wet etching method or a dry etching method.
9. The method according to any of the preceding claims, further comprising at least one cleaning step for removing contaminants (30) from the first conductive layer (111) after structuring the first conductive layer (111) and before forming the passivation layer (40).
10. The method according to claim 9, wherein: The passivation layer (40) is applied to the electrically conductive layer (111) in such a way that the passivation layer completely covers the contaminants (30) still remaining on the surface of the first electrically conductive layer (111) after the at least one cleaning step.
11. The method according to any of the preceding claims, further comprising, after shaping the passivation layer (40), applying one or more semiconductor components (20) to the first conductive layer (111) and the passivation layer (40) by means of a welding process.
12. The method according to claim 11, wherein: The welding process is carried out using welded prefabricated parts and in an environment containing formic acid.
13. A substrate (10) for a semiconductor module, wherein: The substrate (10) has A dielectric insulating layer (11); a first electrically conductive layer (111) arranged on a first side of the dielectric insulation layer (11), wherein the first electrically conductive layer (111) is a structured layer having one or more cutouts between different completely mutually separated sections of the first electrically conductive layer (111); and A passivation layer (40) covers the entire surface of the structured first conductive layer (111).